From patchwork Thu Dec 3 23:53:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11949925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49F6CC4361B for ; Thu, 3 Dec 2020 23:51:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E8DAB22285 for ; Thu, 3 Dec 2020 23:51:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E8DAB22285 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B1EB06E0E3; Thu, 3 Dec 2020 23:51:05 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6E1F26E0DE for ; Thu, 3 Dec 2020 23:51:04 +0000 (UTC) IronPort-SDR: cr6jFsk6XYy2V/8Nh0jw/YZF15k/DkSAsUoeP80TzErpt4rbL+leZl01T+ERXSX3VHu5wBnJC/ dNedZUaT9gaQ== X-IronPort-AV: E=McAfee;i="6000,8403,9824"; a="161067204" X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="161067204" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2020 15:51:03 -0800 IronPort-SDR: HLGIj796a9ezA+/32c47XNKMpeHTYVAUjWSinAkK/DOfIX68wV1hJ0ekazNB4b80phnl1L+um2 anQwbKj9qdNQ== X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="550716490" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 03 Dec 2020 15:51:03 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Dec 2020 15:53:50 -0800 Message-Id: <20201203235358.18041-1-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 1/9] drm/i915/display/vrr: Create VRR file and add VRR capability check X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We create a new file for all VRR related helpers. Also add a function to check vrr capability based on platform support, DPCD bits and EDID monitor range. v2: * Remove author (Jani N) * Define HAS_VRR (Jani N) * Ensure intel_dp can be obtained from conn (Jani N) Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 32 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 15 +++++++++++ drivers/gpu/drm/i915/i915_drv.h | 2 ++ 4 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index e5574e506a5c..3beeaf517191 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -249,6 +249,7 @@ i915-y += \ display/intel_sdvo.o \ display/intel_tv.o \ display/intel_vdsc.o \ + display/intel_vrr.o \ display/vlv_dsi.o \ display/vlv_dsi_pll.o diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c new file mode 100644 index 000000000000..8a427c152341 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2020 Intel Corporation + * + */ + +#include "i915_drv.h" +#include "intel_display_types.h" +#include "intel_vrr.h" + +bool intel_vrr_is_capable(struct drm_connector *connector) +{ + struct intel_dp *intel_dp; + const struct drm_display_info *info = &connector->display_info; + struct drm_i915_private *i915 = to_i915(connector->dev); + + if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && + connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) + return false; + + intel_dp = intel_attached_dp(to_intel_connector(connector)); + /* + * DP Sink is capable of Variable refresh video timings if + * Ignore MSA bit is set in DPCD. + * EDID monitor range also should be atleast 10 for reasonable + * Adaptive sync/ VRR end user experience. + */ + return HAS_VRR(i915) && + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; +} + diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h new file mode 100644 index 000000000000..3700acec5d09 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2019 Intel Corporation +*/ + +#ifndef __INTEL_VRR_H__ +#define __INTEL_VRR_H__ + +#include + +struct drm_connector; + +bool intel_vrr_is_capable(struct drm_connector *connector); + +#endif /* __INTEL_VRR_H__ */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fc1090c6889c..385aec744a64 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1753,6 +1753,8 @@ tgl_revids_get(struct drm_i915_private *dev_priv) #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) +#define HAS_VRR(i915) (INTEL_GEN(i915) >= 12) + /* Only valid when HAS_DISPLAY() is true */ #define INTEL_DISPLAY_ENABLED(dev_priv) \ (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) From patchwork Thu Dec 3 23:53:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11949929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DB81C433FE for ; Thu, 3 Dec 2020 23:51:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F24C322285 for ; Thu, 3 Dec 2020 23:51:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F24C322285 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8961B6E0E1; Thu, 3 Dec 2020 23:51:07 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9A4896E0DD for ; Thu, 3 Dec 2020 23:51:04 +0000 (UTC) IronPort-SDR: 1Qq+Y6GPfXtYdfGH0lp0duP9sc4pfOiQWnv4kIVsz+SwNmOqOYKJDdvgEOL9bpK1YVSrDmWgIx xm2hTy14RMkQ== X-IronPort-AV: E=McAfee;i="6000,8403,9824"; a="161067209" X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="161067209" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2020 15:51:03 -0800 IronPort-SDR: Ol0DhG4blTAQNa8O97cTs3Khi8DyE/tfsTX5wjMLxcwihMgek9UATDDWL+PCLaHf+l8b637kOw buK4anU1WbdA== X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="550716499" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 03 Dec 2020 15:51:03 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Dec 2020 15:53:51 -0800 Message-Id: <20201203235358.18041-2-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20201203235358.18041-1-manasi.d.navare@intel.com> References: <20201203235358.18041-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 2/9] drm/i915/display/dp: Attach and set drm connector VRR property X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Aditya Swarup This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v8: * Use HAS_VRR, remove drm_conn declaration (Jani N) * Fix typos in Comment (Jani N) v7: * Move the helper to separate file (Manasi) v6: * Remove unset of prop v5: * Fix the vrr prop not being set in kernel (Manasi) * Unset the prop on connector disconnect (Manasi) v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (Manasi) v2: * Just set this in intel_dp_get_modes instead of new hook (Jani) Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: Aditya Swarup Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2d4d5e95af84..6729e6290132 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -62,6 +62,7 @@ #include "intel_sideband.h" #include "intel_tc.h" #include "intel_vdsc.h" +#include "intel_vrr.h" #define DP_DPRX_ESI_LEN 14 @@ -6740,6 +6741,10 @@ static int intel_dp_get_modes(struct drm_connector *connector) edid = intel_connector->detect_edid; if (edid) { int ret = intel_connector_update_modes(connector, edid); + + if (intel_vrr_is_capable(connector)) + drm_connector_set_vrr_capable_property(connector, + true); if (ret) return ret; } @@ -7224,6 +7229,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; } + + if (HAS_VRR(dev_priv)) + drm_connector_attach_vrr_capable_property(connector); } static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 8a427c152341..869e41aa8396 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -20,10 +20,10 @@ bool intel_vrr_is_capable(struct drm_connector *connector) intel_dp = intel_attached_dp(to_intel_connector(connector)); /* - * DP Sink is capable of Variable refresh video timings if + * DP Sink is capable of VRR video timings if * Ignore MSA bit is set in DPCD. * EDID monitor range also should be atleast 10 for reasonable - * Adaptive sync/ VRR end user experience. + * Adaptive Sync or Variable Refresh Rate end user experience. */ return HAS_VRR(i915) && drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && From patchwork Thu Dec 3 23:53:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11949933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA5CDC4361B for ; Thu, 3 Dec 2020 23:51:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 977BE22285 for ; Thu, 3 Dec 2020 23:51:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 977BE22285 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4FEAC6E0E9; Thu, 3 Dec 2020 23:51:08 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 23E356E0E1 for ; Thu, 3 Dec 2020 23:51:05 +0000 (UTC) IronPort-SDR: cHiR0XHHJQCWAm1OHAcPcXJGfOGl+0lnbqCyIqXY7oL2/NQnej8CkP4iyiBMlabEODzgjHxqh8 TtzlwwKltyXw== X-IronPort-AV: E=McAfee;i="6000,8403,9824"; a="161067205" X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="161067205" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2020 15:51:03 -0800 IronPort-SDR: qjaCspDh1y0MgOdYY5yDsZ9WR1t96cKcCEb/rYMGtJt8vXVDzl7dqhx1+6n6sLdnoCRi/9NqOb w1mNK/xMj2PA== X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="550716494" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 03 Dec 2020 15:51:03 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Dec 2020 15:53:52 -0800 Message-Id: <20201203235358.18041-3-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20201203235358.18041-1-manasi.d.navare@intel.com> References: <20201203235358.18041-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 3/9] drm/i915/display/dp: Compute VRR state in atomic_check X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This forces a complete modeset if vrr drm crtc state goes from enabled to disabled and vice versa. This patch also computes vrr state variables from the mode timings and based on the vrr property set by userspace as well as hardware's vrr capability. v2: *Rebase v3: * Vmin = max (vtotal, vmin) (Manasi) v4: * set crtc_state->vrr.enable = 0 for disable request v5: * drm_dbg_kms, squash crtc states def patch (Jani N) v6: * Move vrr modeset check to separate function (Jani N) Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++ .../drm/i915/display/intel_display_types.h | 7 +++ drivers/gpu/drm/i915/display/intel_dp.c | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 51 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 7 +++ 5 files changed, 73 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6e5b93f6a25e..fa452eb3adb8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -57,6 +57,7 @@ #include "display/intel_sdvo.h" #include "display/intel_tv.h" #include "display/intel_vdsc.h" +#include "display/intel_vrr.h" #include "gt/intel_rps.h" @@ -14383,6 +14384,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(mst_master_transcoder); + PIPE_CONF_CHECK_BOOL(vrr.enable); + PIPE_CONF_CHECK_I(vrr.vtotalmin); + PIPE_CONF_CHECK_I(vrr.vtotalmax); + #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_BOOL @@ -15509,6 +15514,8 @@ static int intel_atomic_check(struct drm_device *dev, new_crtc_state->uapi.mode_changed = true; } + intel_vrr_check_modeset(state); + ret = drm_atomic_helper_check_modeset(dev, &state->base); if (ret) goto fail; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1fa0246b3a82..f5fb5f109a89 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1124,6 +1124,13 @@ struct intel_crtc_state { struct intel_dsb *dsb; u32 psr2_man_track_ctl; + + /* Variable Refresh Rate state */ + struct { + bool enable; + u16 vtotalmin; + u16 vtotalmax; + } vrr; }; enum intel_pipe_crc_source { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6729e6290132..b5abde0351c2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2860,6 +2860,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, if (!HAS_DDI(dev_priv)) intel_dp_set_clock(encoder, pipe_config); + intel_vrr_compute_config(intel_dp, pipe_config); intel_psr_compute_config(intel_dp, pipe_config); intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp, constant_n); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 869e41aa8396..09dcf6f1c4d9 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -30,3 +30,54 @@ bool intel_vrr_is_capable(struct drm_connector *connector) info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; } +void +intel_vrr_check_modeset(struct intel_atomic_state *state) +{ + int i; + struct intel_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_crtc *crtc; + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (new_crtc_state->uapi.vrr_enabled != + old_crtc_state->uapi.vrr_enabled) + new_crtc_state->uapi.mode_changed = true; + } +} + +void +intel_vrr_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + const struct drm_display_info *info = &connector->display_info; + + if (!intel_vrr_is_capable(connector)) + return; + + if (!crtc_state->uapi.vrr_enabled) { + crtc_state->vrr.enable = false; + return; + } + + crtc_state->vrr.enable = true; + crtc_state->vrr.vtotalmin = + max_t(u16, adjusted_mode->crtc_vtotal, + DIV_ROUND_CLOSEST(adjusted_mode->crtc_clock * 1000, + adjusted_mode->crtc_htotal * + info->monitor_range.max_vfreq)); + crtc_state->vrr.vtotalmax = + max_t(u16, adjusted_mode->crtc_vtotal, + DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, + adjusted_mode->crtc_htotal * + info->monitor_range.min_vfreq)); + + drm_dbg_kms(&i915->drm, + "VRR Config: Enable = %s Vtotal Min = %d Vtotal Max = %d\n", + yesno(crtc_state->vrr.enable), crtc_state->vrr.vtotalmin, + crtc_state->vrr.vtotalmax); +} + diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 3700acec5d09..3f08c32d1afe 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -9,7 +9,14 @@ #include struct drm_connector; +struct intel_atomic_state; +struct intel_crtc; +struct intel_crtc_state; +struct intel_dp; bool intel_vrr_is_capable(struct drm_connector *connector); +void intel_vrr_check_modeset(struct intel_atomic_state *state); +void intel_vrr_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Thu Dec 3 23:53:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11949923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A24B9C4361A for ; Thu, 3 Dec 2020 23:51:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4645D22285 for ; Thu, 3 Dec 2020 23:51:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4645D22285 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 30FC66E0DD; Thu, 3 Dec 2020 23:51:05 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id DCDE46E0DD for ; Thu, 3 Dec 2020 23:51:03 +0000 (UTC) IronPort-SDR: W0xzclSGxKYQ+wu+lDKt+YTjnCk1EcEb4rbwAhhhzrwgNNVrCPTbEC2zlJL9jbfaLPFP5F77Aj jzE2F/zQP38Q== X-IronPort-AV: E=McAfee;i="6000,8403,9824"; a="161067206" X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="161067206" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2020 15:51:03 -0800 IronPort-SDR: 4ccXkzf9dvcJ4dKwVViV0z/3It69BZ5ZuKjf/TSBCdLxRmRCmRLrMgrVqcOsE7UnJquxrwRTd5 RCZd4f/0zpdQ== X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="550716497" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 03 Dec 2020 15:51:03 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Dec 2020 15:53:53 -0800 Message-Id: <20201203235358.18041-4-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20201203235358.18041-1-manasi.d.navare@intel.com> References: <20201203235358.18041-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 4/9] drm/i915/display/dp: Do not enable PSR if VRR is enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Even though our HW supports PSR + VRR, the available panels do not work reliably with PSR and VRR together. So if user requested VRR and is supported by HW enable that and do not enable PSR in that case. Cc: Ville Syrjälä Cc: Gwan-gyeong Mun Cc: Imre Deak Signed-off-by: Manasi Navare Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d9a395c486d3..4bbd92135651 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -811,6 +811,13 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, &crtc_state->hw.adjusted_mode; int psr_setup_time; + /* + * Current PSR panels dont work reliably with VRR enabled + * So if VRR is enabled, do not enable PSR. + */ + if (crtc_state->vrr.enable) + return; + if (!CAN_PSR(dev_priv)) return; From patchwork Thu Dec 3 23:53:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11949935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9849C433FE for ; Thu, 3 Dec 2020 23:51:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 559EA22285 for ; Thu, 3 Dec 2020 23:51:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 559EA22285 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 071F76E0E5; Thu, 3 Dec 2020 23:51:08 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id E083C6E0DD for ; Thu, 3 Dec 2020 23:51:04 +0000 (UTC) IronPort-SDR: zdbkA1Erbr6mUaq/lxnrOA0oUehxn9phw9QGFkWbmOwulglghen10CzXQP/lqtCWDd8BkfWmv/ u123MN7qFU5w== X-IronPort-AV: E=McAfee;i="6000,8403,9824"; a="161067207" X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="161067207" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2020 15:51:03 -0800 IronPort-SDR: hEHrkBAgwR5tm0pVls17zx4Eetdr0UtzAFnlzHvLhiLgcvrxbxdzXzDLo6cmLGSr1UnKGkI+S0 MLtgXa1AGmkw== X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="550716502" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 03 Dec 2020 15:51:03 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Dec 2020 15:53:54 -0800 Message-Id: <20201203235358.18041-5-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20201203235358.18041-1-manasi.d.navare@intel.com> References: <20201203235358.18041-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 5/9] drm/i915/display/vrr: Configure and enable VRR in modeset enable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This patch computes the VRR parameters from VRR crtc states and configures them in VRR registers during CRTC enable in the modeset enable sequence. v2: * Remove initialization to 0 (Jani N) * Use correct pipe %c (Jani N) Cc: Ville Syrjälä Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++ drivers/gpu/drm/i915/display/intel_vrr.c | 33 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 3 +++ 3 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5193473c838c..48467c6abb37 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -50,6 +50,7 @@ #include "intel_sprite.h" #include "intel_tc.h" #include "intel_vdsc.h" +#include "intel_vrr.h" struct ddi_buf_trans { u32 trans1; /* balance leg enable, de-emph level */ @@ -4245,6 +4246,8 @@ static void intel_enable_ddi(struct intel_atomic_state *state, if (!crtc_state->bigjoiner_slave) intel_ddi_enable_transcoder_func(encoder, crtc_state); + intel_vrr_enable(encoder, crtc_state); + intel_enable_pipe(crtc_state); intel_crtc_vblank_on(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 09dcf6f1c4d9..9dec01695773 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -81,3 +81,36 @@ intel_vrr_compute_config(struct intel_dp *intel_dp, crtc_state->vrr.vtotalmax); } +void intel_vrr_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum pipe pipe = crtc->pipe; + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + u32 trans_vrr_ctl; + u16 framestart_to_pipelinefull_linecnt; + + if (!crtc_state->vrr.enable) + return; + + framestart_to_pipelinefull_linecnt = + min_t(u16, 255, (crtc_state->vrr.vtotalmin - adjusted_mode->crtc_vdisplay - 4)); + + trans_vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_IGN_MAX_SHIFT | + VRR_CTL_FLIP_LINE_EN | VRR_CTL_LINE_COUNT(framestart_to_pipelinefull_linecnt) | + VRR_CTL_SW_FULLLINE_COUNT; + + intel_de_write(dev_priv, TRANS_VRR_VMIN(pipe), crtc_state->vrr.vtotalmin - 2); + intel_de_write(dev_priv, TRANS_VRR_VMAX(pipe), crtc_state->vrr.vtotalmax - 1); + intel_de_write(dev_priv, TRANS_VRR_CTL(pipe), trans_vrr_ctl); + intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(pipe), crtc_state->vrr.vtotalmin - 1); + intel_de_write(dev_priv, TRANS_PUSH(pipe), TRANS_PUSH_EN); + + drm_dbg_kms(&dev_priv->drm, "Enabling VRR on pipe %c\n", pipe_name(pipe)); + drm_dbg_kms(&dev_priv->drm, "VRR Parameters: Vtotal Min = %d, Max = %d Flipline Count = %d, CTL Reg = 0x%08x, TRANS PUSH reg = 0x%08x", + crtc_state->vrr.vtotalmin - 1, crtc_state->vrr.vtotalmax, + crtc_state->vrr.vtotalmin, trans_vrr_ctl, + TRANS_PUSH_EN); +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 3f08c32d1afe..97bbbfb4c33b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -13,10 +13,13 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_dp; +struct intel_encoder; bool intel_vrr_is_capable(struct drm_connector *connector); void intel_vrr_check_modeset(struct intel_atomic_state *state); void intel_vrr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); +void intel_vrr_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Thu Dec 3 23:53:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11949931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 214C9C4361A for ; Thu, 3 Dec 2020 23:51:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C118522285 for ; Thu, 3 Dec 2020 23:51:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C118522285 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA0E46E0E4; Thu, 3 Dec 2020 23:51:07 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id F2C9A6E0DF for ; Thu, 3 Dec 2020 23:51:04 +0000 (UTC) IronPort-SDR: bcNq+EQ6lPfUT5t0f1EWl+s5dl58betssgKlmHgBNvF/ILxLTS2VZ+309Puyy7KKD8WWd9r1hW YinZdkGQvUcA== X-IronPort-AV: E=McAfee;i="6000,8403,9824"; a="161067208" X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="161067208" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2020 15:51:03 -0800 IronPort-SDR: o4MSW7e1g9kmXPv5Q4GbfMDFEYneGg6OYevAE9WpsXSDta0M+9YKu6OWqD2f/ACfWaOyJmG2Ig PFZNo/44IV/Q== X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="550716505" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 03 Dec 2020 15:51:03 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Dec 2020 15:53:55 -0800 Message-Id: <20201203235358.18041-6-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20201203235358.18041-1-manasi.d.navare@intel.com> References: <20201203235358.18041-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 6/9] drm/i915/display/vrr: Send VRR push to flip the frame X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" VRR achieves vblank stretching using the HW PUSH functionality. So once the VRR is enabled during modeset then for each flip request from userspace, in the atomic tail pipe_update_end() we need to set the VRR push bit in HW for it to terminate the vblank at configured flipline or anytime after flipline or latest at the Vmax. Also in case of VRR, we need to stall the double buffer updates and PUSH if too close to the Vmax. The HW clears the PUSH bit after the double buffer updates are completed. v2: * Move send push to after irq en (Manasi) * Call send push unconditionally (Jani N) v3: * Stall w.r.t Vrr vmax (Manasi, Gary Smith) Cc: Ville Syrjälä Cc: Gary Smith Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++++++++++ drivers/gpu/drm/i915/display/intel_vrr.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index b7e208816074..744f2ffec1fd 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -49,6 +49,7 @@ #include "intel_psr.h" #include "intel_dsi.h" #include "intel_sprite.h" +#include "intel_vrr.h" int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, int usecs) @@ -98,6 +99,13 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) VBLANK_EVASION_TIME_US); max = vblank_start - 1; + /* In case of VRR, we stall the Push and updates if too close to Vmax */ + if (new_crtc_state->vrr.enable) { + min = new_crtc_state->vrr.vtotalmax - intel_usecs_to_scanlines(adjusted_mode, + VBLANK_EVASION_TIME_US); + max = new_crtc_state->vrr.vtotalmax - 1; + } + if (min <= 0 || max <= 0) goto irq_disable; @@ -257,6 +265,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) local_irq_enable(); + /* Send VRR Push to terminate Vblank */ + intel_vrr_send_push(new_crtc_state); + if (intel_vgpu_active(dev_priv)) return; diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 9dec01695773..3597a53887dd 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -114,3 +114,22 @@ void intel_vrr_enable(struct intel_encoder *encoder, crtc_state->vrr.vtotalmin, trans_vrr_ctl, TRANS_PUSH_EN); } + +void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + u32 trans_push; + + if (!crtc_state->vrr.enable) + return; + + trans_push = intel_de_read(dev_priv, TRANS_PUSH(pipe)); + trans_push |= TRANS_PUSH_SEND; + intel_de_write(dev_priv, TRANS_PUSH(pipe), trans_push); + drm_WARN_ON(&dev_priv->drm, !(trans_push & TRANS_PUSH_EN)); + + drm_dbg_kms(&dev_priv->drm, "Sending VRR Push on pipe %c\n", + pipe_name(pipe)); +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 97bbbfb4c33b..112e40147e35 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -21,5 +21,6 @@ void intel_vrr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); void intel_vrr_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); +void intel_vrr_send_push(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Thu Dec 3 23:53:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11949937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A9FAC4167B for ; Thu, 3 Dec 2020 23:51:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 03C3022285 for ; Thu, 3 Dec 2020 23:51:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 03C3022285 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 672006E0E6; Thu, 3 Dec 2020 23:51:10 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id C6B246E0DE for ; Thu, 3 Dec 2020 23:51:04 +0000 (UTC) IronPort-SDR: 7ciwHQwqnli0Z7mpmnbBPlIwRJAFPdkoM5Ucl90j4RnKav/4T5ghXo0eoJnYpE3Veu6K1a1XgK 9frNhYeKISjA== X-IronPort-AV: E=McAfee;i="6000,8403,9824"; a="161067210" X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="161067210" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2020 15:51:03 -0800 IronPort-SDR: k2ih0vnL7aTaihN14woZr+0tPj562ljw4BBbCIWq+Wony/bzH8WlVJdGcFKTjbOQ3q6ElqFhgI vy24N0nvas1w== X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="550716508" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 03 Dec 2020 15:51:03 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Dec 2020 15:53:56 -0800 Message-Id: <20201203235358.18041-7-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20201203235358.18041-1-manasi.d.navare@intel.com> References: <20201203235358.18041-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 7/9] drm/i915/display/vrr: Disable VRR in modeset disable path X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This patch disables the VRR enable and VRR PUSH bits in the HW during commit modeset disable sequence. Thsi disable will happen when the port is disabled or when the userspace sets VRR prop to false and requests to disable VRR. v2: * Use intel_de_rmw (Jani N) Cc: Ville Syrjälä Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/display/intel_vrr.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 48467c6abb37..07fb7296c8c7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3995,6 +3995,8 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state, intel_disable_pipe(old_crtc_state); + intel_vrr_disable(old_crtc_state); + intel_ddi_disable_transcoder_func(old_crtc_state); intel_dsc_disable(old_crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 3597a53887dd..a3edfadb50f1 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -133,3 +133,19 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) drm_dbg_kms(&dev_priv->drm, "Sending VRR Push on pipe %c\n", pipe_name(pipe)); } + +void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + + if (!old_crtc_state->vrr.enable) + return; + + intel_de_rmw(dev_priv, TRANS_VRR_CTL(pipe), VRR_CTL_FLIP_LINE_EN | VRR_CTL_VRR_ENABLE, 0); + intel_de_rmw(dev_priv, TRANS_PUSH(pipe), TRANS_PUSH_EN, 0); + + drm_dbg_kms(&dev_priv->drm, "Disabling VRR on pipe %c\n", + pipe_name(pipe)); +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 112e40147e35..5d3def024006 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -22,5 +22,6 @@ void intel_vrr_compute_config(struct intel_dp *intel_dp, void intel_vrr_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_vrr_send_push(const struct intel_crtc_state *crtc_state); +void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state); #endif /* __INTEL_VRR_H__ */ From patchwork Thu Dec 3 23:53:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11949921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D72BC4361A for ; Thu, 3 Dec 2020 23:51:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 041DE22285 for ; Thu, 3 Dec 2020 23:51:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 041DE22285 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 23A826E0DE; Thu, 3 Dec 2020 23:51:05 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1558D6E0DE for ; Thu, 3 Dec 2020 23:51:04 +0000 (UTC) IronPort-SDR: ujSaxAMpfpmX/rIWpZicyYFPH/r3c2eoX8VtAoktY7N86Agiltu2zCA3tn4cxzzNt9QVoFUvAM jQh7YjOLG78Q== X-IronPort-AV: E=McAfee;i="6000,8403,9824"; a="161067212" X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="161067212" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2020 15:51:03 -0800 IronPort-SDR: TB2tPq018SCv/L2qDthc2m6bNiyOdOYrk9JvW3mYQ1mxiEiZhY69xR1zF9vEqvw0jKxhYk2FAN okfUhB90BmCA== X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="550716511" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 03 Dec 2020 15:51:03 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Dec 2020 15:53:57 -0800 Message-Id: <20201203235358.18041-8-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20201203235358.18041-1-manasi.d.navare@intel.com> References: <20201203235358.18041-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 8/9] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If VRR is enabled, the sink should ignore MSA parameters and regenerate incoming video stream without depending on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN bit if VRR is enabled. Reset this bit on VRR disable. Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_ddi.c | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 07fb7296c8c7..7db49abd5973 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3486,6 +3486,22 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, return DP_TP_STATUS(encoder->port); } +static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + bool enable) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (!crtc_state->vrr.enable) + return; + + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, + enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) + drm_dbg_kms(&i915->drm, + "Failed to set MSA_TIMING_PAR_IGNORE %s in the sink\n", + enable ? "enable" : "disable"); +} + static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { @@ -3659,6 +3675,12 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_dp_sink_set_fec_ready(intel_dp, crtc_state); + /* + * Sink device should ignore MSA parameters and regenerate + * incoming video stream in case of VRR/Adaptive Sync + */ + intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, crtc_state, true); + /* * 7.i Follow DisplayPort specification training sequence (see notes for * failure handling) @@ -4286,6 +4308,9 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state, /* Disable the decompression in DP Sink */ intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, false); + /* Disable Ignore_MSA bit in DP Sink */ + intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, + false); } static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, From patchwork Thu Dec 3 23:53:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11949927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEB09C4361A for ; Thu, 3 Dec 2020 23:51:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 579192245C for ; Thu, 3 Dec 2020 23:51:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 579192245C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7D2226E0DF; Thu, 3 Dec 2020 23:51:07 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 41D7E6E0DD for ; Thu, 3 Dec 2020 23:51:04 +0000 (UTC) IronPort-SDR: rkj3SZHxmrBsxSbgde0oKSAIjHTTo1PpP30/WENLbPq6glIiJdFTK+coqte1/9Jm1TI01pMVaL hdXfiuJtOyLA== X-IronPort-AV: E=McAfee;i="6000,8403,9824"; a="161067213" X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="161067213" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2020 15:51:03 -0800 IronPort-SDR: XY903eZvL9TUqWmAQuyGgAu1IsgAxFh6SYg9KLF4TlVNgRZvEXLvIKjDA1bsfGMYm7h17ZqysU 4Vi0V22P9XzQ== X-IronPort-AV: E=Sophos;i="5.78,390,1599548400"; d="scan'208";a="550716513" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 03 Dec 2020 15:51:03 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Dec 2020 15:53:58 -0800 Message-Id: <20201203235358.18041-9-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20201203235358.18041-1-manasi.d.navare@intel.com> References: <20201203235358.18041-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 9/9] drm/i915/display: Add HW state readout for VRR X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This functions gets the VRR config from the VRR registers to match the crtc state variables for VRR. v2: * Rebase (Manasi) * Use HAS_VRR (Jani N) Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.h | 3 +++ 3 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index fa452eb3adb8..d5b934ecb30c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -11449,6 +11449,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, intel_get_transcoder_timings(crtc, pipe_config); } + if (HAS_VRR(dev_priv)) + intel_vrr_get_config(crtc, pipe_config); + intel_get_pipe_src_size(crtc, pipe_config); if (IS_HASWELL(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index a3edfadb50f1..9b867f629f86 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -149,3 +149,20 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) drm_dbg_kms(&dev_priv->drm, "Disabling VRR on pipe %c\n", pipe_name(pipe)); } + +void intel_vrr_get_config(struct intel_crtc *crtc, + struct intel_crtc_state *pipe_config) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum pipe pipe = crtc->pipe; + u32 trans_vrr_ctl; + + trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(pipe)); + pipe_config->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (!pipe_config->vrr.enable) + return; + + pipe_config->vrr.vtotalmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(pipe)) + 1; + pipe_config->vrr.vtotalmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(pipe)) + 1; +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 5d3def024006..ae01eef6947f 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -14,6 +14,7 @@ struct intel_crtc; struct intel_crtc_state; struct intel_dp; struct intel_encoder; +struct intel_crtc; bool intel_vrr_is_capable(struct drm_connector *connector); void intel_vrr_check_modeset(struct intel_atomic_state *state); @@ -23,5 +24,7 @@ void intel_vrr_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_vrr_send_push(const struct intel_crtc_state *crtc_state); void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state); +void intel_vrr_get_config(struct intel_crtc *crtc, + struct intel_crtc_state *pipe_config); #endif /* __INTEL_VRR_H__ */