From patchwork Sun Dec 6 23:39:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCF05C4167B for ; Sun, 6 Dec 2020 23:40:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD26A23123 for ; Sun, 6 Dec 2020 23:40:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728288AbgLFXkj (ORCPT ); Sun, 6 Dec 2020 18:40:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726046AbgLFXkj (ORCPT ); Sun, 6 Dec 2020 18:40:39 -0500 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDA16C0613D1 for ; Sun, 6 Dec 2020 15:39:58 -0800 (PST) Received: by mail-wm1-x341.google.com with SMTP id h21so12088886wmb.2 for ; Sun, 06 Dec 2020 15:39:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k2eeYOSwnhkGWaF7Gqxwyv5DCY5GnWH/sPRKUd7DVSw=; b=lCV2tVlTBuYcB4tKKpyVcUZy/dLgDw+fUlNSeB8cvB+ESWGUKwbBTmkJ9hSkZxaaLj gzZNP95EGEBFqJtamjQICHTD7pQe6Brz85Df8Miuns1r2Qmua1gMgWA7Dxfn8LAHXzwI 7SkpOkiwubtSKtkoqhR4BBr5TSsCjl5kPaq7g7M7wyQ8UjYtS1uw3SsWfMr/AhL+FrlG YA49GUPLOV2H3wYgykcJcK28LQcDJhoItqoP2Wi2HiAgfvpUjw7EFMpZ6/B46cxfQE0W 629C1e2wy/sm6XEp9hrkrAv3qTp7Ye5JCxZUxOwTRL869MEaf/eeiJPwjSVcl840NXGm zwew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=k2eeYOSwnhkGWaF7Gqxwyv5DCY5GnWH/sPRKUd7DVSw=; b=euRo/4/5dTC8Lxm/cnsk8GJ99te1QvoOL6ueIkRoWNNJskCG6oqo95h0zYuMqV4S+h awpMnOtRyexNry/W2bVktykL43OxOSIHw5MuwgWxJY5+b4cbugXexWetOhI6vcnlxY5Q JlrHiuI9ASoWJpNnai2ttqFV0UWYGp7ODh5YFoEqo08K6cwqYAYyAaMff3UtrXJ0FDGH gE4gOcURh6fudtF1QAzNh7381emRLivQV2y1yhve/SRWQatr1KTrbFEiFTGnWYbxhQTu 3k7IcFckBEt+VC8yhZFQzYzpB7Qny9zQMvDFJ95y5SbzHH/emtqYXg/qb5TuSebIEuh9 gLDA== X-Gm-Message-State: AOAM532oqRPI9prdajdDRQrrJSp15Qa6sER0jRBBPERiwmMq+t7cx5r2 Bk5Vka/zbZCHJgRI24VZFLXyiverhPw= X-Google-Smtp-Source: ABdhPJy3xT0vKlHKdf2n/udhIrOm526CJP1KpDJx6fJG7TXfFZ2bHXieBHHTpA97RbYwzkbqLswFEQ== X-Received: by 2002:a1c:2b05:: with SMTP id r5mr15395706wmr.179.1607297997495; Sun, 06 Dec 2020 15:39:57 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id n17sm3479198wmc.33.2020.12.06.15.39.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:39:56 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 01/19] hw/mips: Move address translation helpers to target/mips/ Date: Mon, 7 Dec 2020 00:39:31 +0100 Message-Id: <20201206233949.3783184-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Address translation is an architectural thing (not hardware related). Move the helpers from hw/ to target/. As physical address and KVM are specific to system mode emulation, restrict this file to softmmu, so it doesn't get compiled for user-mode emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/mips/cpudevs.h | 7 ------- target/mips/cpu.h | 8 ++++++++ hw/mips/boston.c | 1 - {hw => target}/mips/addr.c | 2 +- target/mips/translate.c | 2 -- hw/mips/meson.build | 2 +- target/mips/meson.build | 1 + 7 files changed, 11 insertions(+), 12 deletions(-) rename {hw => target}/mips/addr.c (98%) diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h index 291f59281a0..f7c9728fa9f 100644 --- a/include/hw/mips/cpudevs.h +++ b/include/hw/mips/cpudevs.h @@ -5,13 +5,6 @@ /* Definitions for MIPS CPU internal devices. */ -/* addr.c */ -uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); -uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); -uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); -bool mips_um_ksegs_enabled(void); -void mips_um_ksegs_enable(void); - /* mips_int.c */ void cpu_mips_irq_init_cpu(MIPSCPU *cpu); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 23f8c6f96cd..313e3252cbb 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1290,6 +1290,14 @@ bool cpu_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); +/* addr.c */ +uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); +uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); + +uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); +bool mips_um_ksegs_enabled(void); +void mips_um_ksegs_enable(void); + /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 3d40867dc4c..91183363ff3 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -28,7 +28,6 @@ #include "hw/loader.h" #include "hw/loader-fit.h" #include "hw/mips/cps.h" -#include "hw/mips/cpudevs.h" #include "hw/pci-host/xilinx-pcie.h" #include "hw/qdev-clock.h" #include "hw/qdev-properties.h" diff --git a/hw/mips/addr.c b/target/mips/addr.c similarity index 98% rename from hw/mips/addr.c rename to target/mips/addr.c index 2f138fe1ea8..27a6036c451 100644 --- a/hw/mips/addr.c +++ b/target/mips/addr.c @@ -21,7 +21,7 @@ */ #include "qemu/osdep.h" -#include "hw/mips/cpudevs.h" +#include "cpu.h" static int mips_um_ksegs; diff --git a/target/mips/translate.c b/target/mips/translate.c index c64a1bc42e1..87dc38c0683 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28,8 +28,6 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" -#include "hw/mips/cpudevs.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "hw/semihosting/semihost.h" diff --git a/hw/mips/meson.build b/hw/mips/meson.build index bcdf96be69f..77b4d8f365e 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,5 +1,5 @@ mips_ss = ss.source_set() -mips_ss.add(files('addr.c', 'mips_int.c')) +mips_ss.add(files('mips_int.c')) mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c')) diff --git a/target/mips/meson.build b/target/mips/meson.build index fa1f024e782..d980240f9e3 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -15,6 +15,7 @@ mips_softmmu_ss = ss.source_set() mips_softmmu_ss.add(files( + 'addr.c', 'cp0_timer.c', 'machine.c', 'mips-semi.c', From patchwork Sun Dec 6 23:39:32 2020 Content-Type: text/plain; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id n126sm12302988wmn.21.2020.12.06.15.40.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:02 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 02/19] target/mips: Remove unused headers from translate.c Date: Mon, 7 Dec 2020 00:39:32 +0100 Message-Id: <20201206233949.3783184-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 87dc38c0683..346635370c4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24,8 +24,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "disas/disas.h" -#include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" From patchwork Sun Dec 6 23:39:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF90FC433FE for ; Sun, 6 Dec 2020 23:41:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 918D2208DB for ; Sun, 6 Dec 2020 23:41:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728339AbgLFXkz (ORCPT ); Sun, 6 Dec 2020 18:40:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726046AbgLFXky (ORCPT ); Sun, 6 Dec 2020 18:40:54 -0500 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C48CAC0613D3 for ; Sun, 6 Dec 2020 15:40:08 -0800 (PST) Received: by mail-wm1-x344.google.com with SMTP id h21so12089069wmb.2 for ; Sun, 06 Dec 2020 15:40:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XM32sGEjA2NXWYAKzKhgTdbipbFOwi76R5qWtxt4kUc=; b=Ncs0+H+gQE1fr7o37GxbbjzKAZ+KHNVELm8jGKBgLMS+T/eVT5HpkqSY3FCkmUAwnt VZXhyiZBQqwAByA1gEh9z5JxlveDyWZhhx1CYEAbGocruA52FLckPeYZe5+lidCB9L/d ztwDbNjqxhB0/xUuyb5MDVTp5Opjg6Gq6aJL1sG21723zjoXQQdpu0yu2x153r2Fc9NM U4j37LoiN9DzIwlIbY5QrdEO6U6pqLpnVaKZhcZwm9NwIBMsNR8rbPdLZ6ETAtC6pDh/ 8QfoR59ntau1MwlvfkhXk42Z/vZRCzRQXPSol/45BGTF9jneakXaZEcL/s8pc4gyWzK9 CvoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=XM32sGEjA2NXWYAKzKhgTdbipbFOwi76R5qWtxt4kUc=; b=r5u8ZKA8+eTLlgKuw8c8sBY36Kv+PS0KbIxDjuTESx697oCvyLLq6q4qdibW+aOyka hXji4uH4Kn7h22NvZ+gqRNZ3WZzlH8bVf0uR9qoohxBIXPaJ/ZQZ59DESm2LlM0kz2QV RiAkZGPujV5OdYWH1Q7VEDnsuqYbxKHu9zATdKsdmW30HJBgzVja2X/PY7M2OeoBVkjj BTHPgwusIgP13RK8k2lCS99luirBBTsZmwNGDUo9X9BkJX50Jc1Mm9w9IcNpabY61Tjg MBG3D1P3iIfvwXZOpua3LnaKHESqw65kaDZDg+9hZaDDjkS5Uj0C0nWb1OuxtqNZ/Zj0 X/jA== X-Gm-Message-State: AOAM532+EL79FVH+fDtq6KdW/EoyTjhHMgW63wVgSkmw46979zkNxjcs qHUNqqEr9fonNHMv78SRw9s= X-Google-Smtp-Source: ABdhPJxlh5IC/oOpnriO1JnFl0cFXBOn29HlgUnDWDg1BSvBhFrPq93YsA0bYQ3pF4kE7N3nTcYigg== X-Received: by 2002:a7b:cd91:: with SMTP id y17mr15169430wmj.171.1607298007613; Sun, 06 Dec 2020 15:40:07 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id 64sm11892213wmd.12.2020.12.06.15.40.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:07 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 03/19] target/mips: Remove unused headers from fpu_helper.c Date: Mon, 7 Dec 2020 00:39:33 +0100 Message-Id: <20201206233949.3783184-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/fpu_helper.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 020b768e87b..956e3417d0f 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -21,15 +21,11 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "internal.h" -#include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -#include "exec/memop.h" -#include "sysemu/kvm.h" #include "fpu/softfloat.h" From patchwork Sun Dec 6 23:39:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2E6BC19425 for ; Sun, 6 Dec 2020 23:41:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C44CC2333E for ; Sun, 6 Dec 2020 23:41:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728473AbgLFXlA (ORCPT ); Sun, 6 Dec 2020 18:41:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728343AbgLFXlA (ORCPT ); Sun, 6 Dec 2020 18:41:00 -0500 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D07F1C0613D4 for ; Sun, 6 Dec 2020 15:40:13 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id l9so1888330wrt.13 for ; Sun, 06 Dec 2020 15:40:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Huxnn0HKIdijL4gbDxvVYsr519/EqwJmDm79CM0bGZ0=; b=uVdfWSV6oUgZ0RiBN0VekDdzex+vaiVx3ppBSPyv8R4HRoXN21n157Z2WSmR4CJMKk fUz87yDqjpCG/qH9w8yUaCetBRGhe0xzl3F5Xd3pklPupaMHTSm6M7ET/yssBcOYdpGN 2uRgK1t4dwtBQjw6zdunVOzomlQ2YacmUjTzTvri/2781e2tucLYNBD/gPWtB2TkdXs6 CTaUmyNyHwzcHhAlEWPmkytqph/KxajjPNDXWXDaHM3+u8n4Q08nnih5MyRcn15evzpj 26EfgVj1L6Z/9WkC72aFaU2xjXyPITodgdhCAKDZvllotVcqaV82URkQnStqKtZ/f+gH mT6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Huxnn0HKIdijL4gbDxvVYsr519/EqwJmDm79CM0bGZ0=; b=O+u3MQPmtuwINm5ZM37fX6RGc8bCkqQcbIJ5AL8E7JFyeASsAtcJjDFXmw1v1Yik3F +N9Le7aFZ5NhdihTXiyRCfiNjT5IWojiEpJ3NHMKssGp8og6uNjofJdJj5dC835YUJcy OTW4dLQQ9jPZkwo2ikt+FeaqmBzlr9l63NSxmLbaPQdebitRtFNlNTjv2eh5Q1Q4hqPj VPzZ2sylEuQS5mEYXvzgl2SH7IYnElPG2DqsiLzJp4mGk2gTBYHCjbUD5nI0L6qjKvgs e0lYAeW1p90jfksquAGwATGDjqMsClbkJf4l1P8/nEDCZB6+5leE9ncAT1nTHC4VjoSd oE0w== X-Gm-Message-State: AOAM5339kCIsw7Hboldl9pef0GIbWIHpLgkfxtbcvU2gfSs6oQnjM1l8 +iY30PTmzJeO8yeqIs4VzgA= X-Google-Smtp-Source: ABdhPJzYcEqcflYGeZNH2yRDKKaaaIcgG6lb7OML9NbCgUdNxk0iaBY70qO18HQkTUwOQy8wR+faaQ== X-Received: by 2002:adf:db45:: with SMTP id f5mr7587571wrj.153.1607298012630; Sun, 06 Dec 2020 15:40:12 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id y130sm12336620wmc.22.2020.12.06.15.40.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:12 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 04/19] target/mips: Remove unused headers from cp0_helper.c Date: Mon, 7 Dec 2020 00:39:34 +0100 Message-Id: <20201206233949.3783184-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Remove unused headers and add missing "qemu/log.h" since qemu_log() is called. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cp0_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index a1b5140ccaf..d8749658945 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -21,15 +21,13 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" #include "internal.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" -#include "exec/memop.h" -#include "sysemu/kvm.h" #ifndef CONFIG_USER_ONLY From patchwork Sun Dec 6 23:39:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56B04C4361B for ; Sun, 6 Dec 2020 23:41:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 29920229C7 for ; Sun, 6 Dec 2020 23:41:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728491AbgLFXlQ (ORCPT ); Sun, 6 Dec 2020 18:41:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726046AbgLFXlP (ORCPT ); Sun, 6 Dec 2020 18:41:15 -0500 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D981AC061A4F for ; Sun, 6 Dec 2020 15:40:18 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id a3so12052927wmb.5 for ; Sun, 06 Dec 2020 15:40:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wgUivnHTiFsBsZUJynu5sdeZ+qIl0Vpz/g/o+OzVfXc=; b=E/w6I/YA1QBm/TJRhjJKH6UCcB0vEAmhPTcnvK9MTghg2gfjSoujrDqduMv9seuqeQ vwzngALnI38rHHDk/z6aPvSXmgAIICymbKJoWZ4aaTDbSICad7V+kstgPc8wIs8BZH8M evZ6S0kfYSiEMF1QCXoRCBZNScSp2fkR4k3GEBL1vJjmMuZ6JSZQKl0RT5Ztm2yM73fv VcoczWisynMrLtCBosob12MrLxCZwNz35lJU1p91FHy0ePl8G68zg9Pce1+qt15sH+tF UHK7tDRu+L6oCSIRI0kI6hy5jyg0Ux5mG5dJMTBGwDn9k6BqNACTUgdCwCxY6ViIhoeK zjAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=wgUivnHTiFsBsZUJynu5sdeZ+qIl0Vpz/g/o+OzVfXc=; b=Gh79VIu8vslOfYmSz65M/+Y11pQoXyNH2jdRk4lP4mfX40gylp597KkKypH1kEYGre plabYNcZD7LLtxTCrz4TMNg40glW+10/kPUak+JMZZNvnLxtD1r8db1mOLEw9iYVEhTR USICpPzQt3c+jlFiPgfYWRKwfK7fB4LU/IbhbfBNR1vuF1Eq0LceZorfF01iEyqkzGGL 7YiHyriBiBKn5AdD51O27U0+/A2pYW0vo/UOS02klmemo1MYPXXgz3PNehpoUCysDGXC 2rBfYJoZ1zGA27A1OmRXKYS5eB0+GqKqDYFvdQaLX7t2WQhfJpUTjji4ocLtfAHTTugf XNkw== X-Gm-Message-State: AOAM5323nDhjvtn4a8dq2c6vzcjwwl6eXmuDU69rvRahj3Rux9PZ4v+a VlYgcb5z/4K9kBtbBcVMzRU= X-Google-Smtp-Source: ABdhPJyn3aNUhSifbgw9ga7ggzYpifzBJNJITGXqPHS89nq/anekJvKjvBXt16wY19n9bHCAzW5XYQ== X-Received: by 2002:a1c:e309:: with SMTP id a9mr15672224wmh.172.1607298017714; Sun, 06 Dec 2020 15:40:17 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id o203sm12394160wmb.0.2020.12.06.15.40.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:17 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 05/19] target/mips: Remove unused headers from op_helper.c Date: Mon, 7 Dec 2020 00:39:35 +0100 Message-Id: <20201206233949.3783184-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/op_helper.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 5184a1838be..5aa97902e98 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -19,15 +19,11 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "internal.h" -#include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "exec/memop.h" -#include "sysemu/kvm.h" /*****************************************************************************/ From patchwork Sun Dec 6 23:39:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42AF8C433FE for ; Sun, 6 Dec 2020 23:41:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 11FD1208DB for ; Sun, 6 Dec 2020 23:41:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728503AbgLFXlQ (ORCPT ); Sun, 6 Dec 2020 18:41:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727468AbgLFXlP (ORCPT ); Sun, 6 Dec 2020 18:41:15 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26BFEC061A51 for ; Sun, 6 Dec 2020 15:40:24 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id r3so11037968wrt.2 for ; Sun, 06 Dec 2020 15:40:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LGB1WfqGgk+E2BwfN1znIYNM8Z3EDS1Ck0ntTTU7ae8=; b=BjYNpSuhMXRN3yzz7v8F0ddsWC0Dvd7e9EXTpN8f3LCl6fgx4hk8n+tmByOePqfT6S XfaNjCg5xXOg8+uwLVvYX+zXVIX/t2N0WAXA8sP1Jbc8xhghOg7Vm0mGuK93ye8H/hkC b+u3WSZBJZcjSc9M01II3aRCYoJSnNHw7s+2vUdsr+rTiy/LGwy7YujgIws3OhDDRweH HOh9PKLKPbtO4TVkaL8vOxQPgPygx0uhcpkLLJOFU5tD8vtHJpQk9jN1wFX2Fhgg1hYV WRm2JD7yO+uNSaaxeQhf+L/EqUlVwVaos4WJAC1uUydp9X6iP+m0P0BPosgXhb5mAcI+ WJFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=LGB1WfqGgk+E2BwfN1znIYNM8Z3EDS1Ck0ntTTU7ae8=; b=gt8cI/p53dJsOkJtYWxoEbkXV10H4QsSEETK3iMB359dYlHHY07OOhVQ9wBw5S8vtu 3wEQrUPXOkYV/rZR/7i5YPBBjApCztiZLl4sNCMCWJHCOWUlfjqDIKrVBHNKrkULZEGO OS8FoLdVn6ZnRgYvD6k4rfTdV6UhdsZeFqotAsqnDo08JEiT6jjD2K4IVUSc5i+y9o24 iDEysIZ3pD3OToy+pKyP5mwejDebJg/X3TVvCsaqCHj7eP1f1jDcFxjAbXw0r8Lar9d3 PAfIo4asn6PJB8yputtnI/g9gGp1+FwnhtXs301/j4LeaMQ3MDYN53p5HVNpyvHV1BVX 8UVA== X-Gm-Message-State: AOAM531rjjrJF6VDSxaGJ4hBIednJs+3PWZOOyg9OkWjh46UttQEJYOt t5B+8uoZ/SZepkCd96ohQd4= X-Google-Smtp-Source: ABdhPJysqiCEfdLErNwAUUYoVp5/a3euOcrunaaXOC5+fFMPXtLaIPATX703omSt4u8PEH29fpe5vQ== X-Received: by 2002:a5d:6191:: with SMTP id j17mr16516791wru.299.1607298022902; Sun, 06 Dec 2020 15:40:22 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id 125sm12128389wmc.27.2020.12.06.15.40.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:22 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 06/19] target/mips: Remove unused headers from kvm.c Date: Mon, 7 Dec 2020 00:39:36 +0100 Message-Id: <20201206233949.3783184-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/kvm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 72637a1e021..b3f193f7764 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -19,11 +19,9 @@ #include "internal.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" -#include "qemu/timer.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "sysemu/runstate.h" -#include "sysemu/cpus.h" #include "kvm_mips.h" #include "exec/memattrs.h" #include "hw/boards.h" From patchwork Sun Dec 6 23:39:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 667C7C4167B for ; Sun, 6 Dec 2020 23:41:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3EB3E22C9F for ; Sun, 6 Dec 2020 23:41:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728522AbgLFXlT (ORCPT ); Sun, 6 Dec 2020 18:41:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727468AbgLFXlT (ORCPT ); Sun, 6 Dec 2020 18:41:19 -0500 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A3CCC061A52 for ; Sun, 6 Dec 2020 15:40:29 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id 3so12019844wmg.4 for ; Sun, 06 Dec 2020 15:40:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nvvnuVAXyMXpDzWyrVINIXmEpj3Xa1vtGYGPNmttFgg=; b=n88N84E/kJAVo0Mxv3CD6rucxKCZvjzDLCaLmUaDQq7FtRotXM5HNe+7mTUSvR0xw2 e+nh5+7e7RxkOcIpAN2a2l2lagy9R6AgbXqmKb3gjMtVS1rHZ24aRbBB8lKg3Dfwhrdt m/uqQbHQE3GChYP9x8yxehO52L680Z91+AKqEpWZungeZHoMVteAU9JqSw2NQ3oGmo4Z yamgUSSLJVXaHyJxIoLCczu+vMChZUaLx/8CqTsxii9Oql71csY140FfWl1VDk1vysui PgDlYmZUw/2UQRF8XdM7RZsCY9HV3vf9kq8vGtuHY8TV0g2w3o7Yh33h2p0uYQN7chvi cmpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nvvnuVAXyMXpDzWyrVINIXmEpj3Xa1vtGYGPNmttFgg=; b=DqjkuTiTOllMmUZ3rh1/1DKQSE05knxa7JQgNCurA+A+LPNdSo8SXnN2PMh/A7luHx tMQNh/JXHCALoao44lAZ4UZLo7xQn3HPTDdph+kROhhPyI7upbF/45JC+m1XMkaQYHFO v5LuAqXOSZzHm1nEyCjXYHkzKPUX4aIPQTWNgLWo/LiDBv0NqFVDQHLMwZYLa70wTYfN dPTcxwz59qUyw0fQSMpHJUd3bnmxCPv3sNmq115w9/YVHlHVnh8O3D9cx7D5OXOjmKtm 4Oq1q/NNCMrq1J0LmgkSNDYMF3Y7472H/GvwTc9rQivDA8aBfmDxQbIwSivHslJYs6Wr FyVA== X-Gm-Message-State: AOAM531hRAJ1jVM9EhQzlm8BhFQawtCE1BIn60n4z3m+7R76R83MoDdY WtvU5HOAkxx84ZSy2EBMlNU= X-Google-Smtp-Source: ABdhPJw3Z/Cg8aKrlfWwSiz6cd42kt3hOEz7TpaPUsuc69JEMA3JkZ1sJCT+n/WH6cgUMPmM3FmWTw== X-Received: by 2002:a1c:5f54:: with SMTP id t81mr15343246wmb.77.1607298027981; Sun, 06 Dec 2020 15:40:27 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id c4sm13758103wrw.72.2020.12.06.15.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:27 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 07/19] target/mips: Include "exec/memattrs.h" in 'internal.h' Date: Mon, 7 Dec 2020 00:39:37 +0100 Message-Id: <20201206233949.3783184-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org mips_cpu_do_transaction_failed() requires MemTxAttrs and MemTxResult declarations. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 1 + target/mips/kvm.c | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index dd8a7809b64..76b7a85cbb3 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -8,6 +8,7 @@ #ifndef MIPS_INTERNAL_H #define MIPS_INTERNAL_H +#include "exec/memattrs.h" #include "fpu/softfloat-helpers.h" /* diff --git a/target/mips/kvm.c b/target/mips/kvm.c index b3f193f7764..7a6ea5299fb 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -23,7 +23,6 @@ #include "sysemu/kvm_int.h" #include "sysemu/runstate.h" #include "kvm_mips.h" -#include "exec/memattrs.h" #include "hw/boards.h" #define DEBUG_KVM 0 From patchwork Sun Dec 6 23:39:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 904E6C19425 for ; Sun, 6 Dec 2020 23:41:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 56E4C208DB for ; Sun, 6 Dec 2020 23:41:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728533AbgLFXlU (ORCPT ); Sun, 6 Dec 2020 18:41:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728505AbgLFXlT (ORCPT ); Sun, 6 Dec 2020 18:41:19 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48C21C061A53 for ; Sun, 6 Dec 2020 15:40:34 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id a12so4230892wrv.8 for ; Sun, 06 Dec 2020 15:40:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Aknicxq69ir15ZLnRnKAAOwqB9N6TW01pMwQWojqcCI=; b=SMcwF9Y38HdM3cHw+XUBTdWjcIxdXMevhr+d3RMSQzJm7SV4btb/jzsKL6dyAT8J4N RF/q0qOF69NuRBYtyjFNGzlvDciWaIjIoQVXTlKFg3tNb+UMTvzOHNi8cTjrAvr38IOB 7gxFGtyOi+UX+l/vxT+ZZYH98m14+QNyVTZyi5LpzA4E9c7w2hx1RKB5VHo0meETNuh6 5BvCm5p+lwkR3annd+3tgsEfLQdKYojvFNrou4sqlExf9n+yKPonUV1PUUHYd51z2D8V fre8cnC9LZsoexMnX6V4/ERaQtZ9XG4ZVXhtBJRs6VxhywP0thKFBNq8kwz6b45vW5Qn b69g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Aknicxq69ir15ZLnRnKAAOwqB9N6TW01pMwQWojqcCI=; b=Oz+KkGeeEy5OLjZueaiw1pfRsDCKfaJ/X/o0p7R/AKWNhm6dvhe4oErva7wscPbcxr pP+DLGE8AC/y3RMdZDa0UOpYrQFiCEvd9sONhHaH2dcWmaIeQyY3f185uODio7ytNgys vQAusB+ozRBbhUlRNKS/ShpVuoFm+vPAED1KHisUDdS4SX5JLhGZHL7a4VIpRo9tg2oF vQaNiRtfPcqt/Tt/4Goh6D+UeOhhGePtLvRVWUZPQ6FeCKJ4uKSzAJ79T/z/da5hMnU8 gOnjMzOXMDeJOF37dj5cKNymbtlxF34waU0PySEY73U1TB4iJ9gwmuDrgXt3RtmmbMey aYww== X-Gm-Message-State: AOAM533vJ/IN2IANEuHy3ptx/cmEKID7wAYNhoG/3OU8G0cL2zkq8s4T xpYAwd6k2oJBeqrOqRD64H8= X-Google-Smtp-Source: ABdhPJxxew9ajV5OxcxEX4k8jrJziKOpQJ8c03uGsdsLbbr/Q/8/WsepohI0sQWMGW6MqgyNb1BSYA== X-Received: by 2002:adf:f48c:: with SMTP id l12mr16503466wro.280.1607298032990; Sun, 06 Dec 2020 15:40:32 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id a12sm12721260wrq.58.2020.12.06.15.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:32 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 08/19] target/mips: Extract cpu_supports*/cpu_set* translate.c Date: Mon, 7 Dec 2020 00:39:38 +0100 Message-Id: <20201206233949.3783184-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Move cpu_supports*() and cpu_set_exception_base() from translate.c to cpu.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu.c | 18 ++++++++++++++++++ target/mips/translate.c | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 76d50b00b42..8d9ef139f07 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -310,3 +310,21 @@ MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) return MIPS_CPU(cpu); } + +bool cpu_supports_cps_smp(const char *cpu_type) +{ + const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); + return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; +} + +bool cpu_supports_isa(const char *cpu_type, uint64_t isa) +{ + const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); + return (mcc->cpu_def->insn_flags & isa) != 0; +} + +void cpu_set_exception_base(int vp_index, target_ulong address) +{ + MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); + vp->env.exception_base = address; +} diff --git a/target/mips/translate.c b/target/mips/translate.c index 346635370c4..dbb71fdaa5d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31766,24 +31766,6 @@ void cpu_mips_realize_env(CPUMIPSState *env) mvp_init(env, env->cpu_model); } -bool cpu_supports_cps_smp(const char *cpu_type) -{ - const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); - return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; -} - -bool cpu_supports_isa(const char *cpu_type, uint64_t isa) -{ - const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); - return (mcc->cpu_def->insn_flags & isa) != 0; -} - -void cpu_set_exception_base(int vp_index, target_ulong address) -{ - MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); - vp->env.exception_base = address; -} - void cpu_state_reset(CPUMIPSState *env) { CPUState *cs = env_cpu(env); From patchwork Sun Dec 6 23:39:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDD8EC19437 for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id 94sm3638043wrq.22.2020.12.06.15.40.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:37 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 09/19] target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c Date: Mon, 7 Dec 2020 00:39:39 +0100 Message-Id: <20201206233949.3783184-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu.c | 33 +++++++++++++++++++++++++++++++++ target/mips/helper.c | 33 --------------------------------- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 8d9ef139f07..e612a7ac41a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -30,6 +30,7 @@ #include "exec/exec-all.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" +#include "qapi/qapi-commands-machine-target.h" static void mips_cpu_set_pc(CPUState *cs, vaddr value) { @@ -299,6 +300,38 @@ static void mips_cpu_register_types(void) type_init(mips_cpu_register_types) +static void mips_cpu_add_definition(gpointer data, gpointer user_data) +{ + ObjectClass *oc = data; + CpuDefinitionInfoList **cpu_list = user_data; + CpuDefinitionInfoList *entry; + CpuDefinitionInfo *info; + const char *typename; + + typename = object_class_get_name(oc); + info = g_malloc0(sizeof(*info)); + info->name = g_strndup(typename, + strlen(typename) - strlen("-" TYPE_MIPS_CPU)); + info->q_typename = g_strdup(typename); + + entry = g_malloc0(sizeof(*entry)); + entry->value = info; + entry->next = *cpu_list; + *cpu_list = entry; +} + +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +{ + CpuDefinitionInfoList *cpu_list = NULL; + GSList *list; + + list = object_class_get_list(TYPE_MIPS_CPU, false); + g_slist_foreach(list, mips_cpu_add_definition, &cpu_list); + g_slist_free(list); + + return cpu_list; +} + /* Could be used by generic CPU object */ MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) { diff --git a/target/mips/helper.c b/target/mips/helper.c index 063b65c0528..bb962a3e8cc 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -24,7 +24,6 @@ #include "exec/cpu_ldst.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" -#include "qapi/qapi-commands-machine-target.h" enum { TLBRET_XI = -6, @@ -1497,35 +1496,3 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, cpu_loop_exit_restore(cs, pc); } - -static void mips_cpu_add_definition(gpointer data, gpointer user_data) -{ - ObjectClass *oc = data; - CpuDefinitionInfoList **cpu_list = user_data; - CpuDefinitionInfoList *entry; - CpuDefinitionInfo *info; - const char *typename; - - typename = object_class_get_name(oc); - info = g_malloc0(sizeof(*info)); - info->name = g_strndup(typename, - strlen(typename) - strlen("-" TYPE_MIPS_CPU)); - info->q_typename = g_strdup(typename); - - entry = g_malloc0(sizeof(*entry)); - entry->value = info; - entry->next = *cpu_list; - *cpu_list = entry; -} - -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) -{ - CpuDefinitionInfoList *cpu_list = NULL; - GSList *list; - - list = object_class_get_list(TYPE_MIPS_CPU, false); - g_slist_foreach(list, mips_cpu_add_definition, &cpu_list); - g_slist_free(list); - - return cpu_list; -} From patchwork Sun Dec 6 23:39:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B52BAC1B0D8 for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id n10sm12603481wrv.77.2020.12.06.15.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:42 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 10/19] target/mips: Add !CONFIG_USER_ONLY comment after #endif Date: Mon, 7 Dec 2020 00:39:40 +0100 Message-Id: <20201206233949.3783184-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org To help understand ifdef'ry, add comment after #endif. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/helper.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index bb962a3e8cc..6d33809fb8b 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -455,7 +455,8 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) } } } -#endif + +#endif /* !CONFIG_USER_ONLY */ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) @@ -537,6 +538,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, } #if !defined(CONFIG_USER_ONLY) + hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { MIPSCPU *cpu = MIPS_CPU(cs); @@ -550,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } -#endif -#if !defined(CONFIG_USER_ONLY) #if !defined(TARGET_MIPS64) /* @@ -886,7 +886,7 @@ refill: return true; } #endif -#endif +#endif /* !CONFIG_USER_ONLY */ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -1017,7 +1017,7 @@ static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_MSADIS] = "MSA disabled", [EXCP_MSAFPE] = "MSA floating point", }; -#endif +#endif /* !CONFIG_USER_ONLY */ target_ulong exception_resume_pc(CPUMIPSState *env) { @@ -1080,7 +1080,8 @@ static inline void set_badinstr_registers(CPUMIPSState *env) env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4); } } -#endif + +#endif /* !CONFIG_USER_ONLY */ void mips_cpu_do_interrupt(CPUState *cs) { @@ -1480,7 +1481,7 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) } } } -#endif +#endif /* !CONFIG_USER_ONLY */ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, From patchwork Sun Dec 6 23:39:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4630AC2BB40 for ; Sun, 6 Dec 2020 23:41:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 28C24208DB for ; Sun, 6 Dec 2020 23:41:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728590AbgLFXlf (ORCPT ); Sun, 6 Dec 2020 18:41:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728559AbgLFXlf (ORCPT ); Sun, 6 Dec 2020 18:41:35 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50802C0613D2 for ; Sun, 6 Dec 2020 15:40:49 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id g25so8475903wmh.1 for ; Sun, 06 Dec 2020 15:40:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ln1ozzZklmmKqm+Rb52d2EFhNZPiZM6Mxpme95/5JJU=; b=jQk92dIVwrdkVPtmX1jJV1rSEKaDAqDXYlCaqujyjc2bEr3l4vFm5AMH5/P7rp1nJ3 8ZPwZCiovi85lM4lJCqIZoKGzh/uFSOAyFMZ0v1lqw9ceWjKRSJJx/MLuPklrcXaVoe9 zs4HMyMBdlQnLCvQg8luWTcyLkkVQtePXq32efmFuF2LYf4RO9MMoJakwHP3u/hzAzZ6 4epyymBDU59e0AD8ZAI56Ilex/yh3WfIS/poeFpjJ9SdbCsyLBi0R1jSTd9vV8s5kZ55 F2idkqYOzfWmL/BJJ88CSc4DjWSESNPjgQaTPtYWaDavZ/nIhyouy02wpAzHdj5MOgzJ 6oOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ln1ozzZklmmKqm+Rb52d2EFhNZPiZM6Mxpme95/5JJU=; b=Je5pGFxO7WkzF884UfgsJJLN56AJ//M3K9DAdpjAhXMH0Uvda0qDyCFG8YXJUV2hPb 96/gBIcF5WwkplDg30U40hoXJtH9O+8vQW5bZTHvuqHYhksFfhEGzYXGnwaXxLGJG9TF qabSS/50aSbz8U5MSmdbquxX6amTu3hHd7udwJtL/xtPNT3cgKuBlYffPRXf4hAxI1hn LIRGejt6WcY1TX+6+EtGnaWgRkI0d+bcIyVniOdczoY8YDX8VlJXCecfX6ViAReeC8nO hT4YZgiWwzDR9HRab9wZ2pE8DTgl3oqJAKP2ThSaOwBfCr+1TH87I8W9KFlFdyXL8Ggj svIg== X-Gm-Message-State: AOAM53275JX3yigPWC+i4W8WmDGkzzmfMXAmgiBqjGWQB6uW2sQ2o4hR pWg/TChrV+8j/E82m56WIME= X-Google-Smtp-Source: ABdhPJyLat0nr9LEAy8mnYK9IXYkcFeq8U2izbHXCuIH5Za9odYVdvWamOlM+ykRnsHXCvQZjFx/kg== X-Received: by 2002:a1c:35c2:: with SMTP id c185mr15673774wma.74.1607298047959; Sun, 06 Dec 2020 15:40:47 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id c1sm11434357wml.8.2020.12.06.15.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:47 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 11/19] target/mips: Extract common helpers from helper.c to common_helper.c Date: Mon, 7 Dec 2020 00:39:41 +0100 Message-Id: <20201206233949.3783184-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The rest of helper.c is TLB related. Extract the non TLB specific functions to a new file, so we can rename helper.c as tlb_helper.c in the next commit. Signed-off-by: Philippe Mathieu-Daudé --- Any better name? xxx_helper.c are usually TCG helpers. --- target/mips/common_helper.c | 178 ++++++++++++++++++++++++++++++++++++ target/mips/helper.c | 152 ------------------------------ target/mips/meson.build | 1 + 3 files changed, 179 insertions(+), 152 deletions(-) create mode 100644 target/mips/common_helper.c diff --git a/target/mips/common_helper.c b/target/mips/common_helper.c new file mode 100644 index 00000000000..07c947ecc55 --- /dev/null +++ b/target/mips/common_helper.c @@ -0,0 +1,178 @@ +/* + * MIPS emulation helpers for qemu. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "qemu/osdep.h" + +#include "cpu.h" +#include "internal.h" +#include "exec/exec-all.h" +#include "exec/log.h" + +#if !defined(CONFIG_USER_ONLY) + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v = cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask = ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu = (v >> CP0St_CU0) & 0xf; + mx = (v >> CP0St_MX) & 0x1; + ksu = (v >> CP0St_KSU) & 0x3; + asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + + tcstatus = cu << CP0TCSt_TCU0; + tcstatus |= mx << CP0TCSt_TMX; + tcstatus |= ksu << CP0TCSt_TKSU; + tcstatus |= asid; + + if (tc == cpu->current_tc) { + tcst = &cpu->active_tc.CP0_TCStatus; + } else { + tcst = &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &= ~mask; + *tcst |= tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask = env->CP0_Status_rw_bitmask; + target_ulong old = env->CP0_Status; + + if (env->insn_flags & ISA_MIPS32R6) { + bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux = (1 << CP0St_KX) & val; + ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ + ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ + val = (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { + mask &= ~(3 << CP0St_KSU); + } + mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status = (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled */ + tlb_flush(env_cpu(env)); + } +#endif + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask = 0x00C00300; + uint32_t old = env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS32R2) { + mask |= 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS32R6) { + mask &= ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i = 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); + } + } +} + +#endif /* !CONFIG_USER_ONLY */ + +target_ulong exception_resume_pc(CPUMIPSState *env) +{ + target_ulong bad_pc; + target_ulong isa_mode; + + isa_mode = !!(env->hflags & MIPS_HFLAG_M16); + bad_pc = env->active_tc.PC | isa_mode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ + bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + } + + return bad_pc; +} + +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index = EXCP_EXT_INTERRUPT; + env->error_code = 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, + uint32_t exception, + int error_code, + uintptr_t pc) +{ + CPUState *cs = env_cpu(env); + + qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", + __func__, exception, error_code); + cs->exception_index = exception; + env->error_code = error_code; + + cpu_loop_exit_restore(cs, pc); +} diff --git a/target/mips/helper.c b/target/mips/helper.c index 6d33809fb8b..5db7e80e22b 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -357,105 +357,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use = env->tlb->nb_tlb; } -/* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ - int32_t tcstatus, *tcst; - uint32_t v = cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask = ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu = (v >> CP0St_CU0) & 0xf; - mx = (v >> CP0St_MX) & 0x1; - ksu = (v >> CP0St_KSU) & 0x3; - asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - - tcstatus = cu << CP0TCSt_TCU0; - tcstatus |= mx << CP0TCSt_TMX; - tcstatus |= ksu << CP0TCSt_TKSU; - tcstatus |= asid; - - if (tc == cpu->current_tc) { - tcst = &cpu->active_tc.CP0_TCStatus; - } else { - tcst = &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &= ~mask; - *tcst |= tcstatus; - compute_hflags(cpu); -} - -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask = env->CP0_Status_rw_bitmask; - target_ulong old = env->CP0_Status; - - if (env->insn_flags & ISA_MIPS32R6) { - bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux = (1 << CP0St_KX) & val; - ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ - ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ - val = (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { - mask &= ~(3 << CP0St_KSU); - } - mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } - - env->CP0_Status = (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled */ - tlb_flush(env_cpu(env)); - } -#endif - if (env->CP0_Config3 & (1 << CP0C3_MT)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); - } -} - -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask = 0x00C00300; - uint32_t old = env->CP0_Cause; - int i; - - if (env->insn_flags & ISA_MIPS32R2) { - mask |= 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS32R6) { - mask &= ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); - } - } - - /* Set/reset software interrupts */ - for (i = 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); - } - } -} - #endif /* !CONFIG_USER_ONLY */ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, @@ -1017,27 +918,7 @@ static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_MSADIS] = "MSA disabled", [EXCP_MSAFPE] = "MSA floating point", }; -#endif /* !CONFIG_USER_ONLY */ -target_ulong exception_resume_pc(CPUMIPSState *env) -{ - target_ulong bad_pc; - target_ulong isa_mode; - - isa_mode = !!(env->hflags & MIPS_HFLAG_M16); - bad_pc = env->active_tc.PC | isa_mode; - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, come back to - * the jump. - */ - bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - } - - return bad_pc; -} - -#if !defined(CONFIG_USER_ONLY) static void set_hflags_for_handler(CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ @@ -1398,24 +1279,6 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index = EXCP_NONE; } -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index = EXCP_EXT_INTERRUPT; - env->error_code = 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { @@ -1482,18 +1345,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) } } #endif /* !CONFIG_USER_ONLY */ - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs = env_cpu(env); - - qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", - __func__, exception, error_code); - cs->exception_index = exception; - env->error_code = error_code; - - cpu_loop_exit_restore(cs, pc); -} diff --git a/target/mips/meson.build b/target/mips/meson.build index d980240f9e3..4858bf86ad6 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,5 +1,6 @@ mips_ss = ss.source_set() mips_ss.add(files( + 'common_helper.c', 'cp0_helper.c', 'cpu.c', 'dsp_helper.c', From patchwork Sun Dec 6 23:39:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D11EC2BB48 for ; Sun, 6 Dec 2020 23:41:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 094C322C9F for ; Sun, 6 Dec 2020 23:41:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728597AbgLFXlg (ORCPT ); Sun, 6 Dec 2020 18:41:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728582AbgLFXlf (ORCPT ); Sun, 6 Dec 2020 18:41:35 -0500 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EC71C061A54 for ; Sun, 6 Dec 2020 15:40:54 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id e25so12106513wme.0 for ; Sun, 06 Dec 2020 15:40:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dkeHRiNqYRfILITll5iC1CRHmgrIelrL5ahd1h8p/CA=; b=AJCAf6tBfcDaLHenkAJcWO8awSPcD6OV0VbmqjcQG8YLcoPHOBX9/zrsfUtNVfpmcP nIiZKqXotBUNxCRuPgt5jlY9J+OmF0W/JRNLxzmga4dPH9o6OjFFAvwGFFet9aapdvQj 4OhagE7WsNKL70LrawKpoX3U5So49v1TraNAHhsokMcGAZgM1ZCnqC4yyvRqs39x/TbY N5UMqqtUfCM3amuvAeTqwaJ44Yc09OO6rP8Wd5M1gDiZNFIutZ8C6OLPOykS5/ywo3T2 xNxVSkbiwCbPmm1cwlK6ZEIrga3rfqeagoYvTmpGjkqsuoRdZxKM29h+CQlW5mkWJQ4y EGww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dkeHRiNqYRfILITll5iC1CRHmgrIelrL5ahd1h8p/CA=; b=DFyMOdOKOsTMj5p98P4ARj+BQBK5rijck4aYJH/Md/DtgIS3P8y8wX7QsBI5xmvnGK MgJiXP93qWb28RKlwFDdprgLjY/COvMSqLsJVJWDBB68VQjsuiuQuZt5DcQZVZ9iSpwu 38iumXKfAMVvc3pM9TelykswSjSD4ilx2jwCXFStOIoHVBFmXGblIywsgsYbGc30Q/fX d29onjfadijNMA84vNcSYTFxuB12w45KGyeChPdHU1qmEyepaliaD29Hizlz7glZC/3J mxhIif0KDfYFknLd4Jp/bNfnnVYm/u2xPPVlZ+Kq7b7H10PCPWXsuCImRxUc8zTjszGY wDoQ== X-Gm-Message-State: AOAM533pJTqWPbkgyEqzhWhr1POzCBaHYh+rZhg7jMlf9SPK8ZbP+RcP g7xtiStFKXJ6CiiFUJdg+UTEYU30C6Y= X-Google-Smtp-Source: ABdhPJz3cUW+H59OJ3Lwu1sxBPsBIrKMW2o+PML6fhNgBmnIF9weKVx8bfaabn+wJQrAekiecwHQeg== X-Received: by 2002:a05:600c:208:: with SMTP id 8mr15652630wmi.146.1607298052994; Sun, 06 Dec 2020 15:40:52 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id a9sm12901278wrp.21.2020.12.06.15.40.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:52 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 12/19] target/mips: Rename helper.c as tlb_helper.c Date: Mon, 7 Dec 2020 00:39:42 +0100 Message-Id: <20201206233949.3783184-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This file contains functions related to TLB management, rename it as 'tlb_helper.c'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- Maybe I missed some functions not TLB specific... --- target/mips/{helper.c => tlb_helper.c} | 2 +- target/mips/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename target/mips/{helper.c => tlb_helper.c} (99%) diff --git a/target/mips/helper.c b/target/mips/tlb_helper.c similarity index 99% rename from target/mips/helper.c rename to target/mips/tlb_helper.c index 5db7e80e22b..7022be13ae4 100644 --- a/target/mips/helper.c +++ b/target/mips/tlb_helper.c @@ -1,5 +1,5 @@ /* - * MIPS emulation helpers for qemu. + * MIPS TLB (Translation lookaside buffer) helpers. * * Copyright (c) 2004-2005 Jocelyn Mayer * diff --git a/target/mips/meson.build b/target/mips/meson.build index 4858bf86ad6..c685f03fb28 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -6,10 +6,10 @@ 'dsp_helper.c', 'fpu_helper.c', 'gdbstub.c', - 'helper.c', 'lmmi_helper.c', 'msa_helper.c', 'op_helper.c', + 'tlb_helper.c', 'translate.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) From patchwork Sun Dec 6 23:39:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1489C4361B for ; Sun, 6 Dec 2020 23:41:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AA47D208DB for ; Sun, 6 Dec 2020 23:41:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728615AbgLFXll (ORCPT ); Sun, 6 Dec 2020 18:41:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728583AbgLFXlk (ORCPT ); Sun, 6 Dec 2020 18:41:40 -0500 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1EF87C0613D3 for ; Sun, 6 Dec 2020 15:41:00 -0800 (PST) Received: by mail-wr1-x441.google.com with SMTP id i2so11043126wrs.4 for ; Sun, 06 Dec 2020 15:41:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T3FlFk78pLMkupK1YI/tjtH+Hq+IGEC+koiKdnLg6D4=; b=Nd40X/OAaFHU7qiOSgMuQvCbYgV4L46HRjBTenvdE6K7BjJktwpHXWNVaawkhTZbhQ f1XDpTbKYfXjgWpc7PVXdXJcmdYjn1hMiVuHUtsfsFC65VKnFs6+HEpRYrSn9o65epuS 5lgBLiZgQz8UrVk5IAkyx1imzjlUXcmBxmReRL8UIury8SpVuEoBWJF+SZTJmZ9U7HVI AlZq61DO68FzIZgkldq06THajtSF5NmsGFoDIjYw/0xsm87uVB5OezgFTXZrItwUvXYZ 2WshCAmKuvvR9dfxG092CZwgXaPEVskHC3S/ioc07+Hob0/TSzoAcpYt7ZLuiEX7P6F9 vFVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=T3FlFk78pLMkupK1YI/tjtH+Hq+IGEC+koiKdnLg6D4=; b=r/C0cDgUGiOWiGnhjdjjLG7U7QsHx443TonaSvuhu6zm9E9GQWIE/ypbTm8gItATsj BF1bQc6L0K4PBVXqWRdc8KqxIipVGSHk4uMw04Lai0aeuTP6kYgvx0KH/VHn5d7lVlWW Oc5mXTRqdyTtu2+yeP8lMMgT5D334uu99JmzXOBFzhou9OGv0Jr/Q8NANZHfaUmmRFZF Ytrky86fd+ZrMcSlqzDJJrlm3/93NqvKIla4eGKrJAmBsAdPsTQmz4mHmPC7GQH3QYe8 l3DfXB1QUjpSOLJpIfqv/w9PSEzMEDwhOT8PoSZZ2MdLR3clBU2Fwf1yytYdmiY95Nz8 7euQ== X-Gm-Message-State: AOAM531LseZffLEzG5rq+Wll5zGkHQ51VOd2u3vWYVJ9ZNYdGtoOxcPb 5X5BKaRRR0J7GGY64O85fGs= X-Google-Smtp-Source: ABdhPJw8IuYkegnv9iK+VaKUkUOm0Qb6xkjQ5rtQTFv+GuhbUTLtX2B/74LwkiAvEJAHYh99X9An8g== X-Received: by 2002:a05:6000:187:: with SMTP id p7mr16728218wrx.240.1607298058923; Sun, 06 Dec 2020 15:40:58 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id v64sm12121580wme.25.2020.12.06.15.40.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:40:58 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 13/19] target/mips: Fix code style for checkpatch.pl Date: Mon, 7 Dec 2020 00:39:43 +0100 Message-Id: <20201206233949.3783184-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate_init.c.inc | 36 ++++++++++++++++---------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index ea85d5c6a79..535b52b5444 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -932,19 +932,19 @@ void mips_cpu_list(void) } #ifndef CONFIG_USER_ONLY -static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb = 1; env->tlb->map_address = &no_mmu_map_address; } -static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb = 1; env->tlb->map_address = &fixed_mmu_map_address; } -static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); env->tlb->map_address = &r4k_map_address; @@ -956,25 +956,25 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; } -static void mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); switch (def->mmu_type) { - case MMU_TYPE_NONE: - no_mmu_init(env, def); - break; - case MMU_TYPE_R4000: - r4k_mmu_init(env, def); - break; - case MMU_TYPE_FMT: - fixed_mmu_init(env, def); - break; - case MMU_TYPE_R3000: - case MMU_TYPE_R6000: - case MMU_TYPE_R8000: - default: - cpu_abort(env_cpu(env), "MMU type not supported\n"); + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env_cpu(env), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ From patchwork Sun Dec 6 23:39:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 403EBC4167B for ; Sun, 6 Dec 2020 23:41:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 15171229C7 for ; Sun, 6 Dec 2020 23:41:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728628AbgLFXlq (ORCPT ); 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id z64sm8420316wme.10.2020.12.06.15.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:41:03 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 14/19] target/mips: Move mmu_init() functions to tlb_helper.c Date: Mon, 7 Dec 2020 00:39:44 +0100 Message-Id: <20201206233949.3783184-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 1 + target/mips/tlb_helper.c | 46 ++++++++++++++++++++++++++++++ target/mips/translate_init.c.inc | 48 -------------------------------- 3 files changed, 47 insertions(+), 48 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 76b7a85cbb3..142fa3e5007 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -218,6 +218,7 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); /* helper.c */ +void mmu_init(CPUMIPSState *env, const mips_def_t *def); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 7022be13ae4..366cc526a14 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -120,6 +120,52 @@ int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, return TLBRET_NOMATCH; } +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1; + env->tlb->map_address = &no_mmu_map_address; +} + +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1; + env->tlb->map_address = &fixed_mmu_map_address; +} + +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); + env->tlb->map_address = &r4k_map_address; + env->tlb->helper_tlbwi = r4k_helper_tlbwi; + env->tlb->helper_tlbwr = r4k_helper_tlbwr; + env->tlb->helper_tlbp = r4k_helper_tlbp; + env->tlb->helper_tlbr = r4k_helper_tlbr; + env->tlb->helper_tlbinv = r4k_helper_tlbinv; + env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; +} + +void mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); + + switch (def->mmu_type) { + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env_cpu(env), "MMU type not supported\n"); + } +} + static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) { /* diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index 535b52b5444..f3daf451a63 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -931,54 +931,6 @@ void mips_cpu_list(void) } } -#ifndef CONFIG_USER_ONLY -static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb = 1; - env->tlb->map_address = &no_mmu_map_address; -} - -static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb = 1; - env->tlb->map_address = &fixed_mmu_map_address; -} - -static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); - env->tlb->map_address = &r4k_map_address; - env->tlb->helper_tlbwi = r4k_helper_tlbwi; - env->tlb->helper_tlbwr = r4k_helper_tlbwr; - env->tlb->helper_tlbp = r4k_helper_tlbp; - env->tlb->helper_tlbr = r4k_helper_tlbr; - env->tlb->helper_tlbinv = r4k_helper_tlbinv; - env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; -} - -static void mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); - - switch (def->mmu_type) { - case MMU_TYPE_NONE: - no_mmu_init(env, def); - break; - case MMU_TYPE_R4000: - r4k_mmu_init(env, def); - break; - case MMU_TYPE_FMT: - fixed_mmu_init(env, def); - break; - case MMU_TYPE_R3000: - case MMU_TYPE_R6000: - case MMU_TYPE_R8000: - default: - cpu_abort(env_cpu(env), "MMU type not supported\n"); - } -} -#endif /* CONFIG_USER_ONLY */ - static void fpu_init (CPUMIPSState *env, const mips_def_t *def) { int i; From patchwork Sun Dec 6 23:39:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0424FC1B0D9 for ; Sun, 6 Dec 2020 23:41:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CB5D1208DB for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id w17sm11457014wmk.12.2020.12.06.15.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:41:08 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 15/19] target/mips: Move cpu definitions, reset() and realize() to cpu.c Date: Mon, 7 Dec 2020 00:39:45 +0100 Message-Id: <20201206233949.3783184-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Nothing TCG specific there, move to common cpu code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 4 - target/mips/cpu.c | 243 ++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 240 --------------------------------------- 3 files changed, 243 insertions(+), 244 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 142fa3e5007..fcd5e8335ec 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -206,10 +206,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) void mips_tcg_init(void); -/* TODO QOM'ify CPU reset and remove */ -void cpu_state_reset(CPUMIPSState *s); -void cpu_mips_realize_env(CPUMIPSState *env); - /* cp0_timer.c */ uint32_t cpu_mips_get_count(CPUMIPSState *env); void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e612a7ac41a..1073db7f257 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" +#include "qemu/qemu-print.h" #include "qapi/error.h" #include "cpu.h" #include "internal.h" @@ -30,6 +31,7 @@ #include "exec/exec-all.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" +#include "hw/semihosting/semihost.h" #include "qapi/qapi-commands-machine-target.h" static void mips_cpu_set_pc(CPUState *cs, vaddr value) @@ -100,6 +102,247 @@ static bool mips_cpu_has_work(CPUState *cs) return has_work; } +#include "translate_init.c.inc" + +static void cpu_mips_realize_env(CPUMIPSState *env) +{ + env->exception_base = (int32_t)0xBFC00000; + +#ifndef CONFIG_USER_ONLY + mmu_init(env, env->cpu_model); +#endif + fpu_init(env, env->cpu_model); + mvp_init(env, env->cpu_model); +} + +/* TODO QOM'ify CPU reset and remove */ +static void cpu_state_reset(CPUMIPSState *env) +{ + CPUState *cs = env_cpu(env); + + /* Reset registers to their default values */ + env->CP0_PRid = env->cpu_model->CP0_PRid; + env->CP0_Config0 = env->cpu_model->CP0_Config0; +#ifdef TARGET_WORDS_BIGENDIAN + env->CP0_Config0 |= (1 << CP0C0_BE); +#endif + env->CP0_Config1 = env->cpu_model->CP0_Config1; + env->CP0_Config2 = env->cpu_model->CP0_Config2; + env->CP0_Config3 = env->cpu_model->CP0_Config3; + env->CP0_Config4 = env->cpu_model->CP0_Config4; + env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; + env->CP0_Config5 = env->cpu_model->CP0_Config5; + env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; + env->CP0_Config6 = env->cpu_model->CP0_Config6; + env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; + env->CP0_Config7 = env->cpu_model->CP0_Config7; + env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; + env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask + << env->cpu_model->CP0_LLAddr_shift; + env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; + env->SYNCI_Step = env->cpu_model->SYNCI_Step; + env->CCRes = env->cpu_model->CCRes; + env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; + env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; + env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; + env->current_tc = 0; + env->SEGBITS = env->cpu_model->SEGBITS; + env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); +#if defined(TARGET_MIPS64) + if (env->cpu_model->insn_flags & ISA_MIPS3) { + env->SEGMask |= 3ULL << 62; + } +#endif + env->PABITS = env->cpu_model->PABITS; + env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; + env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; + env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; + env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; + env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; + env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; + env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; + env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; + env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; + env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; + env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; + env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; + env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; + env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; + env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; + env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; + env->msair = env->cpu_model->MSAIR; + env->insn_flags = env->cpu_model->insn_flags; + +#if defined(CONFIG_USER_ONLY) + env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); +# ifdef TARGET_MIPS64 + /* Enable 64-bit register mode. */ + env->CP0_Status |= (1 << CP0St_PX); +# endif +# ifdef TARGET_ABI_MIPSN64 + /* Enable 64-bit address mode. */ + env->CP0_Status |= (1 << CP0St_UX); +# endif + /* + * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR + * hardware registers. + */ + env->CP0_HWREna |= 0x0000000F; + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + env->CP0_Status |= (1 << CP0St_CU1); + } + if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { + env->CP0_Status |= (1 << CP0St_MX); + } +# if defined(TARGET_MIPS64) + /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ + if ((env->CP0_Config1 & (1 << CP0C1_FP)) && + (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { + env->CP0_Status |= (1 << CP0St_FR); + } +# endif +#else + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, + * come back to the jump. + */ + env->CP0_ErrorEPC = (env->active_tc.PC + - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); + } else { + env->CP0_ErrorEPC = env->active_tc.PC; + } + env->active_tc.PC = env->exception_base; + env->CP0_Random = env->tlb->nb_tlb - 1; + env->tlb->tlb_in_use = env->tlb->nb_tlb; + env->CP0_Wired = 0; + env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; + env->CP0_EBase = (cs->cpu_index & 0x3FF); + if (mips_um_ksegs_enabled()) { + env->CP0_EBase |= 0x40000000; + } else { + env->CP0_EBase |= (int32_t)0x80000000; + } + if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { + env->CP0_CMGCRBase = 0x1fbf8000 >> 4; + } + env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? + 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; + env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); + /* + * Vectored interrupts not implemented, timer on int 7, + * no performance counters. + */ + env->CP0_IntCtl = 0xe0000000; + { + int i; + + for (i = 0; i < 7; i++) { + env->CP0_WatchLo[i] = 0; + env->CP0_WatchHi[i] = 0x80000000; + } + env->CP0_WatchLo[7] = 0; + env->CP0_WatchHi[7] = 0; + } + /* Count register increments in debug mode, EJTAG version 1 */ + env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); + + cpu_mips_store_count(env, 1); + + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + int i; + + /* Only TC0 on VPE 0 starts as active. */ + for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { + env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; + env->tcs[i].CP0_TCHalt = 1; + } + env->active_tc.CP0_TCHalt = 1; + cs->halted = 1; + + if (cs->cpu_index == 0) { + /* VPE0 starts up enabled. */ + env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); + env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); + + /* TC0 starts up unhalted. */ + cs->halted = 0; + env->active_tc.CP0_TCHalt = 0; + env->tcs[0].CP0_TCHalt = 0; + /* With thread 0 active. */ + env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); + env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); + } + } + + /* + * Configure default legacy segmentation control. We use this regardless of + * whether segmentation control is presented to the guest. + */ + /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ + env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); + /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ + env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; + /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ + env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | + (2 << CP0SC_C); + /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ + env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | + (3 << CP0SC_C)) << 16; + /* USeg (seg4 0x40000000..0x7FFFFFFF) */ + env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | + (1 << CP0SC_EU) | (2 << CP0SC_C); + /* USeg (seg5 0x00000000..0x3FFFFFFF) */ + env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | + (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; + /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ + env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); +#endif + if ((env->insn_flags & ISA_MIPS32R6) && + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ + env->CP0_Status |= (1 << CP0St_FR); + } + + if (env->insn_flags & ISA_MIPS32R6) { + /* PTW = 1 */ + env->CP0_PWSize = 0x40; + /* GDI = 12 */ + /* UDI = 12 */ + /* MDI = 12 */ + /* PRI = 12 */ + /* PTEI = 2 */ + env->CP0_PWField = 0x0C30C302; + } else { + /* GDI = 0 */ + /* UDI = 0 */ + /* MDI = 0 */ + /* PRI = 0 */ + /* PTEI = 2 */ + env->CP0_PWField = 0x02; + } + + if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { + /* microMIPS on reset when Config3.ISA is 3 */ + env->hflags |= MIPS_HFLAG_M16; + } + + /* MSA */ + if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + msa_reset(env); + } + + compute_hflags(env); + restore_fp_status(env); + restore_pamask(env); + cs->exception_index = EXCP_NONE; + + if (semihosting_get_argc()) { + /* UHI interface can be used to obtain argc and argv */ + env->active_tc.gpr[4] = -1; + } +} + static void mips_cpu_reset(DeviceState *dev) { CPUState *s = CPU(dev); diff --git a/target/mips/translate.c b/target/mips/translate.c index dbb71fdaa5d..19933b7868c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31753,246 +31753,6 @@ void mips_tcg_init(void) #endif } -#include "translate_init.c.inc" - -void cpu_mips_realize_env(CPUMIPSState *env) -{ - env->exception_base = (int32_t)0xBFC00000; - -#ifndef CONFIG_USER_ONLY - mmu_init(env, env->cpu_model); -#endif - fpu_init(env, env->cpu_model); - mvp_init(env, env->cpu_model); -} - -void cpu_state_reset(CPUMIPSState *env) -{ - CPUState *cs = env_cpu(env); - - /* Reset registers to their default values */ - env->CP0_PRid = env->cpu_model->CP0_PRid; - env->CP0_Config0 = env->cpu_model->CP0_Config0; -#ifdef TARGET_WORDS_BIGENDIAN - env->CP0_Config0 |= (1 << CP0C0_BE); -#endif - env->CP0_Config1 = env->cpu_model->CP0_Config1; - env->CP0_Config2 = env->cpu_model->CP0_Config2; - env->CP0_Config3 = env->cpu_model->CP0_Config3; - env->CP0_Config4 = env->cpu_model->CP0_Config4; - env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; - env->CP0_Config5 = env->cpu_model->CP0_Config5; - env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; - env->CP0_Config6 = env->cpu_model->CP0_Config6; - env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; - env->CP0_Config7 = env->cpu_model->CP0_Config7; - env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; - env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask - << env->cpu_model->CP0_LLAddr_shift; - env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; - env->SYNCI_Step = env->cpu_model->SYNCI_Step; - env->CCRes = env->cpu_model->CCRes; - env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; - env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; - env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; - env->current_tc = 0; - env->SEGBITS = env->cpu_model->SEGBITS; - env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); -#if defined(TARGET_MIPS64) - if (env->cpu_model->insn_flags & ISA_MIPS3) { - env->SEGMask |= 3ULL << 62; - } -#endif - env->PABITS = env->cpu_model->PABITS; - env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; - env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; - env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; - env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; - env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; - env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; - env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; - env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; - env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; - env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; - env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; - env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; - env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; - env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; - env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; - env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; - env->msair = env->cpu_model->MSAIR; - env->insn_flags = env->cpu_model->insn_flags; - -#if defined(CONFIG_USER_ONLY) - env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); -# ifdef TARGET_MIPS64 - /* Enable 64-bit register mode. */ - env->CP0_Status |= (1 << CP0St_PX); -# endif -# ifdef TARGET_ABI_MIPSN64 - /* Enable 64-bit address mode. */ - env->CP0_Status |= (1 << CP0St_UX); -# endif - /* - * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR - * hardware registers. - */ - env->CP0_HWREna |= 0x0000000F; - if (env->CP0_Config1 & (1 << CP0C1_FP)) { - env->CP0_Status |= (1 << CP0St_CU1); - } - if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { - env->CP0_Status |= (1 << CP0St_MX); - } -# if defined(TARGET_MIPS64) - /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ - if ((env->CP0_Config1 & (1 << CP0C1_FP)) && - (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { - env->CP0_Status |= (1 << CP0St_FR); - } -# endif -#else - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, - * come back to the jump. - */ - env->CP0_ErrorEPC = (env->active_tc.PC - - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); - } else { - env->CP0_ErrorEPC = env->active_tc.PC; - } - env->active_tc.PC = env->exception_base; - env->CP0_Random = env->tlb->nb_tlb - 1; - env->tlb->tlb_in_use = env->tlb->nb_tlb; - env->CP0_Wired = 0; - env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; - env->CP0_EBase = (cs->cpu_index & 0x3FF); - if (mips_um_ksegs_enabled()) { - env->CP0_EBase |= 0x40000000; - } else { - env->CP0_EBase |= (int32_t)0x80000000; - } - if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { - env->CP0_CMGCRBase = 0x1fbf8000 >> 4; - } - env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? - 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; - env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); - /* - * Vectored interrupts not implemented, timer on int 7, - * no performance counters. - */ - env->CP0_IntCtl = 0xe0000000; - { - int i; - - for (i = 0; i < 7; i++) { - env->CP0_WatchLo[i] = 0; - env->CP0_WatchHi[i] = 0x80000000; - } - env->CP0_WatchLo[7] = 0; - env->CP0_WatchHi[7] = 0; - } - /* Count register increments in debug mode, EJTAG version 1 */ - env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); - - cpu_mips_store_count(env, 1); - - if (env->CP0_Config3 & (1 << CP0C3_MT)) { - int i; - - /* Only TC0 on VPE 0 starts as active. */ - for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { - env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; - env->tcs[i].CP0_TCHalt = 1; - } - env->active_tc.CP0_TCHalt = 1; - cs->halted = 1; - - if (cs->cpu_index == 0) { - /* VPE0 starts up enabled. */ - env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); - env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); - - /* TC0 starts up unhalted. */ - cs->halted = 0; - env->active_tc.CP0_TCHalt = 0; - env->tcs[0].CP0_TCHalt = 0; - /* With thread 0 active. */ - env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); - env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); - } - } - - /* - * Configure default legacy segmentation control. We use this regardless of - * whether segmentation control is presented to the guest. - */ - /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ - env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); - /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ - env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; - /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ - env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | - (2 << CP0SC_C); - /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ - env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | - (3 << CP0SC_C)) << 16; - /* USeg (seg4 0x40000000..0x7FFFFFFF) */ - env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | - (1 << CP0SC_EU) | (2 << CP0SC_C); - /* USeg (seg5 0x00000000..0x3FFFFFFF) */ - env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | - (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; - /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ - env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); -#endif - if ((env->insn_flags & ISA_MIPS32R6) && - (env->active_fpu.fcr0 & (1 << FCR0_F64))) { - /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ - env->CP0_Status |= (1 << CP0St_FR); - } - - if (env->insn_flags & ISA_MIPS32R6) { - /* PTW = 1 */ - env->CP0_PWSize = 0x40; - /* GDI = 12 */ - /* UDI = 12 */ - /* MDI = 12 */ - /* PRI = 12 */ - /* PTEI = 2 */ - env->CP0_PWField = 0x0C30C302; - } else { - /* GDI = 0 */ - /* UDI = 0 */ - /* MDI = 0 */ - /* PRI = 0 */ - /* PTEI = 2 */ - env->CP0_PWField = 0x02; - } - - if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { - /* microMIPS on reset when Config3.ISA is 3 */ - env->hflags |= MIPS_HFLAG_M16; - } - - /* MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { - msa_reset(env); - } - - compute_hflags(env); - restore_fp_status(env); - restore_pamask(env); - cs->exception_index = EXCP_NONE; - - if (semihosting_get_argc()) { - /* UHI interface can be used to obtain argc and argv */ - env->active_tc.gpr[4] = -1; - } -} - void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, target_ulong *data) { From patchwork Sun Dec 6 23:39:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D237FC1B0E3 for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id y2sm12424711wrn.31.2020.12.06.15.41.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:41:13 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 16/19] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn() Date: Mon, 7 Dec 2020 00:39:46 +0100 Message-Id: <20201206233949.3783184-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1073db7f257..899a746c3e5 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -104,17 +104,6 @@ static bool mips_cpu_has_work(CPUState *cs) #include "translate_init.c.inc" -static void cpu_mips_realize_env(CPUMIPSState *env) -{ - env->exception_base = (int32_t)0xBFC00000; - -#ifndef CONFIG_USER_ONLY - mmu_init(env, env->cpu_model); -#endif - fpu_init(env, env->cpu_model); - mvp_init(env, env->cpu_model); -} - /* TODO QOM'ify CPU reset and remove */ static void cpu_state_reset(CPUMIPSState *env) { @@ -400,6 +389,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); MIPSCPU *cpu = MIPS_CPU(dev); + CPUMIPSState *env = &cpu->env; MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); Error *local_err = NULL; @@ -423,7 +413,13 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) return; } - cpu_mips_realize_env(&cpu->env); + env->exception_base = (int32_t)0xBFC00000; + +#ifndef CONFIG_USER_ONLY + mmu_init(env, env->cpu_model); +#endif + fpu_init(env, env->cpu_model); + mvp_init(env, env->cpu_model); cpu_reset(cs); qemu_init_vcpu(cs); From patchwork Sun Dec 6 23:39:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2446AC2BB3F for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id c4sm12542853wmf.19.2020.12.06.15.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:41:18 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [PATCH 17/19] target/mips: Rename translate_init.c as cpu-defs.c Date: Mon, 7 Dec 2020 00:39:47 +0100 Message-Id: <20201206233949.3783184-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This file is not TCG specific, contains CPU definitions and is consumed by cpu.c. Rename it as such. Signed-off-by: Philippe Mathieu-Daudé --- cpu-defs.c still contains fpu_init()/mvp_init()/msa_reset(). They are moved out in different series (already posted). --- target/mips/cpu.c | 11 ++++++++++- target/mips/{translate_init.c.inc => cpu-defs.c.inc} | 9 --------- 2 files changed, 10 insertions(+), 10 deletions(-) rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (99%) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 899a746c3e5..8a4486e3ea1 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -102,7 +102,16 @@ static bool mips_cpu_has_work(CPUState *cs) return has_work; } -#include "translate_init.c.inc" +#include "cpu-defs.c.inc" + +void mips_cpu_list(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { + qemu_printf("MIPS '%s'\n", mips_defs[i].name); + } +} /* TODO QOM'ify CPU reset and remove */ static void cpu_state_reset(CPUMIPSState *env) diff --git a/target/mips/translate_init.c.inc b/target/mips/cpu-defs.c.inc similarity index 99% rename from target/mips/translate_init.c.inc rename to target/mips/cpu-defs.c.inc index f3daf451a63..ad578cb8601 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -922,15 +922,6 @@ const mips_def_t mips_defs[] = }; const int mips_defs_number = ARRAY_SIZE(mips_defs); -void mips_cpu_list(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { - qemu_printf("MIPS '%s'\n", mips_defs[i].name); - } -} - static void fpu_init (CPUMIPSState *env, const mips_def_t *def) { int i; From patchwork Sun Dec 6 23:39:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11954537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C4FFC433FE for ; Sun, 6 Dec 2020 23:41:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2FF62208DB for ; Sun, 6 Dec 2020 23:41:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728618AbgLFXll (ORCPT ); Sun, 6 Dec 2020 18:41:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728611AbgLFXlk (ORCPT ); Sun, 6 Dec 2020 18:41:40 -0500 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BA56C0613D0 for ; Sun, 6 Dec 2020 15:41:25 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id y23so470512wmi.1 for ; Sun, 06 Dec 2020 15:41:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n+99MQGfH3ws6+hiYTWg+4rrAybzJdIAfbn40ls3kQA=; b=VW7WqeZgfbUIfta173CGJdeR7dfKwzewm7EoRtrSTO3x2mRpzvi/abkbHam9G6TPmD fOWKGB5uSYlElBasR+JVTRkpCVm/f4pr/gp5FexX/gdYKuhCyg4/YwWL02Y4NIVN9Qvg mvAZRAGn7l76CGVBQIjCOWULmL75Jzm7VMVvtBzBZ1kYOqiiEU0U3jdanI7NTWe4+3mh 1MoBYxSHGJhuoYW4J8XDLyPxiEUMMce3/BUASEjZNDYU0tBwohxoZFZy1ZGoSzAgS2Kd ythIuTFf8f+DcYsKh11ijcuxb1Z71ALIS3u/xf/r8xrHnJYBiSwGVX59EedQkDDqfDh1 xFOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=n+99MQGfH3ws6+hiYTWg+4rrAybzJdIAfbn40ls3kQA=; b=JW8kdDP7RU69zpx7j6DVFp15s33NByX7efLO1osb1e7d1GLXqSPSktdva9OliGgLmF zNpKdH5ChFo7Z8RFM9LPVN8kiQvcbVw3cFjefYXLWoFuwwmT+xR0FylHtq83EJ56x7Ox P2eIlDISHbciaoh0vpIcKPOPw4UAYhb4tatJRK2t72JUZH4L8sx0DbAGmA0Yt8Rcdqi4 /W3EOzVjtGdv2vFMyKFQEmajBX4Bo996cqyT60rJ3Lf8KLLQVfTpZxYVuTRd2n2k6ynf xlodhs9Fe9ynKAZzFzypelsLHh//F7RiFv4YWnGhibRMdW+CBplM6z+oTyNpkSpOqxuR xegw== X-Gm-Message-State: AOAM533FfdF1eQTpzVUiOQS70Kdg5o9ZtwuNy7186DTpKwl9A5LMBMI4 3wNW8mEhZjldfqwK7qh8f4k= X-Google-Smtp-Source: ABdhPJyjns/B798+mFTm2wm7XE4zN7sKqY5G1A3JKvnUaOePKo4NsA6M8H2M1DJdBlQYE86l4bMqfQ== X-Received: by 2002:a1c:7218:: with SMTP id n24mr15456149wmc.186.1607298084105; Sun, 06 Dec 2020 15:41:24 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id c2sm13819964wrf.68.2020.12.06.15.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:41:23 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini , Claudio Fontana Subject: [RFC PATCH 18/19] target/mips: Restrict some TCG specific CPUClass handlers Date: Mon, 7 Dec 2020 00:39:48 +0100 Message-Id: <20201206233949.3783184-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Restrict the following CPUClass handlers to TCG: - do_interrupt - do_transaction_failed - do_unaligned_access Signed-off-by: Philippe Mathieu-Daudé --- Cc: Claudio Fontana target/mips/cpu.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 8a4486e3ea1..03bd35b7903 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -483,7 +483,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; - cc->do_interrupt = mips_cpu_do_interrupt; cc->cpu_exec_interrupt = mips_cpu_exec_interrupt; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; @@ -491,8 +490,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->gdb_read_register = mips_cpu_gdb_read_register; cc->gdb_write_register = mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed = mips_cpu_do_transaction_failed; - cc->do_unaligned_access = mips_cpu_do_unaligned_access; + cc->do_interrupt = mips_cpu_do_interrupt; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; cc->vmsd = &vmstate_mips_cpu; #endif @@ -500,6 +498,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) #ifdef CONFIG_TCG cc->tcg_initialize = mips_tcg_init; cc->tlb_fill = mips_cpu_tlb_fill; +#if !defined(CONFIG_USER_ONLY) + cc->do_unaligned_access = mips_cpu_do_unaligned_access; + cc->do_transaction_failed = mips_cpu_do_transaction_failed; +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #endif cc->gdb_num_core_regs = 73; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id s13sm11135976wmj.28.2020.12.06.15.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Dec 2020 15:41:28 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Jiaxun Yang , Paul Burton , kvm@vger.kernel.org, Huacai Chen , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Richard Henderson , Aleksandar Rikalo , Paolo Bonzini Subject: [RFC PATCH 19/19] target/mips: Only build TCG code when CONFIG_TCG is set Date: Mon, 7 Dec 2020 00:39:49 +0100 Message-Id: <20201206233949.3783184-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201206233949.3783184-1-f4bug@amsat.org> References: <20201206233949.3783184-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- We are very close to build with '--enable-kvm --disable-tcg' :) --- target/mips/meson.build | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index c685f03fb28..ef70d9040e2 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,11 +1,13 @@ mips_ss = ss.source_set() mips_ss.add(files( - 'common_helper.c', - 'cp0_helper.c', 'cpu.c', + 'gdbstub.c', + 'common_helper.c', +)) +mips_ss.add(when: 'CONFIG_TCG', if_true: files( + 'cp0_helper.c', 'dsp_helper.c', 'fpu_helper.c', - 'gdbstub.c', 'lmmi_helper.c', 'msa_helper.c', 'op_helper.c',