From patchwork Wed Dec 9 16:30:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bertrand Marquis X-Patchwork-Id: 11961855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D83CC433FE for ; Wed, 9 Dec 2020 16:35:08 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0FF5A239E5 for ; Wed, 9 Dec 2020 16:35:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0FF5A239E5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.48537.85850 (Exim 4.92) (envelope-from ) id 1kn2Qc-0007Ev-Gf; Wed, 09 Dec 2020 16:34:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 48537.85850; Wed, 09 Dec 2020 16:34:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qc-0007Eo-DM; Wed, 09 Dec 2020 16:34:58 +0000 Received: by outflank-mailman (input) for mailman id 48537; Wed, 09 Dec 2020 16:34:56 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qa-0007Ej-Sb for xen-devel@lists.xenproject.org; Wed, 09 Dec 2020 16:34:56 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id 05ca0ee8-e161-471b-a33e-eec6b8ebd799; Wed, 09 Dec 2020 16:34:56 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BF9351FB; Wed, 9 Dec 2020 08:34:55 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F29603F68F; Wed, 9 Dec 2020 08:34:54 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 05ca0ee8-e161-471b-a33e-eec6b8ebd799 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v3 1/7] xen/arm: Add ID registers and complete cpuinfo Date: Wed, 9 Dec 2020 16:30:54 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Add definition and entries in cpuinfo for ID registers introduced in newer Arm Architecture reference manual: - ID_PFR2: processor feature register 2 - ID_DFR1: debug feature register 1 - ID_MMFR4 and ID_MMFR5: Memory model feature registers 4 and 5 - ID_ISA6: ISA Feature register 6 Add more bitfield definitions in PFR fields of cpuinfo. Add MVFR2 register definition for aarch32. Add mvfr values in cpuinfo. Add some registers definition for arm64 in sysregs as some are not always know by compilers. Initialize the new values added in cpuinfo in identify_cpu during init. Signed-off-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Fix dbg32 table size and add proper initialisation of the second entry of the table by reading ID_DFR1 register. Changes in V3: Fix typo in commit title Add MVFR2 definition and handling on aarch32 and remove specific case for mvfr field in cpuinfo (now the same on arm64 and arm32). Add MMFR4 definition if not known by the compiler. --- xen/arch/arm/cpufeature.c | 18 ++++++++++ xen/include/asm-arm/arm64/sysregs.h | 28 +++++++++++++++ xen/include/asm-arm/cpregs.h | 12 +++++++ xen/include/asm-arm/cpufeature.h | 56 ++++++++++++++++++++++++----- 4 files changed, 105 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c index 44126dbf07..bc7ee5ac95 100644 --- a/xen/arch/arm/cpufeature.c +++ b/xen/arch/arm/cpufeature.c @@ -114,15 +114,20 @@ void identify_cpu(struct cpuinfo_arm *c) c->mm64.bits[0] = READ_SYSREG64(ID_AA64MMFR0_EL1); c->mm64.bits[1] = READ_SYSREG64(ID_AA64MMFR1_EL1); + c->mm64.bits[2] = READ_SYSREG64(ID_AA64MMFR2_EL1); c->isa64.bits[0] = READ_SYSREG64(ID_AA64ISAR0_EL1); c->isa64.bits[1] = READ_SYSREG64(ID_AA64ISAR1_EL1); + + c->zfr64.bits[0] = READ_SYSREG64(ID_AA64ZFR0_EL1); #endif c->pfr32.bits[0] = READ_SYSREG32(ID_PFR0_EL1); c->pfr32.bits[1] = READ_SYSREG32(ID_PFR1_EL1); + c->pfr32.bits[2] = READ_SYSREG32(ID_PFR2_EL1); c->dbg32.bits[0] = READ_SYSREG32(ID_DFR0_EL1); + c->dbg32.bits[1] = READ_SYSREG32(ID_DFR1_EL1); c->aux32.bits[0] = READ_SYSREG32(ID_AFR0_EL1); @@ -130,6 +135,8 @@ void identify_cpu(struct cpuinfo_arm *c) c->mm32.bits[1] = READ_SYSREG32(ID_MMFR1_EL1); c->mm32.bits[2] = READ_SYSREG32(ID_MMFR2_EL1); c->mm32.bits[3] = READ_SYSREG32(ID_MMFR3_EL1); + c->mm32.bits[4] = READ_SYSREG32(ID_MMFR4_EL1); + c->mm32.bits[5] = READ_SYSREG32(ID_MMFR5_EL1); c->isa32.bits[0] = READ_SYSREG32(ID_ISAR0_EL1); c->isa32.bits[1] = READ_SYSREG32(ID_ISAR1_EL1); @@ -137,6 +144,17 @@ void identify_cpu(struct cpuinfo_arm *c) c->isa32.bits[3] = READ_SYSREG32(ID_ISAR3_EL1); c->isa32.bits[4] = READ_SYSREG32(ID_ISAR4_EL1); c->isa32.bits[5] = READ_SYSREG32(ID_ISAR5_EL1); + c->isa32.bits[6] = READ_SYSREG32(ID_ISAR6_EL1); + +#ifdef CONFIG_ARM_64 + c->mvfr.bits[0] = READ_SYSREG64(MVFR0_EL1); + c->mvfr.bits[1] = READ_SYSREG64(MVFR1_EL1); + c->mvfr.bits[2] = READ_SYSREG64(MVFR2_EL1); +#else + c->mvfr.bits[0] = READ_CP32(MVFR0); + c->mvfr.bits[1] = READ_CP32(MVFR1); + c->mvfr.bits[2] = READ_CP32(MVFR2); +#endif } /* diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h index c60029d38f..077fd95fb7 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -57,6 +57,34 @@ #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) +/* + * Define ID coprocessor registers if they are not + * already defined by the compiler. + * + * Values picked from linux kernel + */ +#ifndef ID_AA64MMFR2_EL1 +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 +#endif +#ifndef ID_PFR2_EL1 +#define ID_PFR2_EL1 S3_0_C0_C3_4 +#endif +#ifndef ID_MMFR4_EL1 +#define ID_MMFR4_EL1 S3_0_C0_C2_6 +#endif +#ifndef ID_MMFR5_EL1 +#define ID_MMFR5_EL1 S3_0_C0_C3_6 +#endif +#ifndef ID_ISAR6_EL1 +#define ID_ISAR6_EL1 S3_0_C0_C2_7 +#endif +#ifndef ID_AA64ZFR0_EL1 +#define ID_AA64ZFR0_EL1 S3_0_C0_C4_4 +#endif +#ifndef ID_DFR1_EL1 +#define ID_DFR1_EL1 S3_0_C0_C3_5 +#endif + /* Access to system registers */ #define READ_SYSREG32(name) ((uint32_t)READ_SYSREG64(name)) diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index 8fd344146e..2690ddeb7a 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -63,6 +63,8 @@ #define FPSID p10,7,c0,c0,0 /* Floating-Point System ID Register */ #define FPSCR p10,7,c1,c0,0 /* Floating-Point Status and Control Register */ #define MVFR0 p10,7,c7,c0,0 /* Media and VFP Feature Register 0 */ +#define MVFR1 p10,7,c6,c0,0 /* Media and VFP Feature Register 1 */ +#define MVFR2 p10,7,c5,c0,0 /* Media and VFP Feature Register 2 */ #define FPEXC p10,7,c8,c0,0 /* Floating-Point Exception Control Register */ #define FPINST p10,7,c9,c0,0 /* Floating-Point Instruction Register */ #define FPINST2 p10,7,c10,c0,0 /* Floating-point Instruction Register 2 */ @@ -108,18 +110,23 @@ #define MPIDR p15,0,c0,c0,5 /* Multiprocessor Affinity Register */ #define ID_PFR0 p15,0,c0,c1,0 /* Processor Feature Register 0 */ #define ID_PFR1 p15,0,c0,c1,1 /* Processor Feature Register 1 */ +#define ID_PFR2 p15,0,c0,c3,4 /* Processor Feature Register 2 */ #define ID_DFR0 p15,0,c0,c1,2 /* Debug Feature Register 0 */ +#define ID_DFR1 p15,0,c0,c3,5 /* Debug Feature Register 1 */ #define ID_AFR0 p15,0,c0,c1,3 /* Auxiliary Feature Register 0 */ #define ID_MMFR0 p15,0,c0,c1,4 /* Memory Model Feature Register 0 */ #define ID_MMFR1 p15,0,c0,c1,5 /* Memory Model Feature Register 1 */ #define ID_MMFR2 p15,0,c0,c1,6 /* Memory Model Feature Register 2 */ #define ID_MMFR3 p15,0,c0,c1,7 /* Memory Model Feature Register 3 */ +#define ID_MMFR4 p15,0,c0,c2,6 /* Memory Model Feature Register 4 */ +#define ID_MMFR5 p15,0,c0,c3,6 /* Memory Model Feature Register 5 */ #define ID_ISAR0 p15,0,c0,c2,0 /* ISA Feature Register 0 */ #define ID_ISAR1 p15,0,c0,c2,1 /* ISA Feature Register 1 */ #define ID_ISAR2 p15,0,c0,c2,2 /* ISA Feature Register 2 */ #define ID_ISAR3 p15,0,c0,c2,3 /* ISA Feature Register 3 */ #define ID_ISAR4 p15,0,c0,c2,4 /* ISA Feature Register 4 */ #define ID_ISAR5 p15,0,c0,c2,5 /* ISA Feature Register 5 */ +#define ID_ISAR6 p15,0,c0,c2,7 /* ISA Feature Register 6 */ #define CCSIDR p15,1,c0,c0,0 /* Cache Size ID Registers */ #define CLIDR p15,1,c0,c0,1 /* Cache Level ID Register */ #define CSSELR p15,2,c0,c0,0 /* Cache Size Selection Register */ @@ -312,18 +319,23 @@ #define HSTR_EL2 HSTR #define ID_AFR0_EL1 ID_AFR0 #define ID_DFR0_EL1 ID_DFR0 +#define ID_DFR1_EL1 ID_DFR1 #define ID_ISAR0_EL1 ID_ISAR0 #define ID_ISAR1_EL1 ID_ISAR1 #define ID_ISAR2_EL1 ID_ISAR2 #define ID_ISAR3_EL1 ID_ISAR3 #define ID_ISAR4_EL1 ID_ISAR4 #define ID_ISAR5_EL1 ID_ISAR5 +#define ID_ISAR6_EL1 ID_ISAR6 #define ID_MMFR0_EL1 ID_MMFR0 #define ID_MMFR1_EL1 ID_MMFR1 #define ID_MMFR2_EL1 ID_MMFR2 #define ID_MMFR3_EL1 ID_MMFR3 +#define ID_MMFR4_EL1 ID_MMFR4 +#define ID_MMFR5_EL1 ID_MMFR5 #define ID_PFR0_EL1 ID_PFR0 #define ID_PFR1_EL1 ID_PFR1 +#define ID_PFR2_EL1 ID_PFR2 #define IFSR32_EL2 IFSR #define MDCR_EL2 HDCR #define MIDR_EL1 MIDR diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index c7b5052992..6cf83d775b 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -148,6 +148,7 @@ struct cpuinfo_arm { union { uint64_t bits[2]; struct { + /* PFR0 */ unsigned long el0:4; unsigned long el1:4; unsigned long el2:4; @@ -155,9 +156,23 @@ struct cpuinfo_arm { unsigned long fp:4; /* Floating Point */ unsigned long simd:4; /* Advanced SIMD */ unsigned long gic:4; /* GIC support */ - unsigned long __res0:28; + unsigned long ras:4; + unsigned long sve:4; + unsigned long sel2:4; + unsigned long mpam:4; + unsigned long amu:4; + unsigned long dit:4; + unsigned long __res0:4; unsigned long csv2:4; - unsigned long __res1:4; + unsigned long cvs3:4; + + /* PFR1 */ + unsigned long bt:4; + unsigned long ssbs:4; + unsigned long mte:4; + unsigned long ras_frac:4; + unsigned long mpam_frac:4; + unsigned long __res1:44; }; } pfr64; @@ -170,7 +185,7 @@ struct cpuinfo_arm { } aux64; union { - uint64_t bits[2]; + uint64_t bits[3]; struct { unsigned long pa_range:4; unsigned long asid_bits:4; @@ -190,6 +205,8 @@ struct cpuinfo_arm { unsigned long pan:4; unsigned long __res1:8; unsigned long __res2:32; + + unsigned long __res3:64; }; } mm64; @@ -197,6 +214,10 @@ struct cpuinfo_arm { uint64_t bits[2]; } isa64; + struct { + uint64_t bits[1]; + } zfr64; + #endif /* @@ -204,25 +225,38 @@ struct cpuinfo_arm { * when running in 32-bit mode. */ union { - uint32_t bits[2]; + uint32_t bits[3]; struct { + /* PFR0 */ unsigned long arm:4; unsigned long thumb:4; unsigned long jazelle:4; unsigned long thumbee:4; - unsigned long __res0:16; + unsigned long csv2:4; + unsigned long amu:4; + unsigned long dit:4; + unsigned long ras:4; + /* PFR1 */ unsigned long progmodel:4; unsigned long security:4; unsigned long mprofile:4; unsigned long virt:4; unsigned long gentimer:4; - unsigned long __res1:12; + unsigned long sec_frac:4; + unsigned long virt_frac:4; + unsigned long gic:4; + + /* PFR2 */ + unsigned long csv3:4; + unsigned long ssbs:4; + unsigned long ras_frac:4; + unsigned long __res2:20; }; } pfr32; struct { - uint32_t bits[1]; + uint32_t bits[2]; } dbg32; struct { @@ -230,12 +264,16 @@ struct cpuinfo_arm { } aux32; struct { - uint32_t bits[4]; + uint32_t bits[6]; } mm32; struct { - uint32_t bits[6]; + uint32_t bits[7]; } isa32; + + struct { + uint64_t bits[3]; + } mvfr; }; extern struct cpuinfo_arm boot_cpu_data; From patchwork Wed Dec 9 16:30:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bertrand Marquis X-Patchwork-Id: 11961857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0401C4361B for ; Wed, 9 Dec 2020 16:35:09 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A03123B51 for ; Wed, 9 Dec 2020 16:35:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9A03123B51 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.48539.85874 (Exim 4.92) (envelope-from ) id 1kn2Qh-0007Ic-6p; Wed, 09 Dec 2020 16:35:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 48539.85874; Wed, 09 Dec 2020 16:35:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qh-0007IU-2q; Wed, 09 Dec 2020 16:35:03 +0000 Received: by outflank-mailman (input) for mailman id 48539; Wed, 09 Dec 2020 16:35:01 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qf-0007Ej-Oe for xen-devel@lists.xenproject.org; Wed, 09 Dec 2020 16:35:01 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id ac6edc1e-1ffb-419b-90c9-721a0d2890e0; Wed, 09 Dec 2020 16:34:56 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A3F241042; Wed, 9 Dec 2020 08:34:56 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F046C3F68F; Wed, 9 Dec 2020 08:34:55 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ac6edc1e-1ffb-419b-90c9-721a0d2890e0 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v3 2/7] xen/arm: Add arm64 ID registers definitions Date: Wed, 9 Dec 2020 16:30:55 +0000 Message-Id: <96a970e5e5d2f1b1bd0e50327857de6a8c8441f7.1607524536.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Add coprocessor registers definitions for all ID registers trapped through the TID3 bit of HSR. Those are the one that will be emulated in Xen to only publish to guests the features that are supported by Xen and that are accessible to guests. Also define a case to catch all reserved registers that should be handled as RAZ. Signed-off-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Rebase Changes in V3: Add case definition for reserved registers. --- xen/include/asm-arm/arm64/hsr.h | 66 +++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/xen/include/asm-arm/arm64/hsr.h b/xen/include/asm-arm/arm64/hsr.h index ca931dd2fe..ffe0f0007e 100644 --- a/xen/include/asm-arm/arm64/hsr.h +++ b/xen/include/asm-arm/arm64/hsr.h @@ -110,6 +110,72 @@ #define HSR_SYSREG_CNTP_CTL_EL0 HSR_SYSREG(3,3,c14,c2,1) #define HSR_SYSREG_CNTP_CVAL_EL0 HSR_SYSREG(3,3,c14,c2,2) +/* Those registers are used when HCR_EL2.TID3 is set */ +#define HSR_SYSREG_ID_PFR0_EL1 HSR_SYSREG(3,0,c0,c1,0) +#define HSR_SYSREG_ID_PFR1_EL1 HSR_SYSREG(3,0,c0,c1,1) +#define HSR_SYSREG_ID_PFR2_EL1 HSR_SYSREG(3,0,c0,c3,4) +#define HSR_SYSREG_ID_DFR0_EL1 HSR_SYSREG(3,0,c0,c1,2) +#define HSR_SYSREG_ID_DFR1_EL1 HSR_SYSREG(3,0,c0,c3,5) +#define HSR_SYSREG_ID_AFR0_EL1 HSR_SYSREG(3,0,c0,c1,3) +#define HSR_SYSREG_ID_MMFR0_EL1 HSR_SYSREG(3,0,c0,c1,4) +#define HSR_SYSREG_ID_MMFR1_EL1 HSR_SYSREG(3,0,c0,c1,5) +#define HSR_SYSREG_ID_MMFR2_EL1 HSR_SYSREG(3,0,c0,c1,6) +#define HSR_SYSREG_ID_MMFR3_EL1 HSR_SYSREG(3,0,c0,c1,7) +#define HSR_SYSREG_ID_MMFR4_EL1 HSR_SYSREG(3,0,c0,c2,6) +#define HSR_SYSREG_ID_MMFR5_EL1 HSR_SYSREG(3,0,c0,c3,6) +#define HSR_SYSREG_ID_ISAR0_EL1 HSR_SYSREG(3,0,c0,c2,0) +#define HSR_SYSREG_ID_ISAR1_EL1 HSR_SYSREG(3,0,c0,c2,1) +#define HSR_SYSREG_ID_ISAR2_EL1 HSR_SYSREG(3,0,c0,c2,2) +#define HSR_SYSREG_ID_ISAR3_EL1 HSR_SYSREG(3,0,c0,c2,3) +#define HSR_SYSREG_ID_ISAR4_EL1 HSR_SYSREG(3,0,c0,c2,4) +#define HSR_SYSREG_ID_ISAR5_EL1 HSR_SYSREG(3,0,c0,c2,5) +#define HSR_SYSREG_ID_ISAR6_EL1 HSR_SYSREG(3,0,c0,c2,7) +#define HSR_SYSREG_MVFR0_EL1 HSR_SYSREG(3,0,c0,c3,0) +#define HSR_SYSREG_MVFR1_EL1 HSR_SYSREG(3,0,c0,c3,1) +#define HSR_SYSREG_MVFR2_EL1 HSR_SYSREG(3,0,c0,c3,2) + +#define HSR_SYSREG_ID_AA64PFR0_EL1 HSR_SYSREG(3,0,c0,c4,0) +#define HSR_SYSREG_ID_AA64PFR1_EL1 HSR_SYSREG(3,0,c0,c4,1) +#define HSR_SYSREG_ID_AA64DFR0_EL1 HSR_SYSREG(3,0,c0,c5,0) +#define HSR_SYSREG_ID_AA64DFR1_EL1 HSR_SYSREG(3,0,c0,c5,1) +#define HSR_SYSREG_ID_AA64ISAR0_EL1 HSR_SYSREG(3,0,c0,c6,0) +#define HSR_SYSREG_ID_AA64ISAR1_EL1 HSR_SYSREG(3,0,c0,c6,1) +#define HSR_SYSREG_ID_AA64MMFR0_EL1 HSR_SYSREG(3,0,c0,c7,0) +#define HSR_SYSREG_ID_AA64MMFR1_EL1 HSR_SYSREG(3,0,c0,c7,1) +#define HSR_SYSREG_ID_AA64MMFR2_EL1 HSR_SYSREG(3,0,c0,c7,2) +#define HSR_SYSREG_ID_AA64AFR0_EL1 HSR_SYSREG(3,0,c0,c5,4) +#define HSR_SYSREG_ID_AA64AFR1_EL1 HSR_SYSREG(3,0,c0,c5,5) +#define HSR_SYSREG_ID_AA64ZFR0_EL1 HSR_SYSREG(3,0,c0,c4,4) + +/* + * Those cases are catching all Reserved registers trapped by TID3 which + * currently have no assignment. + * HCR.TID3 is trapping all registers in the group 3: + * Op0 == 3, op1 == 0, CRn == c0,CRm == {c1-c7}, op2 == {0-7}. + */ +#define HSR_SYSREG_TID3_RESERVED_CASE case HSR_SYSREG(3,0,c0,c3,3): \ + case HSR_SYSREG(3,0,c0,c3,7): \ + case HSR_SYSREG(3,0,c0,c4,2): \ + case HSR_SYSREG(3,0,c0,c4,3): \ + case HSR_SYSREG(3,0,c0,c4,5): \ + case HSR_SYSREG(3,0,c0,c4,6): \ + case HSR_SYSREG(3,0,c0,c4,7): \ + case HSR_SYSREG(3,0,c0,c5,2): \ + case HSR_SYSREG(3,0,c0,c5,3): \ + case HSR_SYSREG(3,0,c0,c5,6): \ + case HSR_SYSREG(3,0,c0,c5,7): \ + case HSR_SYSREG(3,0,c0,c6,2): \ + case HSR_SYSREG(3,0,c0,c6,3): \ + case HSR_SYSREG(3,0,c0,c6,4): \ + case HSR_SYSREG(3,0,c0,c6,5): \ + case HSR_SYSREG(3,0,c0,c6,6): \ + case HSR_SYSREG(3,0,c0,c6,7): \ + case HSR_SYSREG(3,0,c0,c7,3): \ + case HSR_SYSREG(3,0,c0,c7,4): \ + case HSR_SYSREG(3,0,c0,c7,5): \ + case HSR_SYSREG(3,0,c0,c7,6): \ + case HSR_SYSREG(3,0,c0,c7,7) + #endif /* __ASM_ARM_ARM64_HSR_H */ /* From patchwork Wed Dec 9 16:30:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bertrand Marquis X-Patchwork-Id: 11961863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDE89C433FE for ; Wed, 9 Dec 2020 16:35:16 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6382D23A5A for ; Wed, 9 Dec 2020 16:35:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6382D23A5A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.48541.85898 (Exim 4.92) (envelope-from ) id 1kn2Qm-0007Ps-PN; Wed, 09 Dec 2020 16:35:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 48541.85898; Wed, 09 Dec 2020 16:35:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qm-0007Pi-LG; Wed, 09 Dec 2020 16:35:08 +0000 Received: by outflank-mailman (input) for mailman id 48541; Wed, 09 Dec 2020 16:35:06 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qk-0007Ej-Ok for xen-devel@lists.xenproject.org; Wed, 09 Dec 2020 16:35:06 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id ccf3f5bc-6f3d-43aa-bb7e-dcb444f4a150; Wed, 09 Dec 2020 16:34:57 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 835F71FB; Wed, 9 Dec 2020 08:34:57 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D44463F68F; Wed, 9 Dec 2020 08:34:56 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ccf3f5bc-6f3d-43aa-bb7e-dcb444f4a150 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v3 3/7] xen/arm: create a cpuinfo structure for guest Date: Wed, 9 Dec 2020 16:30:56 +0000 Message-Id: <33f39e7f521e6f73a0dba57a8be9fb50656e1807.1607524536.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Create a cpuinfo structure for guest and mask into it the features that we do not support in Xen or that we do not want to publish to guests. Modify some values in the cpuinfo structure for guests to mask some features which we do not want to allow to guests (like AMU) or we do not support (like SVE). The code is trying to group together registers modifications for the same feature to be able in the long term to easily enable/disable a feature depending on user parameters or add other registers modification in the same place (like enabling/disabling HCR bits). Signed-off-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Rebase Changes in V3: Use current_cpu_data info instead of recalling identify_cpu --- xen/arch/arm/cpufeature.c | 51 ++++++++++++++++++++++++++++++++ xen/include/asm-arm/cpufeature.h | 2 ++ 2 files changed, 53 insertions(+) diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c index bc7ee5ac95..7255383504 100644 --- a/xen/arch/arm/cpufeature.c +++ b/xen/arch/arm/cpufeature.c @@ -24,6 +24,8 @@ DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS); +struct cpuinfo_arm __read_mostly guest_cpuinfo; + void update_cpu_capabilities(const struct arm_cpu_capabilities *caps, const char *info) { @@ -157,6 +159,55 @@ void identify_cpu(struct cpuinfo_arm *c) #endif } +/* + * This function is creating a cpuinfo structure with values modified to mask + * all cpu features that should not be published to guest. + * The created structure is then used to provide ID registers values to guests. + */ +static int __init create_guest_cpuinfo(void) +{ + /* + * TODO: The code is currently using only the features detected on the boot + * core. In the long term we should try to compute values containing only + * features supported by all cores. + */ + guest_cpuinfo = current_cpu_data; + +#ifdef CONFIG_ARM_64 + /* Disable MPAM as xen does not support it */ + guest_cpuinfo.pfr64.mpam = 0; + guest_cpuinfo.pfr64.mpam_frac = 0; + + /* Disable SVE as Xen does not support it */ + guest_cpuinfo.pfr64.sve = 0; + guest_cpuinfo.zfr64.bits[0] = 0; + + /* Disable MTE as Xen does not support it */ + guest_cpuinfo.pfr64.mte = 0; +#endif + + /* Disable AMU */ +#ifdef CONFIG_ARM_64 + guest_cpuinfo.pfr64.amu = 0; +#endif + guest_cpuinfo.pfr32.amu = 0; + + /* Disable RAS as Xen does not support it */ +#ifdef CONFIG_ARM_64 + guest_cpuinfo.pfr64.ras = 0; + guest_cpuinfo.pfr64.ras_frac = 0; +#endif + guest_cpuinfo.pfr32.ras = 0; + guest_cpuinfo.pfr32.ras_frac = 0; + + return 0; +} +/* + * This function needs to be run after all smp are started to have + * cpuinfo structures for all cores. + */ +__initcall(create_guest_cpuinfo); + /* * Local variables: * mode: C diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index 6cf83d775b..10b62bd324 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -283,6 +283,8 @@ extern void identify_cpu(struct cpuinfo_arm *); extern struct cpuinfo_arm cpu_data[]; #define current_cpu_data cpu_data[smp_processor_id()] +extern struct cpuinfo_arm guest_cpuinfo; + #endif /* __ASSEMBLY__ */ #endif From patchwork Wed Dec 9 16:30:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bertrand Marquis X-Patchwork-Id: 11961867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B998C433FE for ; Wed, 9 Dec 2020 16:35:20 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E513822BF3 for ; Wed, 9 Dec 2020 16:35:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E513822BF3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.48543.85922 (Exim 4.92) (envelope-from ) id 1kn2Qr-0007Xv-GT; Wed, 09 Dec 2020 16:35:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 48543.85922; Wed, 09 Dec 2020 16:35:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qr-0007Xh-By; Wed, 09 Dec 2020 16:35:13 +0000 Received: by outflank-mailman (input) for mailman id 48543; Wed, 09 Dec 2020 16:35:11 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qp-0007Ej-Ov for xen-devel@lists.xenproject.org; Wed, 09 Dec 2020 16:35:11 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id b11871d3-465d-40c5-a2f5-4589f0a988cb; Wed, 09 Dec 2020 16:34:58 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6728C1FB; Wed, 9 Dec 2020 08:34:58 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B6EBB3F68F; Wed, 9 Dec 2020 08:34:57 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b11871d3-465d-40c5-a2f5-4589f0a988cb From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v3 4/7] xen/arm: Add handler for ID registers on arm64 Date: Wed, 9 Dec 2020 16:30:57 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Add vsysreg emulation for registers trapped when TID3 bit is activated in HSR. The emulation is returning the value stored in cpuinfo_guest structure for know registers and is handling reserved registers as RAZ. Signed-off-by: Bertrand Marquis --- Changes in V2: Rebase Changes in V3: Fix commit message Fix code style for GENERATE_TID3_INFO declaration Add handling of reserved registers as RAZ. --- xen/arch/arm/arm64/vsysreg.c | 53 ++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 8a85507d9d..ef7a11dbdd 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -69,6 +69,14 @@ TVM_REG(CONTEXTIDR_EL1) break; \ } +/* Macro to generate easily case for ID co-processor emulation */ +#define GENERATE_TID3_INFO(reg, field, offset) \ + case HSR_SYSREG_##reg: \ + { \ + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, \ + 1, guest_cpuinfo.field.bits[offset]); \ + } + void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { @@ -259,6 +267,51 @@ void do_sysreg(struct cpu_user_regs *regs, */ return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1); + /* + * HCR_EL2.TID3 + * + * This is trapping most Identification registers used by a guest + * to identify the processor features + */ + GENERATE_TID3_INFO(ID_PFR0_EL1, pfr32, 0) + GENERATE_TID3_INFO(ID_PFR1_EL1, pfr32, 1) + GENERATE_TID3_INFO(ID_PFR2_EL1, pfr32, 2) + GENERATE_TID3_INFO(ID_DFR0_EL1, dbg32, 0) + GENERATE_TID3_INFO(ID_DFR1_EL1, dbg32, 1) + GENERATE_TID3_INFO(ID_AFR0_EL1, aux32, 0) + GENERATE_TID3_INFO(ID_MMFR0_EL1, mm32, 0) + GENERATE_TID3_INFO(ID_MMFR1_EL1, mm32, 1) + GENERATE_TID3_INFO(ID_MMFR2_EL1, mm32, 2) + GENERATE_TID3_INFO(ID_MMFR3_EL1, mm32, 3) + GENERATE_TID3_INFO(ID_MMFR4_EL1, mm32, 4) + GENERATE_TID3_INFO(ID_MMFR5_EL1, mm32, 5) + GENERATE_TID3_INFO(ID_ISAR0_EL1, isa32, 0) + GENERATE_TID3_INFO(ID_ISAR1_EL1, isa32, 1) + GENERATE_TID3_INFO(ID_ISAR2_EL1, isa32, 2) + GENERATE_TID3_INFO(ID_ISAR3_EL1, isa32, 3) + GENERATE_TID3_INFO(ID_ISAR4_EL1, isa32, 4) + GENERATE_TID3_INFO(ID_ISAR5_EL1, isa32, 5) + GENERATE_TID3_INFO(ID_ISAR6_EL1, isa32, 6) + GENERATE_TID3_INFO(MVFR0_EL1, mvfr, 0) + GENERATE_TID3_INFO(MVFR1_EL1, mvfr, 1) + GENERATE_TID3_INFO(MVFR2_EL1, mvfr, 2) + GENERATE_TID3_INFO(ID_AA64PFR0_EL1, pfr64, 0) + GENERATE_TID3_INFO(ID_AA64PFR1_EL1, pfr64, 1) + GENERATE_TID3_INFO(ID_AA64DFR0_EL1, dbg64, 0) + GENERATE_TID3_INFO(ID_AA64DFR1_EL1, dbg64, 1) + GENERATE_TID3_INFO(ID_AA64ISAR0_EL1, isa64, 0) + GENERATE_TID3_INFO(ID_AA64ISAR1_EL1, isa64, 1) + GENERATE_TID3_INFO(ID_AA64MMFR0_EL1, mm64, 0) + GENERATE_TID3_INFO(ID_AA64MMFR1_EL1, mm64, 1) + GENERATE_TID3_INFO(ID_AA64MMFR2_EL1, mm64, 2) + GENERATE_TID3_INFO(ID_AA64AFR0_EL1, aux64, 0) + GENERATE_TID3_INFO(ID_AA64AFR1_EL1, aux64, 1) + GENERATE_TID3_INFO(ID_AA64ZFR0_EL1, zfr64, 0) + + HSR_SYSREG_TID3_RESERVED_CASE: + /* Handle all reserved registers as RAZ */ + return handle_ro_raz(regs, regidx, hsr.sysreg.read, hsr, 1); + /* * HCR_EL2.TIDCP * From patchwork Wed Dec 9 16:30:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bertrand Marquis X-Patchwork-Id: 11961859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77D7FC4167B for ; Wed, 9 Dec 2020 16:35:10 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2741D239E5 for ; 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Wed, 09 Dec 2020 16:35:00 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 01d21cba-7b66-414c-baeb-6ed292fe766b; Wed, 09 Dec 2020 16:34:59 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4C7A21FB; Wed, 9 Dec 2020 08:34:59 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 99C683F68F; Wed, 9 Dec 2020 08:34:58 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 01d21cba-7b66-414c-baeb-6ed292fe766b From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v3 5/7] xen/arm: Add handler for cp15 ID registers Date: Wed, 9 Dec 2020 16:30:58 +0000 Message-Id: <5a36325410f485dbdddc0f6088378cacc54c5243.1607524536.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Add support for emulation of cp15 based ID registers (on arm32 or when running a 32bit guest on arm64). The handlers are returning the values stored in the guest_cpuinfo structure for known registers and RAZ for all reserved registers. In the current status the MVFR registers are no supported. Signed-off-by: Bertrand Marquis --- Changes in V2: Rebase Changes in V3: Add case definition for reserved registers Add handling of reserved registers as RAZ. Fix code style in GENERATE_TID3_INFO declaration --- xen/arch/arm/vcpreg.c | 39 ++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/cpregs.h | 25 +++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index cdc91cdf5b..d371a1c38c 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -155,6 +155,14 @@ TVM_REG32(CONTEXTIDR, CONTEXTIDR_EL1) break; \ } +/* Macro to generate easily case for ID co-processor emulation */ +#define GENERATE_TID3_INFO(reg, field, offset) \ + case HSR_CPREG32(reg): \ + { \ + return handle_ro_read_val(regs, regidx, cp32.read, hsr, \ + 1, guest_cpuinfo.field.bits[offset]); \ + } + void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) { const struct hsr_cp32 cp32 = hsr.cp32; @@ -286,6 +294,37 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) */ return handle_raz_wi(regs, regidx, cp32.read, hsr, 1); + /* + * HCR_EL2.TID3 + * + * This is trapping most Identification registers used by a guest + * to identify the processor features + */ + GENERATE_TID3_INFO(ID_PFR0, pfr32, 0) + GENERATE_TID3_INFO(ID_PFR1, pfr32, 1) + GENERATE_TID3_INFO(ID_PFR2, pfr32, 2) + GENERATE_TID3_INFO(ID_DFR0, dbg32, 0) + GENERATE_TID3_INFO(ID_DFR1, dbg32, 1) + GENERATE_TID3_INFO(ID_AFR0, aux32, 0) + GENERATE_TID3_INFO(ID_MMFR0, mm32, 0) + GENERATE_TID3_INFO(ID_MMFR1, mm32, 1) + GENERATE_TID3_INFO(ID_MMFR2, mm32, 2) + GENERATE_TID3_INFO(ID_MMFR3, mm32, 3) + GENERATE_TID3_INFO(ID_MMFR4, mm32, 4) + GENERATE_TID3_INFO(ID_MMFR5, mm32, 5) + GENERATE_TID3_INFO(ID_ISAR0, isa32, 0) + GENERATE_TID3_INFO(ID_ISAR1, isa32, 1) + GENERATE_TID3_INFO(ID_ISAR2, isa32, 2) + GENERATE_TID3_INFO(ID_ISAR3, isa32, 3) + GENERATE_TID3_INFO(ID_ISAR4, isa32, 4) + GENERATE_TID3_INFO(ID_ISAR5, isa32, 5) + GENERATE_TID3_INFO(ID_ISAR6, isa32, 6) + /* MVFR registers are in cp10 no cp15 */ + + HSR_CPREG32_TID3_RESERVED_CASE: + /* Handle all reserved registers as RAZ */ + return handle_ro_raz(regs, regidx, cp32.read, hsr, 1); + /* * HCR_EL2.TIDCP * diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index 2690ddeb7a..5cb1ad5cbe 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -133,6 +133,31 @@ #define VPIDR p15,4,c0,c0,0 /* Virtualization Processor ID Register */ #define VMPIDR p15,4,c0,c0,5 /* Virtualization Multiprocessor ID Register */ +/* + * Those cases are catching all Reserved registers trapped by TID3 which + * currently have no assignment. + * HCR.TID3 is trapping all registers in the group 3: + * coproc == p15, opc1 == 0, CRn == c0, CRm == {c2-c7}, opc2 == {0-7}. + */ +#define HSR_CPREG32_TID3_CASES(REG) case HSR_CPREG32(p15,0,c0,REG,0): \ + case HSR_CPREG32(p15,0,c0,REG,1): \ + case HSR_CPREG32(p15,0,c0,REG,2): \ + case HSR_CPREG32(p15,0,c0,REG,3): \ + case HSR_CPREG32(p15,0,c0,REG,4): \ + case HSR_CPREG32(p15,0,c0,REG,5): \ + case HSR_CPREG32(p15,0,c0,REG,6): \ + case HSR_CPREG32(p15,0,c0,REG,7) + +#define HSR_CPREG32_TID3_RESERVED_CASE case HSR_CPREG32(p15,0,c0,c3,0): \ + case HSR_CPREG32(p15,0,c0,c3,1): \ + case HSR_CPREG32(p15,0,c0,c3,2): \ + case HSR_CPREG32(p15,0,c0,c3,3): \ + case HSR_CPREG32(p15,0,c0,c3,7): \ + HSR_CPREG32_TID3_CASES(c4): \ + HSR_CPREG32_TID3_CASES(c5): \ + HSR_CPREG32_TID3_CASES(c6): \ + HSR_CPREG32_TID3_CASES(c7) + /* CP15 CR1: System Control Registers */ #define SCTLR p15,0,c1,c0,0 /* System Control Register */ #define ACTLR p15,0,c1,c0,1 /* Auxiliary Control Register */ From patchwork Wed Dec 9 16:30:59 2020 Content-Type: text/plain; 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Wed, 09 Dec 2020 16:35:00 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2C67B1042; Wed, 9 Dec 2020 08:35:00 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7C9EE3F68F; Wed, 9 Dec 2020 08:34:59 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 6af9f6ac-e876-40fd-afa6-506424aaec58 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v3 6/7] xen/arm: Add CP10 exception support to handle MVFR Date: Wed, 9 Dec 2020 16:30:59 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Add support for cp10 exceptions decoding to be able to emulate the values for MVFR0, MVFR1 and MVFR2 when TID3 bit of HSR is activated. This is required for aarch32 guests accessing MVFR registers using vmrs and vmsr instructions. Signed-off-by: Bertrand Marquis --- Changes in V2: Rebase Changes in V3: Add case for MVFR2, fix typo VMFR <-> MVFR. --- xen/arch/arm/traps.c | 5 ++++ xen/arch/arm/vcpreg.c | 39 +++++++++++++++++++++++++++++++- xen/include/asm-arm/perfc_defn.h | 1 + xen/include/asm-arm/traps.h | 1 + 4 files changed, 45 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 22bd1bd4c6..28d9d64558 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2097,6 +2097,11 @@ void do_trap_guest_sync(struct cpu_user_regs *regs) perfc_incr(trap_cp14_dbg); do_cp14_dbg(regs, hsr); break; + case HSR_EC_CP10: + GUEST_BUG_ON(!psr_mode_is_32bit(regs)); + perfc_incr(trap_cp10); + do_cp10(regs, hsr); + break; case HSR_EC_CP: GUEST_BUG_ON(!psr_mode_is_32bit(regs)); perfc_incr(trap_cp); diff --git a/xen/arch/arm/vcpreg.c b/xen/arch/arm/vcpreg.c index d371a1c38c..da4e22a467 100644 --- a/xen/arch/arm/vcpreg.c +++ b/xen/arch/arm/vcpreg.c @@ -319,7 +319,7 @@ void do_cp15_32(struct cpu_user_regs *regs, const union hsr hsr) GENERATE_TID3_INFO(ID_ISAR4, isa32, 4) GENERATE_TID3_INFO(ID_ISAR5, isa32, 5) GENERATE_TID3_INFO(ID_ISAR6, isa32, 6) - /* MVFR registers are in cp10 no cp15 */ + /* MVFR registers are in cp10 not cp15 */ HSR_CPREG32_TID3_RESERVED_CASE: /* Handle all reserved registers as RAZ */ @@ -638,6 +638,43 @@ void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr) inject_undef_exception(regs, hsr); } +void do_cp10(struct cpu_user_regs *regs, const union hsr hsr) +{ + const struct hsr_cp32 cp32 = hsr.cp32; + int regidx = cp32.reg; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP32_REGS_MASK ) + { + /* + * HSR.TID3 is trapping access to MVFR register used to identify the + * VFP/Simd using VMRS/VMSR instructions. + * Exception encoding is using MRC/MCR standard with the reg field in Crn + * as are declared MVFR0 and MVFR1 in cpregs.h + */ + GENERATE_TID3_INFO(MVFR0, mvfr, 0) + GENERATE_TID3_INFO(MVFR1, mvfr, 1) + GENERATE_TID3_INFO(MVFR2, mvfr, 2) + + default: + gdprintk(XENLOG_ERR, + "%s p10, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit CP10 access %#x\n", + hsr.bits & HSR_CP32_REGS_MASK); + inject_undef_exception(regs, hsr); + return; + } + + advance_pc(regs, hsr); +} + void do_cp(struct cpu_user_regs *regs, const union hsr hsr) { const struct hsr_cp cp = hsr.cp; diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_defn.h index 6a83185163..31f071222b 100644 --- a/xen/include/asm-arm/perfc_defn.h +++ b/xen/include/asm-arm/perfc_defn.h @@ -11,6 +11,7 @@ PERFCOUNTER(trap_cp15_64, "trap: cp15 64-bit access") PERFCOUNTER(trap_cp14_32, "trap: cp14 32-bit access") PERFCOUNTER(trap_cp14_64, "trap: cp14 64-bit access") PERFCOUNTER(trap_cp14_dbg, "trap: cp14 dbg access") +PERFCOUNTER(trap_cp10, "trap: cp10 access") PERFCOUNTER(trap_cp, "trap: cp access") PERFCOUNTER(trap_smc32, "trap: 32-bit smc") PERFCOUNTER(trap_hvc32, "trap: 32-bit hvc") diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h index 997c37884e..c4a3d0fb1b 100644 --- a/xen/include/asm-arm/traps.h +++ b/xen/include/asm-arm/traps.h @@ -62,6 +62,7 @@ void do_cp15_64(struct cpu_user_regs *regs, const union hsr hsr); void do_cp14_32(struct cpu_user_regs *regs, const union hsr hsr); void do_cp14_64(struct cpu_user_regs *regs, const union hsr hsr); void do_cp14_dbg(struct cpu_user_regs *regs, const union hsr hsr); +void do_cp10(struct cpu_user_regs *regs, const union hsr hsr); void do_cp(struct cpu_user_regs *regs, const union hsr hsr); /* SMCCC handling */ From patchwork Wed Dec 9 16:31:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bertrand Marquis X-Patchwork-Id: 11961865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 209E5C4361B for ; Wed, 9 Dec 2020 16:35:19 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C517223A5A for ; Wed, 9 Dec 2020 16:35:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C517223A5A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.48542.85910 (Exim 4.92) (envelope-from ) id 1kn2Qp-0007Tq-6b; Wed, 09 Dec 2020 16:35:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 48542.85910; Wed, 09 Dec 2020 16:35:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qp-0007Te-1F; Wed, 09 Dec 2020 16:35:11 +0000 Received: by outflank-mailman (input) for mailman id 48542; Wed, 09 Dec 2020 16:35:10 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1kn2Qo-0007Fp-F9 for xen-devel@lists.xenproject.org; Wed, 09 Dec 2020 16:35:10 +0000 Received: from foss.arm.com (unknown [217.140.110.172]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id b4d68c8c-474d-45c1-be3a-5e462c638463; Wed, 09 Dec 2020 16:35:01 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 108B31FB; Wed, 9 Dec 2020 08:35:01 -0800 (PST) Received: from e109506-lin.cambridge.arm.com (e109506-lin.cambridge.arm.com [10.1.199.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5FE4A3F68F; Wed, 9 Dec 2020 08:35:00 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b4d68c8c-474d-45c1-be3a-5e462c638463 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Volodymyr Babchuk Subject: [PATCH v3 7/7] xen/arm: Activate TID3 in HCR_EL2 Date: Wed, 9 Dec 2020 16:31:00 +0000 Message-Id: <956cf336ffce24f0cabfc7a98ae855bc71d5f028.1607524536.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Activate TID3 bit in HSR register when starting a guest. This will trap all coprecessor ID registers so that we can give to guest values corresponding to what they can actually use and mask some features to guests even though they would be supported by the underlying hardware (like SVE or MPAM). Signed-off-by: Bertrand Marquis Reviewed-by: Stefano Stabellini --- Changes in V2: Rebase Changes in V3: Rebase --- xen/arch/arm/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 28d9d64558..c1a9ad6056 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -98,7 +98,7 @@ register_t get_default_hcr_flags(void) { return (HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM| (vwfi != NATIVE ? (HCR_TWI|HCR_TWE) : 0) | - HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); + HCR_TID3|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); } static enum {