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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id b4sm27219980wrr.30.2020.12.13.12.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:19:53 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Huacai Chen Subject: [PULL 01/26] MAINTAINERS: chenhc@lemote.com -> chenhuacai@kernel.org Date: Sun, 13 Dec 2020 21:19:21 +0100 Message-Id: <20201213201946.236123-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Huacai Chen Use @kernel.org address as the main communications end point. Update the corresponding M-entries and .mailmap (for git shortlog translation). Signed-off-by: Huacai Chen Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-Id: <1607160121-9977-1-git-send-email-chenhuacai@kernel.org> --- .mailmap | 2 ++ MAINTAINERS | 8 ++++---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/.mailmap b/.mailmap index 663819fb017..a1bd659817d 100644 --- a/.mailmap +++ b/.mailmap @@ -49,6 +49,8 @@ Anthony Liguori Anthony Liguori Filip Bozuta Frederic Konrad Greg Kurz +Huacai Chen +Huacai Chen James Hogan Leif Lindholm Radoslaw Biernacki diff --git a/MAINTAINERS b/MAINTAINERS index d48a4e8a8b7..d396c5943b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -388,7 +388,7 @@ S: Maintained F: target/arm/kvm.c MIPS KVM CPUs -M: Huacai Chen +M: Huacai Chen S: Odd Fixes F: target/mips/kvm.c @@ -1149,7 +1149,7 @@ F: hw/mips/mipssim.c F: hw/net/mipsnet.c Fuloong 2E -M: Huacai Chen +M: Huacai Chen M: Philippe Mathieu-Daudé R: Jiaxun Yang S: Odd Fixes @@ -1159,7 +1159,7 @@ F: hw/pci-host/bonito.c F: include/hw/isa/vt82c686.h Loongson-3 virtual platforms -M: Huacai Chen +M: Huacai Chen R: Jiaxun Yang S: Maintained F: hw/intc/loongson_liointc.c @@ -2861,7 +2861,7 @@ F: disas/i386.c MIPS TCG target M: Philippe Mathieu-Daudé R: Aurelien Jarno -R: Huacai Chen +R: Huacai Chen R: Jiaxun Yang R: Aleksandar Rikalo S: Odd Fixes From patchwork Sun Dec 13 20:19:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11970977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14681C4167B for ; Sun, 13 Dec 2020 20:20:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB13323976 for ; Sun, 13 Dec 2020 20:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733047AbgLMUUl (ORCPT ); Sun, 13 Dec 2020 15:20:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726787AbgLMUUl (ORCPT ); Sun, 13 Dec 2020 15:20:41 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2ED14C0613D6 for ; Sun, 13 Dec 2020 12:20:00 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id a3so13415393wmb.5 for ; Sun, 13 Dec 2020 12:20:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=39WDzgrzKw1HI9cbUqd/4nglotTqMx2ozVZiEV9EMeo=; b=HNeZlXVtc7YfjiBul+Rccx5JKDxdpjacjieOOVNOFISfGRL06tM3qvroTYE1jrNqfZ QcQZ6KXhyY8ucZpcziHxytnf1cM0TZk40qOl4gCcD0ZGmVx58ssLywumZ+c9fOCHu7m/ PtVXnTWWnDmZapEKqWpEOAguvf/tkTkTOMpwnZ1vEYZpOk7KOwKwkrlIjfkj9yeg02XR 49rsclJmeSCajmC5NXGljEy7aevH63eryJL068edfTaKTGUOTDnQvoa1lBKogaNAcPjv ZoOTWDi0x/6iJHEro0xLrcAF7PruNCGo9iVGZ9vqukZaNKkNUCuThrGHNzuoYEjeGC7d vq9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=39WDzgrzKw1HI9cbUqd/4nglotTqMx2ozVZiEV9EMeo=; b=hanDPMgc2N0sc/SKYaUiiI18+8DBtm9cMsI8WZzHoVOw+Suz0L8XQhQ454myq92Bmc AxLRytS4kiyTWqv94qiYJl3GL0U9iF3/1CJ5Uu4NAUje9q8TUepQ7B4ymd1/B3+q0zOz nqDp4aMmmayY1XWkmheKqYKcfWHT9ASANAQ0pX4qDBqXdwVqKQQflANaa717qW7B1/VI ZGBoi6Z9Jn5TqyUA488ZqXAVXQiOYidCaqksBeWyeBt0H5xlF5iU191CzUfu/9t1cBE8 I/lXVMw0eA8/SZ8s1TYUoC4T8oDo0I59rMXpEba650+RiHaso397FpLf26i7PriMXhb1 1ZZw== X-Gm-Message-State: AOAM533chhznxvZkdcNUjl4Kjpo3eD6GxKjKlvYBpC5yhgvJSelO50d7 xahZX713TIAb4K9l/I5J1Ww= X-Google-Smtp-Source: ABdhPJwOC+VH1ItUocY5MR5+0dEvvtca8Eo/rZUkwGTsvktz0B4ZV7qWU/u1sqZ4Y1ulDcTps9maWw== X-Received: by 2002:a05:600c:224b:: with SMTP id a11mr24308206wmm.97.1607890798961; Sun, 13 Dec 2020 12:19:58 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id h13sm28766022wrm.28.2020.12.13.12.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:19:58 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Huacai Chen Subject: [PULL 02/26] target/mips/kvm: Assert unreachable code is not used Date: Sun, 13 Dec 2020 21:19:22 +0100 Message-Id: <20201213201946.236123-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This code must not be used outside of KVM. Abort if it is. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Huacai Chen Acked-by: Paolo Bonzini Message-Id: <20200429082916.10669-3-f4bug@amsat.org> --- target/mips/kvm.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 72637a1e021..cbd0cb8faa4 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -198,9 +198,7 @@ int kvm_mips_set_interrupt(MIPSCPU *cpu, int irq, int level) CPUState *cs = CPU(cpu); struct kvm_mips_interrupt intr; - if (!kvm_enabled()) { - return 0; - } + assert(kvm_enabled()); intr.cpu = -1; @@ -221,9 +219,7 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) CPUState *dest_cs = CPU(cpu); struct kvm_mips_interrupt intr; - if (!kvm_enabled()) { - return 0; - } + assert(kvm_enabled()); intr.cpu = dest_cs->cpu_index; From patchwork Sun Dec 13 20:19:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11970975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F19AC0018C for ; Sun, 13 Dec 2020 20:20:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0049E2396D for ; Sun, 13 Dec 2020 20:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388845AbgLMUUp (ORCPT ); Sun, 13 Dec 2020 15:20:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726787AbgLMUUp (ORCPT ); Sun, 13 Dec 2020 15:20:45 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26226C061793 for ; Sun, 13 Dec 2020 12:20:05 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id y17so14366834wrr.10 for ; Sun, 13 Dec 2020 12:20:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vNFKJu+n4IZ/CMsPrcMiCbRPKxOJx+sfVgOoT8DzTzM=; b=CyOXhXqwoUkfAHoDJ5+Gr9Hbrb+VgeWX8hIQ/FNHc3Hb7BLFVqGC3+E3dFjW5fWpK2 NRW34VR85opUiAoszJTDQUgchzByaZeYWoCmzg/UHX6imyHI2CIfws6UhWbrpp2JG8lN DTVs8W9OoeRiDkStjIGXi9phFLw/ahtRXN4O9fCNObwvwM05BNrZu7grhxs5ZqHpc1I9 kHi5SMU83DA3eaCC9teGDk+Fi5d2G7J9SdtY2nH5Igv9F1sfBYmzRaWoSXFaoftMVp9w XALx4Whce6OghuL7VrmTJH8frRaQ09eyU3UiJAn+ft+nb1E2OQE++y9J76PKMuPOPpEw 2Uew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vNFKJu+n4IZ/CMsPrcMiCbRPKxOJx+sfVgOoT8DzTzM=; b=Xsd2c1jdwtTyE9xsewqYJNHCTUVnQyXAtJjV650lUbb+CNrbRI9a1BIAkEGWjRqclf WuCeKeY1sYnAyVuLvGwCuuiQmuTr9zBF/2AKa1HG8HVIhUPSqgyjqKPk+DhSKQAfQhbk GoEWbRFyXL9/7OUmapsSKRcvMKK3jEUhLoAdXtms9nRG/+08jjT5fTUpZFRILXY69Q7e WSUZrYUzTzLiF/Drjn9AhU3ca69OJK5AKOx3RvYqlduQXaiptmT6hN248b17d3U2Zstb 6QSqNr1xmm+iFZteHEMut5sRjYVVlUQuN/p34batL5U97O3so2XzjzRtA8UOuVmMl2jL flyQ== X-Gm-Message-State: AOAM531nsB48n/PQddp9IRLtXTFwEyGC7cWiRcpJxk7KJ1WkIvdYxlMk ZicwVUK1FZ86uB2P56mgiJQ= X-Google-Smtp-Source: ABdhPJw3B2k1CxOd1n/33Sb1EtYQBldcALPKmiH+xNbh4q3vPykzdo6PwXeiPFYLzDkgmyv3WTcvCw== X-Received: by 2002:a5d:4242:: with SMTP id s2mr25494476wrr.187.1607890803857; Sun, 13 Dec 2020 12:20:03 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id d9sm29807500wrc.87.2020.12.13.12.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:03 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 03/26] target/mips/kvm: Remove unused headers Date: Sun, 13 Dec 2020 21:19:23 +0100 Message-Id: <20201213201946.236123-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-7-f4bug@amsat.org> --- target/mips/kvm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/kvm.c b/target/mips/kvm.c index cbd0cb8faa4..94b3a88d8f8 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -19,11 +19,9 @@ #include "internal.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" -#include "qemu/timer.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "sysemu/runstate.h" -#include "sysemu/cpus.h" #include "kvm_mips.h" #include "exec/memattrs.h" #include "hw/boards.h" From patchwork Sun Dec 13 20:19:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11970979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88AE9C4361B for ; Sun, 13 Dec 2020 20:21:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 54CCB2396F for ; Sun, 13 Dec 2020 20:21:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389949AbgLMUUv (ORCPT ); Sun, 13 Dec 2020 15:20:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726787AbgLMUUv (ORCPT ); Sun, 13 Dec 2020 15:20:51 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 251ADC061794 for ; Sun, 13 Dec 2020 12:20:10 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id t16so14387414wra.3 for ; Sun, 13 Dec 2020 12:20:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h9xJIRQyKnane3GYzE3+NuQLJbx63PUZ7Fm8rhK2xB8=; b=mbgZQSGvTX3mqzqH4M6D4PcWZL78hL4Wie0tg103QQUUWktW0cmRGQYR0h7V3slQhg t4gSMQ34Q5A54o0Y1Sa7R7MGoucJqp3Q0Us+rViwnYoy08Q/6oLfcMz0cdEkMESRDLRr Pi8LEeMxrAFFcLQoiRffdL7iBoiQ/mR2Dzj7OwnN+lylVIQ42+5OjzgEPKLsgfYebJJu HihK+fShS3Ky+qibhLQDYRXvfHcg3/ibMXrTXJWu5fXCMu3lLORDVMWeiJK9Sw1coYqp i+kYxZP+dhrTFNcy+GQGtkLBuIULoYdwIAI0mI2UoaytcdImai1YpdGbLcLvVZ4xDrrh X4/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=h9xJIRQyKnane3GYzE3+NuQLJbx63PUZ7Fm8rhK2xB8=; b=A6QSLURCneUPh5FqTj3D5rM0VgTPD2n3nbMR3hvWqGtzfP+B2zZx+T38LMXZKWlJ1Y +5EiAgv/Xkim8QAk9PzY9ASQuroRkYNYM+aDbxVr3/DS11Xovokd32HMfkw26Zw7vW2J Hm5teQq7OiESxbt9l/IQQnK98ann+axRZxdlv7EuAuglE2N6lz0IXoz2qvczRQ/XUuz0 qaX+2VsIGQ9vFD9183eHKmd4WATwohr7WbUqybn+4W5b/3GG+5PTl0QTyyAiWwqBuyfD 74/LWu7DHtpVa9QWnGk2tnAc0rN48+LTpK9v90KbSLqWsgUekbQVzHFJnyyofkzq1ciL 0pMA== X-Gm-Message-State: AOAM5303L3aIjMTHJPXKQrY1GKPMhthviitlT0wIYG0xXtJteGUVsyng 0zksVNDYzSjuGXH87gDvo10= X-Google-Smtp-Source: ABdhPJyhMywD88l8pOLmlXDRQKN769S3On8PU2OFuV79N9zVGRbpyseC8eMUVxtOcr1kWIil4eIZuw== X-Received: by 2002:adf:d18a:: with SMTP id v10mr25231575wrc.273.1607890808840; Sun, 13 Dec 2020 12:20:08 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id w189sm15877043wmg.31.2020.12.13.12.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:08 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 04/26] target/mips: Include "exec/memattrs.h" in 'internal.h' Date: Sun, 13 Dec 2020 21:19:24 +0100 Message-Id: <20201213201946.236123-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org mips_cpu_do_transaction_failed() requires MemTxAttrs and MemTxResult declarations. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-8-f4bug@amsat.org> --- target/mips/internal.h | 1 + target/mips/kvm.c | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index dd8a7809b64..76b7a85cbb3 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -8,6 +8,7 @@ #ifndef MIPS_INTERNAL_H #define MIPS_INTERNAL_H +#include "exec/memattrs.h" #include "fpu/softfloat-helpers.h" /* diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 94b3a88d8f8..477692566a4 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -23,7 +23,6 @@ #include "sysemu/kvm_int.h" #include "sysemu/runstate.h" #include "kvm_mips.h" -#include "exec/memattrs.h" #include "hw/boards.h" #define DEBUG_KVM 0 From patchwork Sun Dec 13 20:19:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFB7FC4361B for ; Sun, 13 Dec 2020 20:21:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 803332399A for ; Sun, 13 Dec 2020 20:21:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391069AbgLMUVL (ORCPT ); Sun, 13 Dec 2020 15:21:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726787AbgLMUVL (ORCPT ); Sun, 13 Dec 2020 15:21:11 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 299E6C06179C for ; Sun, 13 Dec 2020 12:20:15 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id e25so13417256wme.0 for ; Sun, 13 Dec 2020 12:20:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2ISNCVzJYbaoq1vI61by2IBAkaqbdNie7OHgVDeXnbA=; b=QnkMcMiqG8UVyDMMuGRox71t7T+UqZBUKvKswBUB2KOeED01VBfl1gTqc5svpwe1CC rgudl0VE4QS0bigb8esLT9df+NjBOsWyrZfVj+qQPS449oSmXo9w2OybNxuwdEVbGcnf 9OZMrO0pd1dU/wYb+ybwrpJ0agz5ct4pj1VARipaQZi2eWaE2lDbgFBkJv4TXxPQ73ds n3sXcx4L7PddPgiwLLwSksoL8J28lLeRaYWBl/pcU7PRnZTDyVwPmI//BYk9vZdt7FsQ HwBqSaqbkszXuQTYtepR5kp0AgKMRup1qCrXkbc0/S+7Kkax0P9mPw/pOaLd5c2R2Ccw wprA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2ISNCVzJYbaoq1vI61by2IBAkaqbdNie7OHgVDeXnbA=; b=q0j42VthGUdggprPYjMpqc0lG4aDrVhQeHP/FbEq+g6uLs22q4q/e7CD83LY93YdWO 2BeHZHfesxhJBTlqrM57z6a89YgjhAl89INgABQ4qOdvHpLiKetVV1peZQGdldSzq/kK 1S3CP/JtyjTAdYXsUrLgewjzZVGVeFgFLI7+eqCCbAmy+AkWtqMzxVhm6BCIR1+zVdSr nxqD2xi8Evd0JpYDVZ/Gn1VZZ6HExLhChF7PUhmBQYNtpF02pGkpBoLqG7K9YvK88j4n uYDDfIZLtBeb2XAbThTfekmxS8Y8ImV5xGVc61ODyNe7H9ktibLt/rxFQ9lpf9B3+x+6 Ep+w== X-Gm-Message-State: AOAM533s48Hp0fljAHawiY072ifxaS3bmi8GAQ1KDnznCH+gUdSn8jv8 1RF2yfoU3Q/8I+6l0ji/LzM= X-Google-Smtp-Source: ABdhPJw2ev9B7VvAvmY2StzAj4Kxo6/UL0BE2A2EbJKABhbhMiX+nTwfhVj5Xh5TwXp8OPQeLmPEsw== X-Received: by 2002:a1c:2b46:: with SMTP id r67mr24316116wmr.162.1607890813972; Sun, 13 Dec 2020 12:20:13 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id l8sm20448668wrb.73.2020.12.13.12.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:13 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson , Huacai Chen Subject: [PULL 05/26] target/mips: Replace magic values by CP0PM_MASK or TARGET_PAGE_BITS_MIN Date: Sun, 13 Dec 2020 21:19:25 +0100 Message-Id: <20201213201946.236123-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Replace magic values related to page size: 12 -> TARGET_PAGE_BITS_MIN 13 -> CP0PM_MASK Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Huacai Chen Message-Id: <20201109090422.2445166-2-f4bug@amsat.org> --- target/mips/cp0_helper.c | 5 +++-- target/mips/helper.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index a1b5140ccaf..e8b9343ec9c 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -904,7 +904,7 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask) goto invalid; } /* We don't support VTLB entry smaller than target page */ - if ((maskbits + 12) < TARGET_PAGE_BITS) { + if ((maskbits + TARGET_PAGE_BITS_MIN) < TARGET_PAGE_BITS) { goto invalid; } env->CP0_PageMask = mask << CP0PM_MASK; @@ -913,7 +913,8 @@ void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask) invalid: /* When invalid, set to default target page size. */ - env->CP0_PageMask = (~TARGET_PAGE_MASK >> 12) << CP0PM_MASK; + mask = (~TARGET_PAGE_MASK >> TARGET_PAGE_BITS_MIN); + env->CP0_PageMask = mask << CP0PM_MASK; } void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) diff --git a/target/mips/helper.c b/target/mips/helper.c index 063b65c0528..041432489d6 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -858,8 +858,8 @@ refill: break; } } - pw_pagemask = m >> 12; - update_pagemask(env, pw_pagemask << 13, &pw_pagemask); + pw_pagemask = m >> TARGET_PAGE_BITS_MIN; + update_pagemask(env, pw_pagemask << CP0PM_MASK, &pw_pagemask); pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF); { target_ulong tmp_entryhi = env->CP0_EntryHi; From patchwork Sun Dec 13 20:19:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EE0FC433FE for ; Sun, 13 Dec 2020 20:21:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6688D2396F for ; Sun, 13 Dec 2020 20:21:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403928AbgLMUVL (ORCPT ); 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id x7sm19488199wmi.11.2020.12.13.12.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:18 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson , Huacai Chen Subject: [PULL 06/26] target/mips: Do not include CP0 helpers in user-mode emulation Date: Sun, 13 Dec 2020 21:19:26 +0100 Message-Id: <20201213201946.236123-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org CP0 helpers are restricted to system-mode emulation. Do not intent do build cp0_helper.c in user-mode (this allows to simplify some #ifdef'ry). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Huacai Chen Message-Id: <20201109090422.2445166-3-f4bug@amsat.org> --- target/mips/cp0_helper.c | 4 ---- target/mips/meson.build | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index e8b9343ec9c..caaaefcc8ad 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -32,7 +32,6 @@ #include "sysemu/kvm.h" -#ifndef CONFIG_USER_ONLY /* SMP helpers. */ static bool mips_vpe_is_wfi(MIPSCPU *c) { @@ -1667,10 +1666,8 @@ target_ulong helper_evpe(CPUMIPSState *env) } return prev; } -#endif /* !CONFIG_USER_ONLY */ /* R6 Multi-threading */ -#ifndef CONFIG_USER_ONLY target_ulong helper_dvp(CPUMIPSState *env) { CPUState *other_cs = first_cpu; @@ -1709,4 +1706,3 @@ target_ulong helper_evp(CPUMIPSState *env) } return prev; } -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/meson.build b/target/mips/meson.build index fa1f024e782..681a5524c0e 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,6 +1,5 @@ mips_ss = ss.source_set() mips_ss.add(files( - 'cp0_helper.c', 'cpu.c', 'dsp_helper.c', 'fpu_helper.c', @@ -15,6 +14,7 @@ mips_softmmu_ss = ss.source_set() mips_softmmu_ss.add(files( + 'cp0_helper.c', 'cp0_timer.c', 'machine.c', 'mips-semi.c', From patchwork Sun Dec 13 20:19:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0FBFC0018C for ; Sun, 13 Dec 2020 20:21:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9AB9C2396F for ; Sun, 13 Dec 2020 20:21:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403976AbgLMUVQ (ORCPT ); Sun, 13 Dec 2020 15:21:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390355AbgLMUVQ (ORCPT ); Sun, 13 Dec 2020 15:21:16 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24099C0617A7 for ; Sun, 13 Dec 2020 12:20:25 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id d26so1169762wrb.12 for ; Sun, 13 Dec 2020 12:20:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ElGn7JwtMTMMU13LrhvDMbTZ+gVsyAEKbzwxbxdSXTQ=; b=r279oMzyuCA06s9efRNLeeAbvEmXQa8MM5wCrkN4z80SdfG4YW8i5qEoPXL3o3oJzi RmVwgMhKBr4cnlxAyCF1GV3mj4WeRSBTBlqhLnx+iO+4rrza/osaiircUIlMbzxNd3iK Cbwao2wMXofejyOGUVwrDa3Mf/5sK/dAsxP39CKyeGmdw4+1UtmB9pQuHKPBPFn9bSht 7zAg5Kaca5zsZLeJuvFC37lgO14GuwKCNbMWbpRowN04gx/ili7iU2l2H8mkWf8bmfS0 tq3lVJknSoW4EbcjJAJPadvtUseVOKUUdCQvD5ciCtG5101ztnGpoCG/dKyAxgwTlvjB lG/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ElGn7JwtMTMMU13LrhvDMbTZ+gVsyAEKbzwxbxdSXTQ=; b=SD+6DPZ+r+qpgdHHlfN5bJU1j9VEDsQaLBq+D4FwhL+RSLSiP3jCvRgZaHD0SkuOlq +a++/0FMYIg0rv8C1BDomsUBlm+mELMQnr7lRJaMSMvoUVTPLWg+lELAHnxmRGqkWfOq v5vKHZuO2YSaOC++kN5Du9OoXqK2jxizH8KtIu4vQFWx6XoZ5gNb/3H3SmumoW827G/m hlr6+BW3JH5wr2SGryRyN6uPeXcM6EfaTDSJPqA0m5ptkv7JmhZ4VExHtg1lByhpbPla XFYWUbIVDJr0NcMLV4LCu/+gUkXES5GLeQ8kBkiaNapWgkh1kC+Oy7RjlVvtNrEnbW1Z aP5g== X-Gm-Message-State: AOAM533cj59AMenyNdn14gYGdTGtvXK4dSzuGKkIRnVGWR6Nanfo+tky hIfXY56lvugrHoxwazP+6OY= X-Google-Smtp-Source: ABdhPJyXLdF/7P0sm1YXBUTdja+xRF+QyOyW3QdtUpku/c3SnS6EaVS1ygEllhtb7X2nkTZzGO+ydg== X-Received: by 2002:a5d:4349:: with SMTP id u9mr24715442wrr.319.1607890823912; Sun, 13 Dec 2020 12:20:23 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id q17sm27617700wrr.53.2020.12.13.12.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:23 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 07/26] target/mips: Remove unused headers from cp0_helper.c Date: Sun, 13 Dec 2020 21:19:27 +0100 Message-Id: <20201213201946.236123-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Remove unused headers and add missing "qemu/log.h" since qemu_log() is called. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-5-f4bug@amsat.org> --- target/mips/cp0_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index caaaefcc8ad..cb899fe3d73 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -21,15 +21,13 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" #include "internal.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" -#include "exec/memop.h" -#include "sysemu/kvm.h" /* SMP helpers. */ From patchwork Sun Dec 13 20:19:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBE2CC4167B for ; Sun, 13 Dec 2020 20:21:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B47CA239D3 for ; Sun, 13 Dec 2020 20:21:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392457AbgLMUVQ (ORCPT ); Sun, 13 Dec 2020 15:21:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390539AbgLMUVQ (ORCPT ); Sun, 13 Dec 2020 15:21:16 -0500 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93D1AC0617B0 for ; Sun, 13 Dec 2020 12:20:30 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id g185so13431486wmf.3 for ; Sun, 13 Dec 2020 12:20:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WU7av211Gw3wbADY6XPgoCLNL0Q/6KDqRZlDd72LlCc=; b=lg3Plv9yDZIf0oqfQcqIFKuS+fY1twqqoLWJGkP/0s5QmgX9g+AcAhlXe1vIXb4SkU u6+sEEol4i03yQAqE9FQXbu+uJeG4jQ718E7L+3h4cgjvP6xQ1yzqV14WzhsvaDrVG0P XTMhtyIG1mGkUbiZ7EkPa89KKSkfSi4+ZKW1Capz0GuBJr3TBqqMgLU9DJ5WgV3BQGZ+ CdCT70G6GNCe49e0Qzn/arC9q/YMgpkeOdC5fZdvpcze8suLyybPK+ZM84FYfw742Tk0 SrhkkMAjcR233PY95gVChi8+8HwmS3hTg9g4QhMLzpOsJw2UyGpoLsFgG/Ul6Ol8kqE4 8OqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=WU7av211Gw3wbADY6XPgoCLNL0Q/6KDqRZlDd72LlCc=; b=tNN4fLBhtdOWNzbFqI6nNKVYSxzgNDbLMl62o6yGKwqh4izOtehopzqzQRFnwZcyd5 MEt9eTBs5QQL1DjeEKNzGf2c2cJjNo3ioO89sBJfvWtYKDOu8d75Nh39BXBm+aa2mNpc B8pxIIr0QnRO+4xkl0noi53qa3HFBqSOaVQ3E3bOJPVs2Px+6DaIbofeDsLE6O6wjPhQ 8OtigYVveuY4CdUc6cNWQ7qDHDv5aqf3WTgWQTH62q2sSW5OTVKlkKRi4nwnHH0kWQLm kWGoAvaD+Qabn9MYoGGMXxeMF6UM0uRYTJd7Ck9/Oc4KCsuUxqzVMiZCz2Vy4Njes6UN A2kQ== X-Gm-Message-State: AOAM531kLUoCJVAJRcat8aeaaaf3lGKIgLD/nZEXU5EzJtBrQodKlikG dTbXv9ewUM9FhcESzR26cj0= X-Google-Smtp-Source: ABdhPJwGswfU1INeuc5+Xpdh/7IEhKrZYuniVVNcdgaPCtjzp2Ttm7znjOhHTptaP+0DrvPGZdnyxQ== X-Received: by 2002:a1c:2182:: with SMTP id h124mr24378018wmh.25.1607890828851; Sun, 13 Dec 2020 12:20:28 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id 64sm28192537wmd.12.2020.12.13.12.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:28 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 08/26] target/mips: Also display exception names in user-mode Date: Sun, 13 Dec 2020 21:19:28 +0100 Message-Id: <20201213201946.236123-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Currently MIPS exceptions are displayed as string in system-mode emulation, but as number in user-mode. Unify by extracting the current system-mode code as excp_name() and use that in user-mode. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201119160536.1980329-1-f4bug@amsat.org> --- target/mips/helper.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 041432489d6..59de58fcbc9 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -978,6 +978,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, return physical; } } +#endif /* !CONFIG_USER_ONLY */ static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_RESET] = "reset", @@ -1018,7 +1019,14 @@ static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_MSADIS] = "MSA disabled", [EXCP_MSAFPE] = "MSA floating point", }; -#endif + +static const char *mips_exception_name(int32_t exception) +{ + if (exception < 0 || exception > EXCP_LAST) { + return "unknown"; + } + return excp_names[exception]; +} target_ulong exception_resume_pc(CPUMIPSState *env) { @@ -1091,19 +1099,13 @@ void mips_cpu_do_interrupt(CPUState *cs) bool update_badinstr = 0; target_ulong offset; int cause = -1; - const char *name; if (qemu_loglevel_mask(CPU_LOG_INT) && cs->exception_index != EXCP_EXT_INTERRUPT) { - if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) { - name = "unknown"; - } else { - name = excp_names[cs->exception_index]; - } - qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", - __func__, env->active_tc.PC, env->CP0_EPC, name); + __func__, env->active_tc.PC, env->CP0_EPC, + mips_exception_name(cs->exception_index)); } if (cs->exception_index == EXCP_EXT_INTERRUPT && (env->hflags & MIPS_HFLAG_DM)) { @@ -1490,8 +1492,9 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, { CPUState *cs = env_cpu(env); - qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", - __func__, exception, error_code); + qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", + __func__, exception, mips_exception_name(exception), + error_code); cs->exception_index = exception; env->error_code = error_code; From patchwork Sun Dec 13 20:19:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13D2FC1B0D9 for ; Sun, 13 Dec 2020 20:21:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EAB40239A4 for ; Sun, 13 Dec 2020 20:21:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393046AbgLMUVV (ORCPT ); Sun, 13 Dec 2020 15:21:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390355AbgLMUVV (ORCPT ); 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id w3sm27387242wma.3.2020.12.13.12.20.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:33 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson , Huacai Chen Subject: [PULL 09/26] target/mips: Allow executing MSA instructions on Loongson-3A4000 Date: Sun, 13 Dec 2020 21:19:29 +0100 Message-Id: <20201213201946.236123-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE: https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html Commit af868995e1b correctly set the 'MSA present' bit of Config3 register, but forgot to allow the MSA instructions decoding in insn_flags, so executing them triggers a 'Reserved Instruction'. Fix by adding the ASE_MSA mask to insn_flags. Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Huacai Chen Message-Id: <20201130102228.2395100-1-f4bug@amsat.org> --- target/mips/translate_init.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index ea85d5c6a79..79f75ed863c 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -832,7 +832,7 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - .name = "Loongson-3A4000", + .name = "Loongson-3A4000", /* GS464V-based */ .CP0_PRid = 0x14C000, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | @@ -885,7 +885,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 48, .PABITS = 48, - .insn_flags = CPU_LOONGSON3A, + .insn_flags = CPU_LOONGSON3A | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, { From patchwork Sun Dec 13 20:19:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03FFBC2BB48 for ; Sun, 13 Dec 2020 20:21:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D49FF2396F for ; Sun, 13 Dec 2020 20:21:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393086AbgLMUVV (ORCPT ); Sun, 13 Dec 2020 15:21:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392882AbgLMUVV (ORCPT ); Sun, 13 Dec 2020 15:21:21 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9B5DC0613D3 for ; Sun, 13 Dec 2020 12:20:39 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id x22so11943543wmc.5 for ; Sun, 13 Dec 2020 12:20:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UKVyHTJcfnmphpZOlFQ3sK0TO5i59SQTbNG7ZpwIL2s=; b=Q2ksS/NIJwRo6OVacRh1D3+KqjRnj3fQkjk+RFruSjRTqsxfiGyG+2kd+xqRaPSyNn Og8GyaYIUtXhBQX+ZW1nfYS1ilo/N/MXh94szzfdIv4dta73ui2OpQFnEmnU3t/r+teV Tka2QbqFNDF+03VruDSDXm2EDY0TDxtdzQcGizbC803leH6tL1MOB8fNUmFcmB7n+bV4 N8yARhMJkKFDmnjPEv7kVWv0GVMvQAhDMqIa45YAM3Bwo7t5En2DVylczCrwAzDEA5Xl sIg9lVvazuHl6l7sJEEFsd8GbAJt4sB2QIEPGG9ZKAcN5ikpBAIkwDEfNdY7XCyoOr7v +I3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UKVyHTJcfnmphpZOlFQ3sK0TO5i59SQTbNG7ZpwIL2s=; b=okxy7xnTGMlSIH+V/hL2qAL4wOw4+Ig8M8dQY7b+0ndsroXzhBCx98G83xNnzYsiDX wr7xsXyWrCMgt+xpmE4RZ5bmpTVXuvSmLjxiy7vfavjzFpyvfhNi6K1QSXcTpEwjgMNO hS8TteCAa7+oBBA12hEweWAR9MgHli/aCKHskgojCFEcb5GWlakHHpLHNiPzVv6hu6h8 /KLi2z6O9k+0RH0aE26BTP5rZa1np8fFNnnKZTUA4Id/tjP4pOylgW8/7uhwyS/1iRwL NMkap3O6kVFfXG0JLeYDaboneJLKBJhX/AtNP32bufyv/R624zGK/XNT7pyXYzzpmfvq dpxg== X-Gm-Message-State: AOAM530fxQxFEW7AWSu4p7vLykUCeovtPb88P2abShixhVbxH0+ipkJX bXY98TQh6zY1C6XTPTq9Ko8= X-Google-Smtp-Source: ABdhPJzgoE2qp8c/gtBc5k0f18CqNg5PxnMO3ehBmX6yeySByMtolXCKZoaCC8qZNyu+dyEmkIbmeA== X-Received: by 2002:a7b:c773:: with SMTP id x19mr23833930wmk.127.1607890838712; Sun, 13 Dec 2020 12:20:38 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id r20sm28985853wrg.66.2020.12.13.12.20.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:38 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 10/26] target/mips: Explicit Release 6 MMU types Date: Sun, 13 Dec 2020 21:19:30 +0100 Message-Id: <20201213201946.236123-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org As of Release 6, MMU type 4 is assigned to "Dual Variable-Page-Size and Fixed-Page-Size TLBs" and type 2 to "Block Address Translation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201201132817.2863301-4-f4bug@amsat.org> --- target/mips/internal.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 76b7a85cbb3..bcd3d857ab6 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -16,10 +16,11 @@ * CP0C0_MT field. */ enum mips_mmu_types { - MMU_TYPE_NONE, - MMU_TYPE_R4000, - MMU_TYPE_RESERVED, - MMU_TYPE_FMT, + MMU_TYPE_NONE = 0, + MMU_TYPE_R4000 = 1, /* Standard TLB */ + MMU_TYPE_BAT = 2, /* Block Address Translation */ + MMU_TYPE_FMT = 3, /* Fixed Mapping */ + MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */ MMU_TYPE_R3000, MMU_TYPE_R6000, MMU_TYPE_R8000 From patchwork Sun Dec 13 20:19:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D46AC2BBCA for ; Sun, 13 Dec 2020 20:21:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E5A62396F for ; Sun, 13 Dec 2020 20:21:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393417AbgLMUV0 (ORCPT ); Sun, 13 Dec 2020 15:21:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2393142AbgLMUVZ (ORCPT ); Sun, 13 Dec 2020 15:21:25 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B135C0613D6 for ; Sun, 13 Dec 2020 12:20:45 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id c5so10754989wrp.6 for ; Sun, 13 Dec 2020 12:20:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cgaHXNW/5WgtwEvWMUgAxy7itdnx69iC1c/ZHbcmFvM=; b=uQYrE+2Qhcmp3WlwFdf+D5+FYcDpG6cFeMPXtrY0OjHRN54VDeyV4PYKH/fjkNOH9Q wVzi+zTFbAwfMhEeLrysDanA7Mn6Mn2C4DDp1HvOyjpdDoU4ASjaqqP9Qs24Lel8Cbxv mmNDIGN4fufjv6MdWjm7hfFh6ERPFyXQyvz90Cgu/eOfrsQt9OaWmrME9kyFMTOByKQS uTO11JZ01gOSC4kbMTGupYqPGQAbUyfxx+LV1WebPC+cKjZXaaxCKRIsmB1BhjpZWiy0 Wa8m/TJZIggopdrFRJw4oPlIfG3PA3fYFMNZQPEV9CjXXisBjwZFNqI2F3YR4NDw6izZ 6mGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cgaHXNW/5WgtwEvWMUgAxy7itdnx69iC1c/ZHbcmFvM=; b=czmu0dU7WtG26wgZhuh2TkG+2kE+gN3y4Dg+ko4XxEArBUGkOPpmwBwqhOz7Wqwqjl va6Jq1DOb7Pv4m/eWy/9g8QqBrVD0WJ3t0zd/HVaVb7hJCsWlYQ0EbgKITTOPSN6KpMA /6+hj21FD3yVP+QB17TJSQiJgBZxCcVHGGKAX/yte1WDaXyi8p5qhjtNlrzXPPQPkvly fBmTN1pZ2E0bRLCy03RttFfHutIgH15/oWH5ufUUx7jbjVdpefTjH9huPiDKfPlEh7pM SL9guubeBxbAT1ryyNrZT1fSYs0m6sraDD1Fv2w484h0gE5H7Y0OQOZWTC9FNQbunO0l fSNg== X-Gm-Message-State: AOAM5310JzwutlQHBmi5zGOnaHR9foQCXZoEYAU7/KE9Wu7atn7aCCx3 a0ITJhkvHY4tKNwyyPOYqkU= X-Google-Smtp-Source: ABdhPJxi1HLf3FD13UfxWm0lJHdi9m9BmBMJoArKmNJDfLLV01NRhcTmbVSlznxIufmZF2k7WGlVfg== X-Received: by 2002:a5d:56c3:: with SMTP id m3mr8510854wrw.419.1607890843830; Sun, 13 Dec 2020 12:20:43 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id h13sm28768884wrm.28.2020.12.13.12.20.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:43 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 11/26] target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT() Date: Sun, 13 Dec 2020 21:19:31 +0100 Message-Id: <20201213201946.236123-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org As cpu_supports_isa() / cpu_supports_cps_smp() take a 'cpu_type' name argument, rename them cpu_type_supports_FEAT(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207215257.4004222-2-f4bug@amsat.org> --- target/mips/cpu.h | 4 ++-- hw/mips/boston.c | 4 ++-- hw/mips/malta.c | 4 ++-- target/mips/translate.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 23f8c6f96cd..9c65c87bf99 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1286,8 +1286,8 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU -bool cpu_supports_cps_smp(const char *cpu_type); -bool cpu_supports_isa(const char *cpu_type, uint64_t isa); +bool cpu_type_supports_cps_smp(const char *cpu_type); +bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); /* mips_int.c */ diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 3d40867dc4c..16467ea4752 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -459,12 +459,12 @@ static void boston_mach_init(MachineState *machine) s = BOSTON(dev); s->mach = machine; - if (!cpu_supports_cps_smp(machine->cpu_type)) { + if (!cpu_type_supports_cps_smp(machine->cpu_type)) { error_report("Boston requires CPUs which support CPS"); exit(1); } - is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); + is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64); object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 5c11eecec11..4651a1055c9 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1205,7 +1205,7 @@ static void create_cps(MachineState *ms, MaltaState *s, static void mips_create_cpu(MachineState *ms, MaltaState *s, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { - if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { + if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) { create_cps(ms, s, cbus_irq, i8259_irq); } else { create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); @@ -1309,7 +1309,7 @@ void mips_malta_init(MachineState *machine) loaderparams.initrd_filename = initrd_filename; kernel_entry = load_kernel(); - if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { + if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) { write_bootloader(memory_region_get_ram_ptr(bios), bootloader_run_addr, kernel_entry); } else { diff --git a/target/mips/translate.c b/target/mips/translate.c index c64a1bc42e1..b8ed16bb779 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31770,13 +31770,13 @@ void cpu_mips_realize_env(CPUMIPSState *env) mvp_init(env, env->cpu_model); } -bool cpu_supports_cps_smp(const char *cpu_type) +bool cpu_type_supports_cps_smp(const char *cpu_type) { const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } -bool cpu_supports_isa(const char *cpu_type, uint64_t isa) +bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) { const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); return (mcc->cpu_def->insn_flags & isa) != 0; From patchwork Sun Dec 13 20:19:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9655C4361B for ; Sun, 13 Dec 2020 20:21:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AC21F2396F for ; Sun, 13 Dec 2020 20:21:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404842AbgLMUVa (ORCPT ); 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id j15sm28136891wrr.85.2020.12.13.12.20.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:48 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 12/26] target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument Date: Sun, 13 Dec 2020 21:19:32 +0100 Message-Id: <20201213201946.236123-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce cpu_supports_isa() which takes a CPUMIPSState argument, more useful at runtime when the CPU is created (no need to call the extensive object_class_by_name()). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207215257.4004222-3-f4bug@amsat.org> --- target/mips/cpu.h | 1 + target/mips/cpu.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9c65c87bf99..e8bca75f237 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1287,6 +1287,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU bool cpu_type_supports_cps_smp(const char *cpu_type); +bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 76d50b00b42..687e2680dd1 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -310,3 +310,8 @@ MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) return MIPS_CPU(cpu); } + +bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) +{ + return (env->cpu_model->insn_flags & isa_mask) != 0; +} From patchwork Sun Dec 13 20:19:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A76E0C4361B for ; Sun, 13 Dec 2020 20:21:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 810162396F for ; Sun, 13 Dec 2020 20:21:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404978AbgLMUVf (ORCPT ); Sun, 13 Dec 2020 15:21:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404142AbgLMUVf (ORCPT ); Sun, 13 Dec 2020 15:21:35 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06DE7C061794 for ; Sun, 13 Dec 2020 12:20:55 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id a3so13416986wmb.5 for ; Sun, 13 Dec 2020 12:20:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uJl+/EeXqBxB7hfG+/ZfbRL30Nmwpy+BSYnXX9dfemM=; b=u0ko4PweyxhLkeeWo3yjo1wYFhxgNEC5xrZTR5djqgHZbI8mv4MheQT0hAFOCezq1y +t+3hg7NcxRhx5zGvUWyOQD/p4xngcgSYKQMqZfOpdvwVne724d8k7enBYPR8EEBO+Ox WQJBbfGqH/t/swYfHhLzKf58Gnqqduou53TdAER3Rs4MeTNB483JcdU4MHLKZRSr7Mz9 05sglCyISn7H2VfrielSp9BMFJIzKeB03RoLFBZEbTEZ/pdDM11S49XzFQe9uadwbl88 nZkR0X5hG4lVOf0s6Up0ZgAaMPZ7phLTFTweLuF9xF706SfIDnJYl1HfY6PkSueSwrCx 7JAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=uJl+/EeXqBxB7hfG+/ZfbRL30Nmwpy+BSYnXX9dfemM=; b=ka83iiaWV6oX0IVjeY5nvY8u21u2NOB0KcX6WUQC8AUM7YF3anFibrMEz+TS+Zr01T YZaovhN96rR2zWx2K6+KAo41mG8VyP4tBfmoONRNqmc482Q0DyoqSl0A0orspolque1d iimLZfiosIymGMwMnaMICEGrpPCtn02wAs6QBi90SD7sDE/d8lxQdNDSQJltneJkijti WEkOaGpwO2akfc2rjG+2DSV8qpiio22GgzGy0NKLBmV4BTN0y5eceWlz5WEPwl4x2ezx yOBZRezvnn61wsZXxgMygzUordmSD+pSFit7QZXHZJqxH0qKLcZDJk+l10BSrBv14J+q gLLg== X-Gm-Message-State: AOAM532oaV8B1q5WyvH/YXnXZhMKc3lU5cL5AscWupZWZsfwJIgY8yqv PWpw38G0yFJtuEKX5TUEIuc= X-Google-Smtp-Source: ABdhPJwyr3Bcz0npqHp1+rzM78Aj/bFoHAUN+iHfi/EMO7r5KVcn6S69kfPOW50IF7acg/ABH6c7cA== X-Received: by 2002:a1c:b78a:: with SMTP id h132mr24042122wmf.141.1607890853818; Sun, 13 Dec 2020 12:20:53 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id s1sm31441773wrv.97.2020.12.13.12.20.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:53 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 13/26] hw/mips: Move address translation helpers to target/mips/ Date: Sun, 13 Dec 2020 21:19:33 +0100 Message-Id: <20201213201946.236123-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Address translation is an architectural thing (not hardware related). Move the helpers from hw/ to target/. As physical address and KVM are specific to system mode emulation, restrict this file to softmmu, so it doesn't get compiled for user-mode emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-2-f4bug@amsat.org> --- include/hw/mips/cpudevs.h | 7 ------- target/mips/cpu.h | 8 ++++++++ hw/mips/boston.c | 1 - {hw => target}/mips/addr.c | 2 +- target/mips/translate.c | 2 -- hw/mips/meson.build | 2 +- target/mips/meson.build | 1 + 7 files changed, 11 insertions(+), 12 deletions(-) rename {hw => target}/mips/addr.c (98%) diff --git a/include/hw/mips/cpudevs.h b/include/hw/mips/cpudevs.h index 291f59281a0..f7c9728fa9f 100644 --- a/include/hw/mips/cpudevs.h +++ b/include/hw/mips/cpudevs.h @@ -5,13 +5,6 @@ /* Definitions for MIPS CPU internal devices. */ -/* addr.c */ -uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); -uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); -uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); -bool mips_um_ksegs_enabled(void); -void mips_um_ksegs_enable(void); - /* mips_int.c */ void cpu_mips_irq_init_cpu(MIPSCPU *cpu); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e8bca75f237..5d3b2a01c01 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1291,6 +1291,14 @@ bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); +/* addr.c */ +uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); +uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); + +uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); +bool mips_um_ksegs_enabled(void); +void mips_um_ksegs_enable(void); + /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 16467ea4752..c3b94c68e1b 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -28,7 +28,6 @@ #include "hw/loader.h" #include "hw/loader-fit.h" #include "hw/mips/cps.h" -#include "hw/mips/cpudevs.h" #include "hw/pci-host/xilinx-pcie.h" #include "hw/qdev-clock.h" #include "hw/qdev-properties.h" diff --git a/hw/mips/addr.c b/target/mips/addr.c similarity index 98% rename from hw/mips/addr.c rename to target/mips/addr.c index 2f138fe1ea8..27a6036c451 100644 --- a/hw/mips/addr.c +++ b/target/mips/addr.c @@ -21,7 +21,7 @@ */ #include "qemu/osdep.h" -#include "hw/mips/cpudevs.h" +#include "cpu.h" static int mips_um_ksegs; diff --git a/target/mips/translate.c b/target/mips/translate.c index b8ed16bb779..4a1ae73f9d0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28,8 +28,6 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" -#include "hw/mips/cpudevs.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "hw/semihosting/semihost.h" diff --git a/hw/mips/meson.build b/hw/mips/meson.build index bcdf96be69f..77b4d8f365e 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,5 +1,5 @@ mips_ss = ss.source_set() -mips_ss.add(files('addr.c', 'mips_int.c')) +mips_ss.add(files('mips_int.c')) mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c')) diff --git a/target/mips/meson.build b/target/mips/meson.build index 681a5524c0e..4179395a8ea 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -14,6 +14,7 @@ mips_softmmu_ss = ss.source_set() mips_softmmu_ss.add(files( + 'addr.c', 'cp0_helper.c', 'cp0_timer.c', 'machine.c', From patchwork Sun Dec 13 20:19:34 2020 Content-Type: text/plain; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id u3sm30014199wre.54.2020.12.13.12.20.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:20:58 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 14/26] target/mips: Remove unused headers from translate.c Date: Sun, 13 Dec 2020 21:19:34 +0100 Message-Id: <20201213201946.236123-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-3-f4bug@amsat.org> --- target/mips/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4a1ae73f9d0..e87f472a8d1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24,8 +24,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "disas/disas.h" -#include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" From patchwork Sun Dec 13 20:19:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EF25C2BB9A for ; Sun, 13 Dec 2020 20:21:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2278B23998 for ; Sun, 13 Dec 2020 20:21:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404092AbgLMUV0 (ORCPT ); Sun, 13 Dec 2020 15:21:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2393142AbgLMUV0 (ORCPT ); Sun, 13 Dec 2020 15:21:26 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA2EDC061285 for ; Sun, 13 Dec 2020 12:21:04 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id w206so7881384wma.0 for ; Sun, 13 Dec 2020 12:21:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U1U85wbWiHYedQBnfCehC7vZG2diuqNh/zEf3sAbatk=; b=mbQ3Z2kBPsaAeNkAQKlf/Uqc+U93xRoHgnDONlAQ92t4i03Hzh6EQALZI3Y2KEc3U+ o1H1TjPOani/Sz3yMY3hKY0n4Iz4FeNkEvoziMZBhVWPvaAKITTeu44/mfWZKwfWa0I4 /T/ovt9++wGDAVVgNaxc87M6DLv7/29iSOO5+y5mmpzQKXzDAstTpYhBBdpnhsqyy+JI xRRTW0sZVAuSoU6T7YTvOgQbY3LDniMGS6RyWJroOc9o4kEmKD0NqLGZr4oPM7YSPIMn IPXHhDCwvsP6b4T/7/VJQrFU++XjnyBZwrmpSRQizF+pFmOmSQAF3ZXYlKC0BEfn25V7 qyeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=U1U85wbWiHYedQBnfCehC7vZG2diuqNh/zEf3sAbatk=; b=jS7viDQ0XTjmSIqBP/LA1LVmEDqjnA2e3g/tOj6By3p3jANWFETZj+FgMw0hufBkJJ WDb7XI+z/tFrSRttFpLsWr8qP4g1J85NqybgwfzjV3k8TrwsrmfwemUlom0b447AtPcf XDOA3xYdOnd4Jljb8N295tckWc/Oes13Q00cZoDExAvzwLamok6AMZN21FuhZw06XDgi lZ1yrkWonKm7ScgtBIvfR1JK3DmC6RHEPym/Ga5Kx7bvr47gxNfEFmW++1nGFPsiFc60 r19zcVCP+jZm9Jw1DETDrL2lzzQoZdoGGiAzuqNMT0fMHm7MLUzOWABJax6TBqR2t6wS C6yw== X-Gm-Message-State: AOAM531TWnzYNSdofLOAAnAcoN9EE4cobPI46taAoIYDSQmd72sG64YQ lGjv28If1lI14M2VD1C4III= X-Google-Smtp-Source: ABdhPJzNHgtxhEQNX7DznNzRimsoGP5ISuhO0bLMbYb6QifZ7mqmtSXaufbgDyGau189eqa0XDfA4Q== X-Received: by 2002:a1c:43c5:: with SMTP id q188mr24563275wma.163.1607890863692; Sun, 13 Dec 2020 12:21:03 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id h5sm30144342wrp.56.2020.12.13.12.21.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:03 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 15/26] target/mips: Remove unused headers from op_helper.c Date: Sun, 13 Dec 2020 21:19:35 +0100 Message-Id: <20201213201946.236123-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-6-f4bug@amsat.org> --- target/mips/op_helper.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 5184a1838be..5aa97902e98 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -19,15 +19,11 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "internal.h" -#include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "exec/memop.h" -#include "sysemu/kvm.h" /*****************************************************************************/ From patchwork Sun Dec 13 20:19:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20D9DC4361B for ; Sun, 13 Dec 2020 20:21:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E4DA42396F for ; Sun, 13 Dec 2020 20:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405251AbgLMUVw (ORCPT ); Sun, 13 Dec 2020 15:21:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405038AbgLMUVv (ORCPT ); Sun, 13 Dec 2020 15:21:51 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5A63C061248 for ; Sun, 13 Dec 2020 12:21:09 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id q75so13417277wme.2 for ; Sun, 13 Dec 2020 12:21:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H63X5j82a+LliFWq3Jbhu57DqrlxgL6DTtMOErZtbQQ=; b=lPbs7U1Oj6rFYBbgUiPOqTZ6521oG6m+tJxriuzaHqVF5erscvscVQ3dhMqHQsbHNQ 5r9lEXG2Gscm2RVAf9pZE28wmVUPfVz1xp/azb5nsQ+p8xRdcz+/rFA5qDhVfAa3RqV4 moCXUB4u6iiAHyqx3vEkswuoqCZJ8b4afHlsipDajERjcJBYzGwLIQ9hINcsUjMtS9Oy xp7SflzOtoo6X2jQA+ewdqeXJvIXeZnC8PtpfnS+k6j6Cnd8mXs03HgnrF2P4Nx9nALF D/D8YdWZxqKzUbigIhvS9SQBnkXcnFZ/0Xr5dUbBbgMSxPsXAcwf2RFJvxZ3CJKe8XSI AeZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=H63X5j82a+LliFWq3Jbhu57DqrlxgL6DTtMOErZtbQQ=; b=PtZcPUFRIpRZMMw9uQmY4t+ge/fx4HXHAxST0SWibJQ25UCGxd6laSPMAGjslQ785S HXlYIBchDI7FS8DKvJ+YUg5/AgwXQksLCzY94cXeVda+bQ6rt1ftk45+tkO7VY3XLacS QT82apXEGM+isUx6eGrTHxjW9UcmiicSeeLHpN7NotBlGyeRBc1lj8LLjD7vK7IqRu/U 0PYVLTmBpZDCb5RT6zZuVqtgCsoCcTAy7O8rR1Uh5/mn9UmJ7fe26H41hUi17NUjyjmj UgiZ167lrTWJ9cZA3GMbQ8ppr4cJ7Cl7r+HBebeoKVrnAHYo2UPlOTzcjk6b/5CoWV7L Vrjg== X-Gm-Message-State: AOAM5321aipXz7u5M92e1/O6v/kv5BW8YtIhfnThjIEI2+pd5YtXLZXo QOqkePAoVacv5/4YfgTgXwk= X-Google-Smtp-Source: ABdhPJz3/rQrsUemKBe0Gm+tyYr3IRJvrRwSyn2Alp0P+Zr8a+YhxOpvSZRX/WsAXlj7ubTDzVcY9g== X-Received: by 2002:a1c:6383:: with SMTP id x125mr24420960wmb.46.1607890868670; Sun, 13 Dec 2020 12:21:08 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id q73sm28249910wme.44.2020.12.13.12.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:08 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 16/26] target/mips: Remove mips_def_t unused argument from mvp_init() Date: Sun, 13 Dec 2020 21:19:36 +0100 Message-Id: <20201213201946.236123-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org mvp_init() doesn't require any CPU definition (beside the information accessible via CPUMIPSState). Remove the unused argument. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201204222622.2743175-2-f4bug@amsat.org> --- target/mips/translate.c | 2 +- target/mips/translate_init.c.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e87f472a8d1..f218997f049 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31763,7 +31763,7 @@ void cpu_mips_realize_env(CPUMIPSState *env) mmu_init(env, env->cpu_model); #endif fpu_init(env, env->cpu_model); - mvp_init(env, env->cpu_model); + mvp_init(env); } bool cpu_type_supports_cps_smp(const char *cpu_type) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index 79f75ed863c..5a926bc6df3 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -989,7 +989,7 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def) memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); } -static void mvp_init (CPUMIPSState *env, const mips_def_t *def) +static void mvp_init(CPUMIPSState *env) { env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); From patchwork Sun Dec 13 20:19:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 826EEC433FE for ; Sun, 13 Dec 2020 20:21:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 586D32396F for ; Sun, 13 Dec 2020 20:21:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405302AbgLMUV4 (ORCPT ); Sun, 13 Dec 2020 15:21:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404225AbgLMUV4 (ORCPT ); Sun, 13 Dec 2020 15:21:56 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D41CAC06179C for ; Sun, 13 Dec 2020 12:21:14 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id v14so11954045wml.1 for ; Sun, 13 Dec 2020 12:21:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BwBCSJKUs74AgI90rgGgJ5DnyTy76Cwmh6AmTQxT6D8=; b=mrwpFWGC/8qrenEQFhf/VblmOHmQoA6rejjcRRVDeYwpRb49BQO8vN8IeucQNyvrtF f8YuxMsC/iKs1KnLM42AK032qwQW6l08i6+WiyZDZK6g6QWF4NM+9+VGOd3vLxmT/7Qi ccFby7l/TiVjCbtXYXFPy+2pgJoFqeSrI59iqIwfv3HsS6nVHPMaVXFf5lZVFu7AX39r jWGdRsJxAltvakb4Mt5uDaC8KH3wT0ikuaV+GraTYk0xm8X5YbCOlXXnM2oGq16xiT8y vnVMGbcFrCJe28hJIbBHmyESd2jtuTxLLL7rxUCjjEMqKleKO1LzwlpHA9T4SRG4Yxtb dHww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=BwBCSJKUs74AgI90rgGgJ5DnyTy76Cwmh6AmTQxT6D8=; b=me9fCVPayM4sUep1H6yF1saiNFnonXsJgxcinMHEgmd70StXy5pdRZ3aRG3FtYmD/q kjrD11TS1BB96hi4/rGr3AYKPWzT9ji8wolDAbduZ6LhW4cbSase3A8vUVz5QgBNZ1xD Gcp9VNqV7KL1C9OOyCJvwDfuKf/r6axNs3VUhOfPSWrvh8kybmoGlKAldJftKbbp0lpo Ml0F2SBZgkhG28/Y/BDYCbeh4Rhp2ut+G5u/UsO28Nrx6X5NM1hKiv6f86YHSeVB7X2W SDMmbNCgVxsvMSnqVZg4voJWRoUB6XL+vl6zP8pOBgVZaQDwYaaHhochfzeekD29uFiO Twmg== X-Gm-Message-State: AOAM533hGoFq45iFzNczA/H3jwS4yUj2TK3t31w+0KGRDxZAjI4reeyI NpSEEOr5YGHFPVCibHScPoQ= X-Google-Smtp-Source: ABdhPJyjCdeXDlFSxrZSqJn/AgC7v3c15fguzRGYdbHseBQtSeIjGz1sP0ZJiYfQIPcPfGi/6wFVDw== X-Received: by 2002:a1c:2288:: with SMTP id i130mr24700600wmi.78.1607890873572; Sun, 13 Dec 2020 12:21:13 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id h184sm28789455wmh.23.2020.12.13.12.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:12 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 17/26] target/mips: Introduce ase_mt_available() helper Date: Sun, 13 Dec 2020 21:19:37 +0100 Message-Id: <20201213201946.236123-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Instead of accessing CP0_Config3 directly and checking the 'Multi-Threading Present' bit, introduce an helper to simplify code review. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201204222622.2743175-3-f4bug@amsat.org> --- target/mips/cpu.h | 7 +++++++ hw/mips/cps.c | 3 +-- target/mips/cp0_helper.c | 2 +- target/mips/cpu.c | 2 +- target/mips/helper.c | 2 +- target/mips/translate.c | 2 +- 6 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5d3b2a01c01..3ac21d0e9c0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1289,6 +1289,13 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); + +/* Check presence of multi-threading ASE implementation */ +static inline bool ase_mt_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MT); +} + void cpu_set_exception_base(int vp_index, target_ulong address); /* addr.c */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 962b1b0b87c..7a0d289efaf 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -58,8 +58,7 @@ static void main_cpu_reset(void *opaque) static bool cpu_mips_itu_supported(CPUMIPSState *env) { - bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || - (env->CP0_Config3 & (1 << CP0C3_MT)); + bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env); return is_mt && !kvm_enabled(); } diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index cb899fe3d73..36a92857bfb 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -1164,7 +1164,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) old = env->CP0_EntryHi; val = (arg1 & mask) | (old & ~mask); env->CP0_EntryHi = val; - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { sync_c0_entryhi(env, env->current_tc); } /* If the ASID changes, flush qemu's TLB. */ diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 687e2680dd1..9d7edc1ca21 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -74,7 +74,7 @@ static bool mips_cpu_has_work(CPUState *cs) } /* MIPS-MT has the ability to halt the CPU. */ - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { /* * The QEMU model will issue an _WAKE request whenever the CPUs * should be woken up. diff --git a/target/mips/helper.c b/target/mips/helper.c index 59de58fcbc9..0c657865793 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -419,7 +419,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) tlb_flush(env_cpu(env)); } #endif - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { sync_c0_status(env, env, env->current_tc); } else { compute_hflags(env); diff --git a/target/mips/translate.c b/target/mips/translate.c index f218997f049..ccc82abce04 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31917,7 +31917,7 @@ void cpu_state_reset(CPUMIPSState *env) cpu_mips_store_count(env, 1); - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { int i; /* Only TC0 on VPE 0 starts as active. */ From patchwork Sun Dec 13 20:19:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 685BBC433FE for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id y7sm28088689wmb.37.2020.12.13.12.21.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:17 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 18/26] target/mips: Do not initialize MT registers if MT ASE absent Date: Sun, 13 Dec 2020 21:19:38 +0100 Message-Id: <20201213201946.236123-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Do not initialize MT-related config registers if the MT ASE is not present. As some functions access the 'mvp' structure, we still zero-allocate it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201204222622.2743175-4-f4bug@amsat.org> --- target/mips/translate_init.c.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index 5a926bc6df3..f72fee3b40a 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -993,6 +993,10 @@ static void mvp_init(CPUMIPSState *env) { env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); + if (!ase_mt_available(env)) { + return; + } + /* MVPConf1 implemented, TLB sharable, no gating storage support, programmable cache partitioning implemented, number of allocatable and shareable TLB entries, MVP has allocatable TCs, 2 VPEs From patchwork Sun Dec 13 20:19:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 000DCC0018C for ; Sun, 13 Dec 2020 20:23:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BC7062396F for ; Sun, 13 Dec 2020 20:23:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404142AbgLMUWS (ORCPT ); Sun, 13 Dec 2020 15:22:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731160AbgLMUWF (ORCPT ); Sun, 13 Dec 2020 15:22:05 -0500 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD934C0613CF for ; Sun, 13 Dec 2020 12:21:24 -0800 (PST) Received: by mail-wr1-x441.google.com with SMTP id d26so1171237wrb.12 for ; Sun, 13 Dec 2020 12:21:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=34Gjpun7TNPsoaQVN38Yv8sG5iP6wLHtCCAjvvFP5UI=; b=BU3fUzi8DAzwsnOmXIJ76k8U4DrKlFD4XgiVs2SUI68jQ+iKUDSlr9JBsXwLewlN8J MDR35+6wJWQKp8NZ9NCwBBFSRnMsqAnE4kblbrdxgeuWNBEgv/KEOS0YdV54clSlunOG pmTEXF9/gqvpn1SUxQw/jGe9BhmRL4Ta/pxCNPx0KXBSGzNjJlwbTDdqT/R+1ppD9VNL wkVNTJ8ynCM0zNSOgU0iy4PdzHWWKAuBZ/3AdppawIr0PPXO7UCVzzV8EwKG0NrYen3X SCTqipVjLZOjlA5KRD6wCyMiGZh4cUAUpU9+md9tmT8RKZJHvo9KXxw561Vqvhqj9hvy VlYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=34Gjpun7TNPsoaQVN38Yv8sG5iP6wLHtCCAjvvFP5UI=; b=BTWPsicxF/nZFh9ZgenAAu4ZplGge4bz96elU8Oi62EUmDI3bvJtfq/BD/7kPz3Bm6 Rnrzd/OPf+uDrQh3FBlELkO6gh4s2fX5nvZYpd3jy6nKf0wnkmtg6NNHga1rXpWJXJ+5 v8POaDhoH9WL9Fyl8BuzSOj+lTfwYbJlBAWQRSlryaOnpcPtmwOLGG4avK3lmjk8U9la 99zKBBpnkdKF2lvFnYYIHXB1DD3DumRd53gaw37cP/XC5NkZl0I29DJ0OAfOgIYLz0BC PUXabKJfGjaIqcUVOXTLTSVmvWpUAXsBkbUuImagZcbTCt9VhkfK4y5CK0eiiBHJ4qM5 vptg== X-Gm-Message-State: AOAM532R/95ZZ87HXZgCiRZUWVjmA7+hSqX69wcqH2gwbvqJn1ZwJYKC A3rG+5MmIVV0dgLhZgQzBEU= X-Google-Smtp-Source: ABdhPJxgeDq4WOxjOJQN0+vNyfwIGM036dcbEAa5GUj9cBrFjsN9I9AoZgNvo12QV4gNO6aX/iXePw== X-Received: by 2002:a5d:6682:: with SMTP id l2mr25344695wru.213.1607890883667; Sun, 13 Dec 2020 12:21:23 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id m11sm12338992wmi.16.2020.12.13.12.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:23 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 19/26] hw/mips/malta: Do not initialize MT registers if MT ASE absent Date: Sun, 13 Dec 2020 21:19:39 +0100 Message-Id: <20201213201946.236123-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Do not initialize MT-related config register if the MT ASE is not present. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201204222622.2743175-5-f4bug@amsat.org> --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4651a1055c9..f06cb90a44a 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1135,8 +1135,10 @@ static void malta_mips_config(MIPSCPU *cpu) CPUMIPSState *env = &cpu->env; CPUState *cs = CPU(cpu); - env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | + if (ase_mt_available(env)) { + env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC); + } } static void main_cpu_reset(void *opaque) From patchwork Sun Dec 13 20:19:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47AFDC4361B for ; Sun, 13 Dec 2020 20:23:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1AF5223998 for ; Sun, 13 Dec 2020 20:23:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405508AbgLMUX2 (ORCPT ); Sun, 13 Dec 2020 15:23:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405642AbgLMUWK (ORCPT ); Sun, 13 Dec 2020 15:22:10 -0500 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C217AC0613D3 for ; Sun, 13 Dec 2020 12:21:29 -0800 (PST) Received: by mail-wr1-x434.google.com with SMTP id a11so6649955wrr.13 for ; Sun, 13 Dec 2020 12:21:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lPfxuHaLxE9K8aKuTGSCmD6sK9ifyAYTxEpcM22e690=; b=Pr5IDJIIy1ec3blHYUhCbSak/f0RziqCIK5su9y046d1yiq063geeiaEQ9A/rOHqS1 YmXuZzav6vN5pAW+dNS9A6Lzm6NRFhk14UjAiKtbRPB0HT9O4oNODBBqXYvGT/IlzOrB jVtgM/lfkqcO/VNBCClpJZ6wRdH8eSVV36SI01vXijcQuriWNC9GMhIadVKr9TDAokcY ztO950eYWGI71rpLGbfq90p5IItiBoWufekxIvGfkSJnLTQwAUjFvgRKQCl9EhM0Kfux v3zalJvNAiSLoG5rxye32lCy3OLpmlY2Gm4I/Rn0H6Ne/scVsZg72O4oYS3QGFe6bDuc 8eKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=lPfxuHaLxE9K8aKuTGSCmD6sK9ifyAYTxEpcM22e690=; b=cCKalU3G/iIDbWyJXnOsLyP5Dx8cavcSHMEfpCIE8VojZJ+F/yF5JRvoUhmkcK75QF 1YxTsbezPaM6ozPGEzqdZBt+W7SQeF1sUE8RVU7sgkxK/ZHcZsAM3bPgsfzRZGrtSTMU 392RHlLQ12CyV3OGYLz0TEnCTc8PKwQrpYCxgW7V23G6K5cIH+IukU32HrEkmlJs1p0l XFEnevh3yhwZ94ot55tRgsfNEI9p7speYx1DbNFe1w1yFN6wwQIVETREhJ55leq08GrP 0RLWYv3RSSQXkscV7LwVQah3I0FuOM/lSrgwG7hmjYSvp4/Ii2AQlA/aLi97XyrCws8B Qheg== X-Gm-Message-State: AOAM531XZTr2gvW76XIVGagMnRnFXl6YwEK7vPTduKPEstdGbyLUUszz A1qpGMyNhFHkdUGGjB15M2w= X-Google-Smtp-Source: ABdhPJykEIfb+pgpzd8TM3ktlEuSMEG2GBmsebeicQwa/ZyOg087Gw/0IqJ5Ecv/dMNq7lQ3IwomKg== X-Received: by 2002:a05:6000:10c4:: with SMTP id b4mr25926230wrx.170.1607890888569; Sun, 13 Dec 2020 12:21:28 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id n9sm10368160wrq.41.2020.12.13.12.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:27 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 20/26] hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit() Date: Sun, 13 Dec 2020 21:19:40 +0100 Message-Id: <20201213201946.236123-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org PTC field has 8 bits, PVPE has 4. We plan to use the "hw/registerfields.h" API with MIPS CPU definitions (target/mips/cpu.h). Meanwhile we use magic 8 and 4. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201204222622.2743175-6-f4bug@amsat.org> --- hw/mips/malta.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f06cb90a44a..366f4fdfcde 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/bitops.h" #include "qemu-common.h" #include "qemu/datadir.h" #include "cpu.h" @@ -1136,8 +1137,11 @@ static void malta_mips_config(MIPSCPU *cpu) CPUState *cs = CPU(cpu); if (ase_mt_available(env)) { - env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) | - ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC); + env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, + CP0MVPC0_PTC, 8, + smp_cpus * cs->nr_threads - 1); + env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0, + CP0MVPC0_PVPE, 4, smp_cpus - 1); } } From patchwork Sun Dec 13 20:19:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E9CFC433FE for ; Sun, 13 Dec 2020 20:23:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1D16F2396F for ; Sun, 13 Dec 2020 20:23:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728685AbgLMUX1 (ORCPT ); Sun, 13 Dec 2020 15:23:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405812AbgLMUWP (ORCPT ); Sun, 13 Dec 2020 15:22:15 -0500 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D13F5C0613D6 for ; Sun, 13 Dec 2020 12:21:34 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id w206so7881922wma.0 for ; Sun, 13 Dec 2020 12:21:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IDtGX2egqT20QSVpEfuV5BUBIdAjxxq0FJmWInmLOws=; b=Rxe8/tK8x4o7R657Ex50CPpjB7/EeLZSFOP/XW+Mp4GBXVOrmqCRbWCxCDTTx9gQik x0rBQFDVRBfCSceRMW6vr0zWpwdDCV5lTNHemp/PDmd2xIab4knatraB71vETXn7AK7P RaNYEktPRVo/AgDkUZkmq+4gZV7c0YwWEqxeNLxTR7RWm5qW/1YAY7u+bn3Syll+J/G/ qr5Onq688Qk5UTFBdCX/MytWg0Esf5gND5ozdRUZFhagfjUrlaf79+cD6Sr+9UyKaJqk GDbwH1buILB/J3O50q+c6kXzfv2nc/cn2hPveeyXR0JTBMuhp0slv+HJywc43jEmgZta /X/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=IDtGX2egqT20QSVpEfuV5BUBIdAjxxq0FJmWInmLOws=; b=Ry3D/BF8bAWkkVrX38yab0CtKs93j5WOW/pLDXzqipcqP+Dc18YNeDM/RMysFVOSYH DTDU6klcVzgoBu4m6kgl4pl4ua2oNGsSYwOh9MdQXM7M2ango2oqODb3zQ+cXuKujMZL Sl9LejfoCby1SbDYiJR6BaTU3TDgdNPRgYrlmnYwRblNoIMaskbWREFiyxQshz4zxpQN i7VVGWzI7Baw/TKOBz8gk5Zgba8PDs6n6dxihxRbrttD+adlfPI9dr2Xuwo8IzpkLbWf rXiWHcaCektkAQZc9cu9yhOArN1gd+/ba4jS1rp0cp9pqwxmVxL8jH/g45BFdhaUTrfe yKcg== X-Gm-Message-State: AOAM533NfMGhdVs8DMEit1q/UqX2pxw8U2mUn7L7pxQ0Opcf+8Cmwy06 m7ugl2rktn9M9TZQjD6NcTIBOtkfrkI= X-Google-Smtp-Source: ABdhPJw978QeLLZUhsM1IEM53GS3n3KXCYYFMbTvhHOFyz2/tV3RpsUG9gPyUqOu8SIdUbYNfVOzxA== X-Received: by 2002:a05:600c:211:: with SMTP id 17mr24471325wmi.84.1607890893645; Sun, 13 Dec 2020 12:21:33 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id v189sm28388850wmg.14.2020.12.13.12.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:33 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 21/26] target/mips: Extract cpu_supports*/cpu_set* translate.c Date: Sun, 13 Dec 2020 21:19:41 +0100 Message-Id: <20201213201946.236123-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Move cpu_supports*() and cpu_set_exception_base() from translate.c to cpu.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-9-f4bug@amsat.org> --- target/mips/cpu.c | 18 ++++++++++++++++++ target/mips/translate.c | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 9d7edc1ca21..3024c51a211 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -315,3 +315,21 @@ bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) { return (env->cpu_model->insn_flags & isa_mask) != 0; } + +bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) +{ + const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); + return (mcc->cpu_def->insn_flags & isa) != 0; +} + +bool cpu_type_supports_cps_smp(const char *cpu_type) +{ + const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); + return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; +} + +void cpu_set_exception_base(int vp_index, target_ulong address) +{ + MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); + vp->env.exception_base = address; +} diff --git a/target/mips/translate.c b/target/mips/translate.c index ccc82abce04..84d2d44e5d5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31766,24 +31766,6 @@ void cpu_mips_realize_env(CPUMIPSState *env) mvp_init(env); } -bool cpu_type_supports_cps_smp(const char *cpu_type) -{ - const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); - return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; -} - -bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) -{ - const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); - return (mcc->cpu_def->insn_flags & isa) != 0; -} - -void cpu_set_exception_base(int vp_index, target_ulong address) -{ - MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); - vp->env.exception_base = address; -} - void cpu_state_reset(CPUMIPSState *env) { CPUState *cs = env_cpu(env); From patchwork Sun Dec 13 20:19:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F118C433FE for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id j7sm26852271wmb.40.2020.12.13.12.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:38 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 22/26] target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c Date: Sun, 13 Dec 2020 21:19:42 +0100 Message-Id: <20201213201946.236123-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-10-f4bug@amsat.org> --- target/mips/cpu.c | 33 +++++++++++++++++++++++++++++++++ target/mips/helper.c | 33 --------------------------------- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 3024c51a211..c29fef29d00 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -30,6 +30,7 @@ #include "exec/exec-all.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" +#include "qapi/qapi-commands-machine-target.h" static void mips_cpu_set_pc(CPUState *cs, vaddr value) { @@ -299,6 +300,38 @@ static void mips_cpu_register_types(void) type_init(mips_cpu_register_types) +static void mips_cpu_add_definition(gpointer data, gpointer user_data) +{ + ObjectClass *oc = data; + CpuDefinitionInfoList **cpu_list = user_data; + CpuDefinitionInfoList *entry; + CpuDefinitionInfo *info; + const char *typename; + + typename = object_class_get_name(oc); + info = g_malloc0(sizeof(*info)); + info->name = g_strndup(typename, + strlen(typename) - strlen("-" TYPE_MIPS_CPU)); + info->q_typename = g_strdup(typename); + + entry = g_malloc0(sizeof(*entry)); + entry->value = info; + entry->next = *cpu_list; + *cpu_list = entry; +} + +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +{ + CpuDefinitionInfoList *cpu_list = NULL; + GSList *list; + + list = object_class_get_list(TYPE_MIPS_CPU, false); + g_slist_foreach(list, mips_cpu_add_definition, &cpu_list); + g_slist_free(list); + + return cpu_list; +} + /* Could be used by generic CPU object */ MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) { diff --git a/target/mips/helper.c b/target/mips/helper.c index 0c657865793..87296fbad69 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -24,7 +24,6 @@ #include "exec/cpu_ldst.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" -#include "qapi/qapi-commands-machine-target.h" enum { TLBRET_XI = -6, @@ -1500,35 +1499,3 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, cpu_loop_exit_restore(cs, pc); } - -static void mips_cpu_add_definition(gpointer data, gpointer user_data) -{ - ObjectClass *oc = data; - CpuDefinitionInfoList **cpu_list = user_data; - CpuDefinitionInfoList *entry; - CpuDefinitionInfo *info; - const char *typename; - - typename = object_class_get_name(oc); - info = g_malloc0(sizeof(*info)); - info->name = g_strndup(typename, - strlen(typename) - strlen("-" TYPE_MIPS_CPU)); - info->q_typename = g_strdup(typename); - - entry = g_malloc0(sizeof(*entry)); - entry->value = info; - entry->next = *cpu_list; - *cpu_list = entry; -} - -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) -{ - CpuDefinitionInfoList *cpu_list = NULL; - GSList *list; - - list = object_class_get_list(TYPE_MIPS_CPU, false); - g_slist_foreach(list, mips_cpu_add_definition, &cpu_list); - g_slist_free(list); - - return cpu_list; -} From patchwork Sun Dec 13 20:19:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A65CC4361B for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id h5sm30146925wrp.56.2020.12.13.12.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:43 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 23/26] target/mips: Move cpu definitions, reset() and realize() to cpu.c Date: Sun, 13 Dec 2020 21:19:43 +0100 Message-Id: <20201213201946.236123-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Nothing TCG specific there, move to common cpu code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-16-f4bug@amsat.org> --- target/mips/internal.h | 4 - target/mips/cpu.c | 243 ++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 240 --------------------------------------- 3 files changed, 243 insertions(+), 244 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index bcd3d857ab6..0515966469b 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -207,10 +207,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) void mips_tcg_init(void); -/* TODO QOM'ify CPU reset and remove */ -void cpu_state_reset(CPUMIPSState *s); -void cpu_mips_realize_env(CPUMIPSState *env); - /* cp0_timer.c */ uint32_t cpu_mips_get_count(CPUMIPSState *env); void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c29fef29d00..f2c4de7d070 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" +#include "qemu/qemu-print.h" #include "qapi/error.h" #include "cpu.h" #include "internal.h" @@ -30,6 +31,7 @@ #include "exec/exec-all.h" #include "hw/qdev-properties.h" #include "hw/qdev-clock.h" +#include "hw/semihosting/semihost.h" #include "qapi/qapi-commands-machine-target.h" static void mips_cpu_set_pc(CPUState *cs, vaddr value) @@ -100,6 +102,247 @@ static bool mips_cpu_has_work(CPUState *cs) return has_work; } +#include "translate_init.c.inc" + +static void cpu_mips_realize_env(CPUMIPSState *env) +{ + env->exception_base = (int32_t)0xBFC00000; + +#ifndef CONFIG_USER_ONLY + mmu_init(env, env->cpu_model); +#endif + fpu_init(env, env->cpu_model); + mvp_init(env); +} + +/* TODO QOM'ify CPU reset and remove */ +static void cpu_state_reset(CPUMIPSState *env) +{ + CPUState *cs = env_cpu(env); + + /* Reset registers to their default values */ + env->CP0_PRid = env->cpu_model->CP0_PRid; + env->CP0_Config0 = env->cpu_model->CP0_Config0; +#ifdef TARGET_WORDS_BIGENDIAN + env->CP0_Config0 |= (1 << CP0C0_BE); +#endif + env->CP0_Config1 = env->cpu_model->CP0_Config1; + env->CP0_Config2 = env->cpu_model->CP0_Config2; + env->CP0_Config3 = env->cpu_model->CP0_Config3; + env->CP0_Config4 = env->cpu_model->CP0_Config4; + env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; + env->CP0_Config5 = env->cpu_model->CP0_Config5; + env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; + env->CP0_Config6 = env->cpu_model->CP0_Config6; + env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; + env->CP0_Config7 = env->cpu_model->CP0_Config7; + env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; + env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask + << env->cpu_model->CP0_LLAddr_shift; + env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; + env->SYNCI_Step = env->cpu_model->SYNCI_Step; + env->CCRes = env->cpu_model->CCRes; + env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; + env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; + env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; + env->current_tc = 0; + env->SEGBITS = env->cpu_model->SEGBITS; + env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); +#if defined(TARGET_MIPS64) + if (env->cpu_model->insn_flags & ISA_MIPS3) { + env->SEGMask |= 3ULL << 62; + } +#endif + env->PABITS = env->cpu_model->PABITS; + env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; + env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; + env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; + env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; + env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; + env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; + env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; + env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; + env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; + env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; + env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; + env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; + env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; + env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; + env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; + env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; + env->msair = env->cpu_model->MSAIR; + env->insn_flags = env->cpu_model->insn_flags; + +#if defined(CONFIG_USER_ONLY) + env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); +# ifdef TARGET_MIPS64 + /* Enable 64-bit register mode. */ + env->CP0_Status |= (1 << CP0St_PX); +# endif +# ifdef TARGET_ABI_MIPSN64 + /* Enable 64-bit address mode. */ + env->CP0_Status |= (1 << CP0St_UX); +# endif + /* + * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR + * hardware registers. + */ + env->CP0_HWREna |= 0x0000000F; + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + env->CP0_Status |= (1 << CP0St_CU1); + } + if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { + env->CP0_Status |= (1 << CP0St_MX); + } +# if defined(TARGET_MIPS64) + /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ + if ((env->CP0_Config1 & (1 << CP0C1_FP)) && + (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { + env->CP0_Status |= (1 << CP0St_FR); + } +# endif +#else /* !CONFIG_USER_ONLY */ + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, + * come back to the jump. + */ + env->CP0_ErrorEPC = (env->active_tc.PC + - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); + } else { + env->CP0_ErrorEPC = env->active_tc.PC; + } + env->active_tc.PC = env->exception_base; + env->CP0_Random = env->tlb->nb_tlb - 1; + env->tlb->tlb_in_use = env->tlb->nb_tlb; + env->CP0_Wired = 0; + env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; + env->CP0_EBase = (cs->cpu_index & 0x3FF); + if (mips_um_ksegs_enabled()) { + env->CP0_EBase |= 0x40000000; + } else { + env->CP0_EBase |= (int32_t)0x80000000; + } + if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { + env->CP0_CMGCRBase = 0x1fbf8000 >> 4; + } + env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? + 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; + env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); + /* + * Vectored interrupts not implemented, timer on int 7, + * no performance counters. + */ + env->CP0_IntCtl = 0xe0000000; + { + int i; + + for (i = 0; i < 7; i++) { + env->CP0_WatchLo[i] = 0; + env->CP0_WatchHi[i] = 0x80000000; + } + env->CP0_WatchLo[7] = 0; + env->CP0_WatchHi[7] = 0; + } + /* Count register increments in debug mode, EJTAG version 1 */ + env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); + + cpu_mips_store_count(env, 1); + + if (ase_mt_available(env)) { + int i; + + /* Only TC0 on VPE 0 starts as active. */ + for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { + env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; + env->tcs[i].CP0_TCHalt = 1; + } + env->active_tc.CP0_TCHalt = 1; + cs->halted = 1; + + if (cs->cpu_index == 0) { + /* VPE0 starts up enabled. */ + env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); + env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); + + /* TC0 starts up unhalted. */ + cs->halted = 0; + env->active_tc.CP0_TCHalt = 0; + env->tcs[0].CP0_TCHalt = 0; + /* With thread 0 active. */ + env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); + env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); + } + } + + /* + * Configure default legacy segmentation control. We use this regardless of + * whether segmentation control is presented to the guest. + */ + /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ + env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); + /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ + env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; + /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ + env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | + (2 << CP0SC_C); + /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ + env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | + (3 << CP0SC_C)) << 16; + /* USeg (seg4 0x40000000..0x7FFFFFFF) */ + env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | + (1 << CP0SC_EU) | (2 << CP0SC_C); + /* USeg (seg5 0x00000000..0x3FFFFFFF) */ + env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | + (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; + /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ + env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); +#endif /* !CONFIG_USER_ONLY */ + if ((env->insn_flags & ISA_MIPS32R6) && + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ + env->CP0_Status |= (1 << CP0St_FR); + } + + if (env->insn_flags & ISA_MIPS32R6) { + /* PTW = 1 */ + env->CP0_PWSize = 0x40; + /* GDI = 12 */ + /* UDI = 12 */ + /* MDI = 12 */ + /* PRI = 12 */ + /* PTEI = 2 */ + env->CP0_PWField = 0x0C30C302; + } else { + /* GDI = 0 */ + /* UDI = 0 */ + /* MDI = 0 */ + /* PRI = 0 */ + /* PTEI = 2 */ + env->CP0_PWField = 0x02; + } + + if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { + /* microMIPS on reset when Config3.ISA is 3 */ + env->hflags |= MIPS_HFLAG_M16; + } + + /* MSA */ + if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + msa_reset(env); + } + + compute_hflags(env); + restore_fp_status(env); + restore_pamask(env); + cs->exception_index = EXCP_NONE; + + if (semihosting_get_argc()) { + /* UHI interface can be used to obtain argc and argv */ + env->active_tc.gpr[4] = -1; + } +} + static void mips_cpu_reset(DeviceState *dev) { CPUState *s = CPU(dev); diff --git a/target/mips/translate.c b/target/mips/translate.c index 84d2d44e5d5..19933b7868c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31753,246 +31753,6 @@ void mips_tcg_init(void) #endif } -#include "translate_init.c.inc" - -void cpu_mips_realize_env(CPUMIPSState *env) -{ - env->exception_base = (int32_t)0xBFC00000; - -#ifndef CONFIG_USER_ONLY - mmu_init(env, env->cpu_model); -#endif - fpu_init(env, env->cpu_model); - mvp_init(env); -} - -void cpu_state_reset(CPUMIPSState *env) -{ - CPUState *cs = env_cpu(env); - - /* Reset registers to their default values */ - env->CP0_PRid = env->cpu_model->CP0_PRid; - env->CP0_Config0 = env->cpu_model->CP0_Config0; -#ifdef TARGET_WORDS_BIGENDIAN - env->CP0_Config0 |= (1 << CP0C0_BE); -#endif - env->CP0_Config1 = env->cpu_model->CP0_Config1; - env->CP0_Config2 = env->cpu_model->CP0_Config2; - env->CP0_Config3 = env->cpu_model->CP0_Config3; - env->CP0_Config4 = env->cpu_model->CP0_Config4; - env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; - env->CP0_Config5 = env->cpu_model->CP0_Config5; - env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; - env->CP0_Config6 = env->cpu_model->CP0_Config6; - env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; - env->CP0_Config7 = env->cpu_model->CP0_Config7; - env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; - env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask - << env->cpu_model->CP0_LLAddr_shift; - env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; - env->SYNCI_Step = env->cpu_model->SYNCI_Step; - env->CCRes = env->cpu_model->CCRes; - env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; - env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; - env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; - env->current_tc = 0; - env->SEGBITS = env->cpu_model->SEGBITS; - env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); -#if defined(TARGET_MIPS64) - if (env->cpu_model->insn_flags & ISA_MIPS3) { - env->SEGMask |= 3ULL << 62; - } -#endif - env->PABITS = env->cpu_model->PABITS; - env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; - env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; - env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; - env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; - env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; - env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; - env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; - env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; - env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; - env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; - env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; - env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; - env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; - env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; - env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; - env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; - env->msair = env->cpu_model->MSAIR; - env->insn_flags = env->cpu_model->insn_flags; - -#if defined(CONFIG_USER_ONLY) - env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); -# ifdef TARGET_MIPS64 - /* Enable 64-bit register mode. */ - env->CP0_Status |= (1 << CP0St_PX); -# endif -# ifdef TARGET_ABI_MIPSN64 - /* Enable 64-bit address mode. */ - env->CP0_Status |= (1 << CP0St_UX); -# endif - /* - * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR - * hardware registers. - */ - env->CP0_HWREna |= 0x0000000F; - if (env->CP0_Config1 & (1 << CP0C1_FP)) { - env->CP0_Status |= (1 << CP0St_CU1); - } - if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { - env->CP0_Status |= (1 << CP0St_MX); - } -# if defined(TARGET_MIPS64) - /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ - if ((env->CP0_Config1 & (1 << CP0C1_FP)) && - (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { - env->CP0_Status |= (1 << CP0St_FR); - } -# endif -#else - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, - * come back to the jump. - */ - env->CP0_ErrorEPC = (env->active_tc.PC - - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); - } else { - env->CP0_ErrorEPC = env->active_tc.PC; - } - env->active_tc.PC = env->exception_base; - env->CP0_Random = env->tlb->nb_tlb - 1; - env->tlb->tlb_in_use = env->tlb->nb_tlb; - env->CP0_Wired = 0; - env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; - env->CP0_EBase = (cs->cpu_index & 0x3FF); - if (mips_um_ksegs_enabled()) { - env->CP0_EBase |= 0x40000000; - } else { - env->CP0_EBase |= (int32_t)0x80000000; - } - if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { - env->CP0_CMGCRBase = 0x1fbf8000 >> 4; - } - env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? - 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; - env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); - /* - * Vectored interrupts not implemented, timer on int 7, - * no performance counters. - */ - env->CP0_IntCtl = 0xe0000000; - { - int i; - - for (i = 0; i < 7; i++) { - env->CP0_WatchLo[i] = 0; - env->CP0_WatchHi[i] = 0x80000000; - } - env->CP0_WatchLo[7] = 0; - env->CP0_WatchHi[7] = 0; - } - /* Count register increments in debug mode, EJTAG version 1 */ - env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); - - cpu_mips_store_count(env, 1); - - if (ase_mt_available(env)) { - int i; - - /* Only TC0 on VPE 0 starts as active. */ - for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { - env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; - env->tcs[i].CP0_TCHalt = 1; - } - env->active_tc.CP0_TCHalt = 1; - cs->halted = 1; - - if (cs->cpu_index == 0) { - /* VPE0 starts up enabled. */ - env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); - env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); - - /* TC0 starts up unhalted. */ - cs->halted = 0; - env->active_tc.CP0_TCHalt = 0; - env->tcs[0].CP0_TCHalt = 0; - /* With thread 0 active. */ - env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); - env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); - } - } - - /* - * Configure default legacy segmentation control. We use this regardless of - * whether segmentation control is presented to the guest. - */ - /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ - env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); - /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ - env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; - /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ - env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | - (2 << CP0SC_C); - /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ - env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | - (3 << CP0SC_C)) << 16; - /* USeg (seg4 0x40000000..0x7FFFFFFF) */ - env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | - (1 << CP0SC_EU) | (2 << CP0SC_C); - /* USeg (seg5 0x00000000..0x3FFFFFFF) */ - env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | - (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; - /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ - env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); -#endif - if ((env->insn_flags & ISA_MIPS32R6) && - (env->active_fpu.fcr0 & (1 << FCR0_F64))) { - /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ - env->CP0_Status |= (1 << CP0St_FR); - } - - if (env->insn_flags & ISA_MIPS32R6) { - /* PTW = 1 */ - env->CP0_PWSize = 0x40; - /* GDI = 12 */ - /* UDI = 12 */ - /* MDI = 12 */ - /* PRI = 12 */ - /* PTEI = 2 */ - env->CP0_PWField = 0x0C30C302; - } else { - /* GDI = 0 */ - /* UDI = 0 */ - /* MDI = 0 */ - /* PRI = 0 */ - /* PTEI = 2 */ - env->CP0_PWField = 0x02; - } - - if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { - /* microMIPS on reset when Config3.ISA is 3 */ - env->hflags |= MIPS_HFLAG_M16; - } - - /* MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { - msa_reset(env); - } - - compute_hflags(env); - restore_fp_status(env); - restore_pamask(env); - cs->exception_index = EXCP_NONE; - - if (semihosting_get_argc()) { - /* UHI interface can be used to obtain argc and argv */ - env->active_tc.gpr[4] = -1; - } -} - void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, target_ulong *data) { From patchwork Sun Dec 13 20:19:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9CC4C4361B for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id e16sm31304940wra.94.2020.12.13.12.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:48 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 24/26] target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn() Date: Sun, 13 Dec 2020 21:19:44 +0100 Message-Id: <20201213201946.236123-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-17-f4bug@amsat.org> --- target/mips/cpu.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index f2c4de7d070..aadc6f8e74d 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -104,17 +104,6 @@ static bool mips_cpu_has_work(CPUState *cs) #include "translate_init.c.inc" -static void cpu_mips_realize_env(CPUMIPSState *env) -{ - env->exception_base = (int32_t)0xBFC00000; - -#ifndef CONFIG_USER_ONLY - mmu_init(env, env->cpu_model); -#endif - fpu_init(env, env->cpu_model); - mvp_init(env); -} - /* TODO QOM'ify CPU reset and remove */ static void cpu_state_reset(CPUMIPSState *env) { @@ -400,6 +389,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); MIPSCPU *cpu = MIPS_CPU(dev); + CPUMIPSState *env = &cpu->env; MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); Error *local_err = NULL; @@ -423,7 +413,13 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) return; } - cpu_mips_realize_env(&cpu->env); + env->exception_base = (int32_t)0xBFC00000; + +#ifndef CONFIG_USER_ONLY + mmu_init(env, env->cpu_model); +#endif + fpu_init(env, env->cpu_model); + mvp_init(env); cpu_reset(cs); qemu_init_vcpu(cs); From patchwork Sun Dec 13 20:19:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3940C4361B for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id a14sm19603645wrn.3.2020.12.13.12.21.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:53 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 25/26] target/mips: Remove unused headers from fpu_helper.c Date: Sun, 13 Dec 2020 21:19:45 +0100 Message-Id: <20201213201946.236123-26-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-4-f4bug@amsat.org> --- target/mips/fpu_helper.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 020b768e87b..956e3417d0f 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -21,15 +21,11 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "internal.h" -#include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -#include "exec/memop.h" -#include "sysemu/kvm.h" #include "fpu/softfloat.h" From patchwork Sun Dec 13 20:19:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11971035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C6A4C433FE for ; Sun, 13 Dec 2020 20:23:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F2B0C2396F for ; Sun, 13 Dec 2020 20:23:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406196AbgLMUWx (ORCPT ); Sun, 13 Dec 2020 15:22:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2406110AbgLMUWk (ORCPT ); Sun, 13 Dec 2020 15:22:40 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE442C06179C for ; Sun, 13 Dec 2020 12:21:59 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id 190so1722479wmz.0 for ; Sun, 13 Dec 2020 12:21:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fVAITAmVV88TOoHja8gyTESqhv1q8JBRT/l8262AHZk=; b=NHiRLFi7tQsiEdJAPcfC0zbPhb6JmiwS/yPCkgmKA9XgHdOL9CAVSFJ33hrEG9NHuk VxTcak9a3ybUtHDn9Qb0ouA4nIAia2K4rA/4l6Ig1P4lPMTng48qsVzi4B7S0hIxSLTm ddoXqoZDDnR5r+msyxywj9pFkwuO8SQ8WQfGjlOowyZPmRVMzEfVyfRIU9bvBg4/pbRJ I/sjyV5KIyMcdT8b1EL3CLmKYB7LO8uRj3yt7Sx46ML2k/59VEmyABz/jy8/TJGc/6kV RAXzO4La7/sbECmoZWL4AGWSXTuA96vW92ne1NtkbXnFaXBBorVRToQyofsAZOz5723t adRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fVAITAmVV88TOoHja8gyTESqhv1q8JBRT/l8262AHZk=; b=opgpfYzUfo+Wf1h4Pc9ohuJ5Rqz02L+zLa/+CK3CLLHswYI5U9DYeMbD8lqW/Nymrm FA4CA67iCT9sYLD+A5a1/7av1GqYTTZ84USIDQKnpcZn0jyRwY9boUr4Wb8EjDJuIsht K/ivtRm27kCtJUB+KGkpea5QeHVx0k9wV60aAclyKENZJVkQAVWkFOmto/e5a6CBJhtF 5YZVo3SE8Q/uPe2X59jTrA6kkSzPtVphOdEg3SQWo1vOBdsQ1RUtdU+EGrSgyrSlDJJN IJoiErgrK59gWsshTsZVtUnP3GLiP9hjpWtRJzbcLhF4EbGY37ZbP9t6WRy2KcaDgUG9 BPwg== X-Gm-Message-State: AOAM531KCQEtk/otgDIXWkkKEUuaSz8vyTrYPBAR1q/bNYhx6AxTAQbW CDZ2K26lzICwPUShf7E95Ik= X-Google-Smtp-Source: ABdhPJz0CPv/da6KphdHRQ8txpNwxGAeqv36g/49a8+2n8jK31ow8jEvleGDUtARLN/jfRXupU+u2w== X-Received: by 2002:a1c:cc19:: with SMTP id h25mr24645226wmb.124.1607890918580; Sun, 13 Dec 2020 12:21:58 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id f16sm27335349wmh.7.2020.12.13.12.21.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:58 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 26/26] target/mips: Use FloatRoundMode enum for FCR31 modes conversion Date: Sun, 13 Dec 2020 21:19:46 +0100 Message-Id: <20201213201946.236123-27-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Use the FloatRoundMode enum type introduced in commit 3dede407cc6 ("softfloat: Name rounding mode enum") instead of 'unsigned int'. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201123204448.3260804-2-f4bug@amsat.org> --- target/mips/internal.h | 3 ++- target/mips/fpu_helper.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 0515966469b..e4d2d9f44f9 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -223,7 +223,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, uint32_t float_class_s(uint32_t arg, float_status *fst); uint64_t float_class_d(uint64_t arg, float_status *fst); -extern unsigned int ieee_rm[]; +extern const FloatRoundMode ieee_rm[4]; + void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); static inline void restore_rounding_mode(CPUMIPSState *env) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 956e3417d0f..bdb65065ee7 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -38,7 +38,7 @@ #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL /* convert MIPS rounding mode in FCR31 to IEEE library */ -unsigned int ieee_rm[] = { +const FloatRoundMode ieee_rm[4] = { float_round_nearest_even, float_round_to_zero, float_round_up,