From patchwork Mon Dec 14 18:37:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1741C4361B for ; Mon, 14 Dec 2020 18:38:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A660722525 for ; Mon, 14 Dec 2020 18:38:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2408894AbgLNSil (ORCPT ); Mon, 14 Dec 2020 13:38:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2408883AbgLNSi2 (ORCPT ); Mon, 14 Dec 2020 13:38:28 -0500 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30D1CC061793 for ; Mon, 14 Dec 2020 10:37:48 -0800 (PST) Received: by mail-wm1-x341.google.com with SMTP id 3so16186139wmg.4 for ; Mon, 14 Dec 2020 10:37:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PkbswluQKWjRx3dBtHaGXoEp5nk30ZYfIfOdkw/Z4mE=; b=so87HLcUDeHLMSRrrBIoaQWUwBf8G3+RiGUHx0pXI0M8i8oVclm5u38oWxGVU+nRE9 H1/I+bkvfeohZvPRDLGNrptdMb+bS/XgK3I3hemaCE4VuYbp+oP8+OEm6BaxdYpVWC5q 7kdq8C+VkX1BkPWurVnCHTbxnFpB1RkgtRNapuqHjZDaFp5gokompzmmnRBHp7irMovG HplSBu+h5qd5YPQpXjbyjrz2Qx+8dbFmeEToshnQT5AEFmjWT8/8pf5RXYihAN8NPqqV XW+aOXYWZUP/uJ/OYB3uskd5w4ddXWksjA52rV84hF4Rzc6VUX3VxpFwzSY8JvoiQx3F TryQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=PkbswluQKWjRx3dBtHaGXoEp5nk30ZYfIfOdkw/Z4mE=; b=UI89hgdL5ad2wwoZyquraF7rzcMQH0rqtMizGceRnufjEEN92OAVdJYsXS2NILSajH SOfAcjLHrxsNHpEsS0vRJn4cbE0dMolpxMbc8JeRtPiDUykX0ximEuZwR8u2pRRyB+ln X+xmVpyVQhiY2754fxruyCSLdCu4Z7A+3eh6OAcrXkA/4kKLNXsXkquGfIZCkPCVd5bc i7eo8/fTIyiRtbUtQnJXUxkwai+UtSCWfnuqXxNoTKIfYnuT1z5wEN+CZzpv4PobTCuQ 7JKSKmv5IlKSlsBjSi15Q0SGHcEWCAjtrq/hT2vP+FZeBuavNeAGQDuy3QCmRUYwW7al MLOA== X-Gm-Message-State: AOAM530R8i2JuEUxycXQdq9heHRhR0w6PJrBqRfyx97xNQEOBvNmGHdt J5p7pkirnIhtzquTVmJhdKo= X-Google-Smtp-Source: ABdhPJwGXLAxo6yN+sLIdbUznMxVePFYOVX87wckAVWiT7wsnNmHFrE3HhgsbKkK5tMFh6Kt4WouSg== X-Received: by 2002:a1c:2c83:: with SMTP id s125mr29306057wms.161.1607971067021; Mon, 14 Dec 2020 10:37:47 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id y7sm33139083wmb.37.2020.12.14.10.37.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:37:46 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/16] target/mips: Inline cpu_state_reset() in mips_cpu_reset() Date: Mon, 14 Dec 2020 19:37:24 +0100 Message-Id: <20201214183739.500368-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index aadc6f8e74d..7a0dcb11ecd 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -104,10 +104,16 @@ static bool mips_cpu_has_work(CPUState *cs) #include "translate_init.c.inc" -/* TODO QOM'ify CPU reset and remove */ -static void cpu_state_reset(CPUMIPSState *env) +static void mips_cpu_reset(DeviceState *dev) { - CPUState *cs = env_cpu(env); + CPUState *cs = CPU(dev); + MIPSCPU *cpu = MIPS_CPU(cs); + MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); + CPUMIPSState *env = &cpu->env; + + mcc->parent_reset(dev); + + memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); /* Reset registers to their default values */ env->CP0_PRid = env->cpu_model->CP0_PRid; @@ -330,20 +336,6 @@ static void cpu_state_reset(CPUMIPSState *env) /* UHI interface can be used to obtain argc and argv */ env->active_tc.gpr[4] = -1; } -} - -static void mips_cpu_reset(DeviceState *dev) -{ - CPUState *s = CPU(dev); - MIPSCPU *cpu = MIPS_CPU(s); - MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); - CPUMIPSState *env = &cpu->env; - - mcc->parent_reset(dev); - - memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); - - cpu_state_reset(env); #ifndef CONFIG_USER_ONLY if (kvm_enabled()) { From patchwork Mon Dec 14 18:37:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA1C3C2BB48 for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id a62sm35673893wmh.40.2020.12.14.10.37.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:37:51 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 02/16] target/mips: Extract FPU helpers to 'fpu_helper.h' Date: Mon, 14 Dec 2020 19:37:25 +0100 Message-Id: <20201214183739.500368-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201120210844.2625602-2-f4bug@amsat.org> --- target/mips/fpu_helper.h | 59 ++++++++++++++++++++++++++++++++ target/mips/internal.h | 49 -------------------------- linux-user/mips/cpu_loop.c | 1 + target/mips/fpu_helper.c | 1 + target/mips/gdbstub.c | 1 + target/mips/kvm.c | 1 + target/mips/machine.c | 1 + target/mips/msa_helper.c | 1 + target/mips/op_helper.c | 2 +- target/mips/translate.c | 1 + target/mips/translate_init.c.inc | 2 ++ 11 files changed, 69 insertions(+), 50 deletions(-) create mode 100644 target/mips/fpu_helper.h diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h new file mode 100644 index 00000000000..1c2d6d35a71 --- /dev/null +++ b/target/mips/fpu_helper.h @@ -0,0 +1,59 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "fpu/softfloat-helpers.h" +#include "cpu.h" + +extern const FloatRoundMode ieee_rm[4]; + +uint32_t float_class_s(uint32_t arg, float_status *fst); +uint64_t float_class_d(uint64_t arg, float_status *fst); + +static inline void restore_rounding_mode(CPUMIPSState *env) +{ + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], + &env->active_fpu.fp_status); +} + +static inline void restore_flush_mode(CPUMIPSState *env) +{ + set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, + &env->active_fpu.fp_status); +} + +static inline void restore_snan_bit_mode(CPUMIPSState *env) +{ + set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, + &env->active_fpu.fp_status); +} + +static inline void restore_fp_status(CPUMIPSState *env) +{ + restore_rounding_mode(env); + restore_flush_mode(env); + restore_snan_bit_mode(env); +} + +/* MSA */ + +enum CPUMIPSMSADataFormat { + DF_BYTE = 0, + DF_HALF, + DF_WORD, + DF_DOUBLE +}; + +static inline void restore_msa_fp_status(CPUMIPSState *env) +{ + float_status *status = &env->active_tc.msa_fp_status; + int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; + bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; + + set_float_rounding_mode(ieee_rm[rounding_mode], status); + set_flush_to_zero(flush_to_zero, status); + set_flush_inputs_to_zero(flush_to_zero, status); +} diff --git a/target/mips/internal.h b/target/mips/internal.h index e4d2d9f44f9..24d9f0d6a5c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,7 +9,6 @@ #define MIPS_INTERNAL_H #include "exec/memattrs.h" -#include "fpu/softfloat-helpers.h" /* * MMU types, the first four entries have the same layout as the @@ -75,13 +74,6 @@ struct mips_def_t { extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; -enum CPUMIPSMSADataFormat { - DF_BYTE = 0, - DF_HALF, - DF_WORD, - DF_DOUBLE -}; - void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); @@ -220,49 +212,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); /* op_helper.c */ -uint32_t float_class_s(uint32_t arg, float_status *fst); -uint64_t float_class_d(uint64_t arg, float_status *fst); - -extern const FloatRoundMode ieee_rm[4]; - void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); -static inline void restore_rounding_mode(CPUMIPSState *env) -{ - set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], - &env->active_fpu.fp_status); -} - -static inline void restore_flush_mode(CPUMIPSState *env) -{ - set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, - &env->active_fpu.fp_status); -} - -static inline void restore_snan_bit_mode(CPUMIPSState *env) -{ - set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, - &env->active_fpu.fp_status); -} - -static inline void restore_fp_status(CPUMIPSState *env) -{ - restore_rounding_mode(env); - restore_flush_mode(env); - restore_snan_bit_mode(env); -} - -static inline void restore_msa_fp_status(CPUMIPSState *env) -{ - float_status *status = &env->active_tc.msa_fp_status; - int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; - bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; - - set_float_rounding_mode(ieee_rm[rounding_mode], status); - set_flush_to_zero(flush_to_zero, status); - set_flush_inputs_to_zero(flush_to_zero, status); -} - static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cfe7ba5c47d..b58dbeb83d1 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -23,6 +23,7 @@ #include "cpu_loop-common.h" #include "elf.h" #include "internal.h" +#include "fpu_helper.h" # ifdef TARGET_ABI_MIPSO32 # define MIPS_SYSCALL_NUMBER_UNUSED -1 diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index bdb65065ee7..a3c05160b35 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -27,6 +27,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" +#include "fpu_helper.h" /* Complex FPU operations which may need stack space. */ diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index e39f8d75cf0..f1c2a2cf6d6 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internal.h" #include "exec/gdbstub.h" +#include "fpu_helper.h" int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 477692566a4..a5b6fe35dbc 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -24,6 +24,7 @@ #include "sysemu/runstate.h" #include "kvm_mips.h" #include "hw/boards.h" +#include "fpu_helper.h" #define DEBUG_KVM 0 diff --git a/target/mips/machine.c b/target/mips/machine.c index 5b23e3e912a..a4ea67c2980 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "internal.h" #include "migration/cpu.h" +#include "fpu_helper.h" static int cpu_post_load(void *opaque, int version_id) { diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 249f0fdad80..b89b4c44902 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" +#include "fpu_helper.h" /* Data format min and max values */ #define DF_BITS(df) (1 << ((df) + 3)) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 5aa97902e98..3386b8228e9 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -24,7 +24,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/memop.h" - +#include "fpu_helper.h" /*****************************************************************************/ /* Exceptions processing helpers */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 19933b7868c..d2614796214 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -35,6 +35,7 @@ #include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" +#include "fpu_helper.h" #define MIPS_DEBUG_DISAS 0 diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index f72fee3b40a..915277dd1f6 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -18,6 +18,8 @@ * License along with this library; if not, see . */ +#include "fpu_helper.h" + /* CPU / CPU family specific config register values. */ /* Have config1, uncached coherency */ From patchwork Mon Dec 14 18:37:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59E64C2BB40 for ; Mon, 14 Dec 2020 18:39:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2408422525 for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id p15sm24306743wrt.15.2020.12.14.10.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:37:56 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/16] target/mips: Add !CONFIG_USER_ONLY comment after #endif Date: Mon, 14 Dec 2020 19:37:26 +0100 Message-Id: <20201214183739.500368-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org To help understand ifdef'ry, add comment after #endif. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/helper.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 87296fbad69..cdd7704789d 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -455,7 +455,8 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) } } } -#endif + +#endif /* !CONFIG_USER_ONLY */ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) @@ -537,6 +538,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, } #if !defined(CONFIG_USER_ONLY) + hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { MIPSCPU *cpu = MIPS_CPU(cs); @@ -550,7 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } -#endif +#endif /* !CONFIG_USER_ONLY */ #if !defined(CONFIG_USER_ONLY) #if !defined(TARGET_MIPS64) @@ -886,7 +888,7 @@ refill: return true; } #endif -#endif +#endif /* !CONFIG_USER_ONLY */ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -1088,7 +1090,8 @@ static inline void set_badinstr_registers(CPUMIPSState *env) env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4); } } -#endif + +#endif /* !CONFIG_USER_ONLY */ void mips_cpu_do_interrupt(CPUState *cs) { @@ -1482,7 +1485,7 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) } } } -#endif +#endif /* !CONFIG_USER_ONLY */ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, From patchwork Mon Dec 14 18:37:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C18DC2BB40 for ; Mon, 14 Dec 2020 18:38:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0BC1D22525 for ; Mon, 14 Dec 2020 18:38:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2408906AbgLNSit (ORCPT ); Mon, 14 Dec 2020 13:38:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2408895AbgLNSio (ORCPT ); Mon, 14 Dec 2020 13:38:44 -0500 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF9D5C0617A6 for ; Mon, 14 Dec 2020 10:38:03 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id x22so14681027wmc.5 for ; Mon, 14 Dec 2020 10:38:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DvL7rsuXwOy7A4uG7jIuuMdjlMIgZJtQ8Sw9rQv0vgk=; b=kXAzLtsWvoRZNkxK3QfzhePj2xCpEwPeaCxWn+hS8EOAxYHORP2YvWwjfrJVnVvPsE 8Tlkx8zC5Q9G1DJ2ykbNA2MO3XK+2vihDVbBhyiamt12b0N+9sdBXuXFxr1EzW6HvxZM zL9L2cbM+QEvORrXsqF0pL5zzKDY5ACFV+L9dgpApMdTneuUglmnQA5tp0DE9xmhFUwg thbUNg+kismdH916KVP0g1X+s80HA/3zqzsINrVStNv/eNpf5KP4iimlNyn0ztxLfinf SNuSU7BrO+q17UUQv1Inb6nDwbXmE7dcF81tJeJgDX+unA0FPWD8yW1JtK2NnISt/MKg bJeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DvL7rsuXwOy7A4uG7jIuuMdjlMIgZJtQ8Sw9rQv0vgk=; b=hQLUMxjxXl4ZhExcEaw1L314IIdSgEj5OhDzxYsoXvczFBv8E7D5QFJkzXKMe3Ck5C 9jJGKOsCYEIlkanOddfexfSC/QYIhAm9c9TOr8O9/E8sEyBnvO4w5nLBxI464Ow6Z+a4 BYygi23M/p6QdUq2Yn0g+i9nDFcUkLb43cwmeMWzpyybdgSwQl8F48JOX2nmPAuoMdMt GQm20dHYep2DZFED8TpxQwhw5E7q+R7xR6UDyuClDxCIeAczBxIuG+d9yncxrnHRFTXL x6R3OwgluQ8j3Czc9R5CTYkedFlgkfFzKAMFGFHzizZAWPt7TVtRsqvwCX3g2JH4Feug RmzQ== X-Gm-Message-State: AOAM532kjt38AWr3C4ESdJOwlcJTENKNspSuqz0+Rh8ouORqM9d9jS7P 0ADhS8sYQo+LAAiYNdrKYgeh7h28SLs= X-Google-Smtp-Source: ABdhPJx3txinzJGaex7i/x3SQ8SYsfnEhn9muwCasq9NZdu9YYmx4x6odxQdU+R6stgDbXJrnCktAg== X-Received: by 2002:a1c:4d0a:: with SMTP id o10mr30042071wmh.185.1607971082664; Mon, 14 Dec 2020 10:38:02 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id n14sm32217432wmi.1.2020.12.14.10.38.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:02 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 04/16] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs Date: Mon, 14 Dec 2020 19:37:27 +0100 Message-Id: <20201214183739.500368-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index cdd7704789d..0692e232f0a 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -552,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } return phys_addr; } -#endif /* !CONFIG_USER_ONLY */ -#if !defined(CONFIG_USER_ONLY) #if !defined(TARGET_MIPS64) /* From patchwork Mon Dec 14 18:37:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80D00C2BB48 for ; Mon, 14 Dec 2020 18:38:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 47B8522525 for ; Mon, 14 Dec 2020 18:38:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2408909AbgLNSit (ORCPT ); Mon, 14 Dec 2020 13:38:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2408895AbgLNSit (ORCPT ); Mon, 14 Dec 2020 13:38:49 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 042A5C0613D3 for ; Mon, 14 Dec 2020 10:38:09 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id d26so4229364wrb.12 for ; Mon, 14 Dec 2020 10:38:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=35iXDZeU1/ndOktt2O4X9ATnWZ6nXG6x/rceHWRoTA0=; b=tBRSMIu6NzbVXjf3kPj/Qm9VfXdPqPMDdFPreznoNjiHORdK9vRa9pkfieDv+sGlbe MQoKiNx+ycUodFcc5q5Xc1DiVDW6v+m3HlI+6Ixj5cJaxdUxS9RgGBcvhpWCsgJoUkyG BilUjY9090lHE8FRyLBcMm6VjJBtWLeBdJSMaY1CIcYG4YT9qrW1wQ8LcSlC9guoK2n3 7KC0e9S8zw3Qen3YUVQR3gWDUEWRpMLj5KhW/TGks+xQ7GRQ16Ip9p2hSEg5jyF90j1+ CP6XnTKRRWYC65fywUq4BhlPftAVXBjgPWZL4zmFiaiYjtqw3Ist99Am6Jjh4mkItEN2 YIpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=35iXDZeU1/ndOktt2O4X9ATnWZ6nXG6x/rceHWRoTA0=; b=gYxvU+i4cqoQKVUoEEJe8lRZBf6TTxS4yq71/SAibI1Ah1EiunjRY7CGAfFGBxVc1J y/7kgXejp7XhUInaPS7g9t43BictDRa/4opRAk3iLSw9QT2KpOulkbmsAGYLZfjM4IXc 4GnMnpIGYQ3XnV+asedW+EsVXvS6ZhKGGxR/4iblOs/tZ7/xyKrLhn9IfE96diLkQPhq 75MKSevKdzbF0lVZ/Or5uO9A/xCSq9zB8U/14H0Umwk6p5WMNM0SKlVcftBrFRBw6lqz K+KGGwm94DUIzhy+ozLOScB7Rt1Zrjk9RWp9nxTaUGH/lNBf4dmiDv5BejMOE2HZyUIh 1J7w== X-Gm-Message-State: AOAM533ugoChtgWZff40ptN6yQZ7pc3eL4P+vSgtijg4f3VvTyg1DyJ/ Np3n6urSOKg0D6hrN/xYH3o= X-Google-Smtp-Source: ABdhPJzOy3HrSvo4JfYrDgPumHlTtg+Y0kA0lzttaDAXBEXF7YA8bLQlFtHcqal6W3UXiziMszSZKg== X-Received: by 2002:adf:a388:: with SMTP id l8mr30321919wrb.354.1607971087743; Mon, 14 Dec 2020 10:38:07 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id m17sm36097710wrn.0.2020.12.14.10.38.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:06 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/16] target/mips: Extract common helpers from helper.c to common_helper.c Date: Mon, 14 Dec 2020 19:37:28 +0100 Message-Id: <20201214183739.500368-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The rest of helper.c is TLB related. Extract the non TLB specific functions to a new file, so we can rename helper.c as tlb_helper.c in the next commit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/internal.h | 2 + target/mips/cpu.c | 215 +++++++++++++++++++++++++++++++++++++++-- target/mips/helper.c | 201 -------------------------------------- 3 files changed, 211 insertions(+), 207 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 24d9f0d6a5c..c1401492c46 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -399,6 +399,8 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); +const char *mips_exception_name(int32_t exception); + void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, int error_code, uintptr_t pc); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 7a0dcb11ecd..a54be034a2b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -34,6 +34,215 @@ #include "hw/semihosting/semihost.h" #include "qapi/qapi-commands-machine-target.h" +#if !defined(CONFIG_USER_ONLY) + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v = cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask = ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu = (v >> CP0St_CU0) & 0xf; + mx = (v >> CP0St_MX) & 0x1; + ksu = (v >> CP0St_KSU) & 0x3; + asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + + tcstatus = cu << CP0TCSt_TCU0; + tcstatus |= mx << CP0TCSt_TMX; + tcstatus |= ksu << CP0TCSt_TKSU; + tcstatus |= asid; + + if (tc == cpu->current_tc) { + tcst = &cpu->active_tc.CP0_TCStatus; + } else { + tcst = &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &= ~mask; + *tcst |= tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask = env->CP0_Status_rw_bitmask; + target_ulong old = env->CP0_Status; + + if (env->insn_flags & ISA_MIPS32R6) { + bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux = (1 << CP0St_KX) & val; + ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ + ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ + val = (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { + mask &= ~(3 << CP0St_KSU); + } + mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status = (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled */ + tlb_flush(env_cpu(env)); + } +#endif + if (ase_mt_available(env)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask = 0x00C00300; + uint32_t old = env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS32R2) { + mask |= 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS32R6) { + mask &= ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i = 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); + } + } +} + +#endif /* !CONFIG_USER_ONLY */ + +static const char * const excp_names[EXCP_LAST + 1] = { + [EXCP_RESET] = "reset", + [EXCP_SRESET] = "soft reset", + [EXCP_DSS] = "debug single step", + [EXCP_DINT] = "debug interrupt", + [EXCP_NMI] = "non-maskable interrupt", + [EXCP_MCHECK] = "machine check", + [EXCP_EXT_INTERRUPT] = "interrupt", + [EXCP_DFWATCH] = "deferred watchpoint", + [EXCP_DIB] = "debug instruction breakpoint", + [EXCP_IWATCH] = "instruction fetch watchpoint", + [EXCP_AdEL] = "address error load", + [EXCP_AdES] = "address error store", + [EXCP_TLBF] = "TLB refill", + [EXCP_IBE] = "instruction bus error", + [EXCP_DBp] = "debug breakpoint", + [EXCP_SYSCALL] = "syscall", + [EXCP_BREAK] = "break", + [EXCP_CpU] = "coprocessor unusable", + [EXCP_RI] = "reserved instruction", + [EXCP_OVERFLOW] = "arithmetic overflow", + [EXCP_TRAP] = "trap", + [EXCP_FPE] = "floating point", + [EXCP_DDBS] = "debug data break store", + [EXCP_DWATCH] = "data watchpoint", + [EXCP_LTLBL] = "TLB modify", + [EXCP_TLBL] = "TLB load", + [EXCP_TLBS] = "TLB store", + [EXCP_DBE] = "data bus error", + [EXCP_DDBL] = "debug data break load", + [EXCP_THREAD] = "thread", + [EXCP_MDMX] = "MDMX", + [EXCP_C2E] = "precise coprocessor 2", + [EXCP_CACHE] = "cache error", + [EXCP_TLBXI] = "TLB execute-inhibit", + [EXCP_TLBRI] = "TLB read-inhibit", + [EXCP_MSADIS] = "MSA disabled", + [EXCP_MSAFPE] = "MSA floating point", +}; + +const char *mips_exception_name(int32_t exception) +{ + if (exception < 0 || exception > EXCP_LAST) { + return "unknown"; + } + return excp_names[exception]; +} + +void cpu_set_exception_base(int vp_index, target_ulong address) +{ + MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); + vp->env.exception_base = address; +} + +target_ulong exception_resume_pc(CPUMIPSState *env) +{ + target_ulong bad_pc; + target_ulong isa_mode; + + isa_mode = !!(env->hflags & MIPS_HFLAG_M16); + bad_pc = env->active_tc.PC | isa_mode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ + bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + } + + return bad_pc; +} + +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index = EXCP_EXT_INTERRUPT; + env->error_code = 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, + uint32_t exception, + int error_code, + uintptr_t pc) +{ + CPUState *cs = env_cpu(env); + + qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", + __func__, exception, mips_exception_name(exception), + error_code); + cs->exception_index = exception; + env->error_code = error_code; + + cpu_loop_exit_restore(cs, pc); +} + static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu = MIPS_CPU(cs); @@ -591,9 +800,3 @@ bool cpu_type_supports_cps_smp(const char *cpu_type) const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } - -void cpu_set_exception_base(int vp_index, target_ulong address) -{ - MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); - vp->env.exception_base = address; -} diff --git a/target/mips/helper.c b/target/mips/helper.c index 0692e232f0a..59787b870b8 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -357,105 +357,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use = env->tlb->nb_tlb; } -/* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ - int32_t tcstatus, *tcst; - uint32_t v = cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask = ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu = (v >> CP0St_CU0) & 0xf; - mx = (v >> CP0St_MX) & 0x1; - ksu = (v >> CP0St_KSU) & 0x3; - asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - - tcstatus = cu << CP0TCSt_TCU0; - tcstatus |= mx << CP0TCSt_TMX; - tcstatus |= ksu << CP0TCSt_TKSU; - tcstatus |= asid; - - if (tc == cpu->current_tc) { - tcst = &cpu->active_tc.CP0_TCStatus; - } else { - tcst = &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &= ~mask; - *tcst |= tcstatus; - compute_hflags(cpu); -} - -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask = env->CP0_Status_rw_bitmask; - target_ulong old = env->CP0_Status; - - if (env->insn_flags & ISA_MIPS32R6) { - bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux = (1 << CP0St_KX) & val; - ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ - ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ - val = (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { - mask &= ~(3 << CP0St_KSU); - } - mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } - - env->CP0_Status = (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled */ - tlb_flush(env_cpu(env)); - } -#endif - if (ase_mt_available(env)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); - } -} - -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask = 0x00C00300; - uint32_t old = env->CP0_Cause; - int i; - - if (env->insn_flags & ISA_MIPS32R2) { - mask |= 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS32R6) { - mask &= ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); - } - } - - /* Set/reset software interrupts */ - for (i = 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); - } - } -} - #endif /* !CONFIG_USER_ONLY */ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, @@ -977,75 +878,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, return physical; } } -#endif /* !CONFIG_USER_ONLY */ -static const char * const excp_names[EXCP_LAST + 1] = { - [EXCP_RESET] = "reset", - [EXCP_SRESET] = "soft reset", - [EXCP_DSS] = "debug single step", - [EXCP_DINT] = "debug interrupt", - [EXCP_NMI] = "non-maskable interrupt", - [EXCP_MCHECK] = "machine check", - [EXCP_EXT_INTERRUPT] = "interrupt", - [EXCP_DFWATCH] = "deferred watchpoint", - [EXCP_DIB] = "debug instruction breakpoint", - [EXCP_IWATCH] = "instruction fetch watchpoint", - [EXCP_AdEL] = "address error load", - [EXCP_AdES] = "address error store", - [EXCP_TLBF] = "TLB refill", - [EXCP_IBE] = "instruction bus error", - [EXCP_DBp] = "debug breakpoint", - [EXCP_SYSCALL] = "syscall", - [EXCP_BREAK] = "break", - [EXCP_CpU] = "coprocessor unusable", - [EXCP_RI] = "reserved instruction", - [EXCP_OVERFLOW] = "arithmetic overflow", - [EXCP_TRAP] = "trap", - [EXCP_FPE] = "floating point", - [EXCP_DDBS] = "debug data break store", - [EXCP_DWATCH] = "data watchpoint", - [EXCP_LTLBL] = "TLB modify", - [EXCP_TLBL] = "TLB load", - [EXCP_TLBS] = "TLB store", - [EXCP_DBE] = "data bus error", - [EXCP_DDBL] = "debug data break load", - [EXCP_THREAD] = "thread", - [EXCP_MDMX] = "MDMX", - [EXCP_C2E] = "precise coprocessor 2", - [EXCP_CACHE] = "cache error", - [EXCP_TLBXI] = "TLB execute-inhibit", - [EXCP_TLBRI] = "TLB read-inhibit", - [EXCP_MSADIS] = "MSA disabled", - [EXCP_MSAFPE] = "MSA floating point", -}; - -static const char *mips_exception_name(int32_t exception) -{ - if (exception < 0 || exception > EXCP_LAST) { - return "unknown"; - } - return excp_names[exception]; -} - -target_ulong exception_resume_pc(CPUMIPSState *env) -{ - target_ulong bad_pc; - target_ulong isa_mode; - - isa_mode = !!(env->hflags & MIPS_HFLAG_M16); - bad_pc = env->active_tc.PC | isa_mode; - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, come back to - * the jump. - */ - bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - } - - return bad_pc; -} - -#if !defined(CONFIG_USER_ONLY) static void set_hflags_for_handler(CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ @@ -1400,24 +1233,6 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index = EXCP_NONE; } -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index = EXCP_EXT_INTERRUPT; - env->error_code = 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { @@ -1484,19 +1299,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) } } #endif /* !CONFIG_USER_ONLY */ - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs = env_cpu(env); - - qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", - __func__, exception, mips_exception_name(exception), - error_code); - cs->exception_index = exception; - env->error_code = error_code; - - cpu_loop_exit_restore(cs, pc); -} From patchwork Mon Dec 14 18:37:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32FA6C2BB9A for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id v20sm31460263wml.34.2020.12.14.10.38.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:12 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 06/16] target/mips: Rename helper.c as tlb_helper.c Date: Mon, 14 Dec 2020 19:37:29 +0100 Message-Id: <20201214183739.500368-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This file contains functions related to TLB management, rename it as 'tlb_helper.c'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-13-f4bug@amsat.org> --- target/mips/{helper.c => tlb_helper.c} | 2 +- target/mips/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename target/mips/{helper.c => tlb_helper.c} (99%) diff --git a/target/mips/helper.c b/target/mips/tlb_helper.c similarity index 99% rename from target/mips/helper.c rename to target/mips/tlb_helper.c index 59787b870b8..2e52539a511 100644 --- a/target/mips/helper.c +++ b/target/mips/tlb_helper.c @@ -1,5 +1,5 @@ /* - * MIPS emulation helpers for qemu. + * MIPS TLB (Translation lookaside buffer) helpers. * * Copyright (c) 2004-2005 Jocelyn Mayer * diff --git a/target/mips/meson.build b/target/mips/meson.build index 4179395a8ea..5a49951c6d7 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -4,10 +4,10 @@ 'dsp_helper.c', 'fpu_helper.c', 'gdbstub.c', - 'helper.c', 'lmmi_helper.c', 'msa_helper.c', 'op_helper.c', + 'tlb_helper.c', 'translate.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) From patchwork Mon Dec 14 18:37:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 904EEC4361B for ; Mon, 14 Dec 2020 18:41:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 550A122581 for ; Mon, 14 Dec 2020 18:41:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2408597AbgLNSjV (ORCPT ); Mon, 14 Dec 2020 13:39:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2408907AbgLNSjF (ORCPT ); Mon, 14 Dec 2020 13:39:05 -0500 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E21BC0617B0 for ; Mon, 14 Dec 2020 10:38:19 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id v14so14685282wml.1 for ; Mon, 14 Dec 2020 10:38:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1YHqfW9C9zJMYC4AZlw/rgEaF/1fbEs/5bZEvXJxOms=; b=NFZKb47HS15qKB3UYMr+dzqvtDKW4LVGYn53nUuezRuuuZx0/i+K9MpNxIaDZQkfD7 o9XG0NfiKVZAZCviwFql8IBz5V4qlv3xKF/AnfImdPOU6cg0sw22R45IkKZIvOk9e2+x PsTMXsFYEasWyTX7FJOX2/8Ef0nf99oADa8+d9c8v4C+jhIYCVUIRnZLAlcCuFTrMpSr LKGQWD57apC7qhn+WBRbcQmORjXvXY24jm/Ism+alV6z5uRJ5mPICo+nle0BD2vlJy+c bW+0hx1pyfIY/rHS3Iib1Q4H47kvRSp5Pe+4fW/qHfF04v++9DU4Mw4eH64by8e+PUXF X1Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1YHqfW9C9zJMYC4AZlw/rgEaF/1fbEs/5bZEvXJxOms=; b=T+oNawNisy4uDrC11aq7WjNkEKrVKmZKB2WydHufUoQwf4n6KcD3M67S1iuL6C78SF 1V5rfFQwAFEBSF+0OA00XtQC9VxG7vLejFV2mggBJ5h/e6zk+Ic7MnKlddWf1GxGhlbO Uxmwl1z/6GsehM4HwjrgEAhDK4f10q6iWmdPWo8u2VkRp4T8NWLfP0VZqxvda+jVch0j 7t8XAaakvvgQyVsxt57k/AtZc9cDHdKfLlAfqLH5wPVhUL7xU1v+vPF6kt1IyzQE/SYa cHy2BVSmbK0aP/eFuXytOxV4htU8kwR5tIkPErnUU8c9NmsJUOFDZZ5RSpXGhUE04WBF Z1cQ== X-Gm-Message-State: AOAM531+PVDmbxN5OjexczgZGdd2ILmz7W46b/8ccuzcLhLncAFa7ZQk XYyoF/CHzPwIQ4tGnmBvdzo= X-Google-Smtp-Source: ABdhPJxwtUczlKopDRSmG1EyYSoU0DtPkmTvGdqnbZDV9LhACCcRBx2qy8ZipUeryy41Sg/B180lGQ== X-Received: by 2002:a1c:790f:: with SMTP id l15mr29516909wme.188.1607971097824; Mon, 14 Dec 2020 10:38:17 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id j10sm15660953wmj.7.2020.12.14.10.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:17 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 07/16] target/mips: Fix code style for checkpatch.pl Date: Mon, 14 Dec 2020 19:37:30 +0100 Message-Id: <20201214183739.500368-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-14-f4bug@amsat.org> --- target/mips/translate_init.c.inc | 36 ++++++++++++++++---------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index 915277dd1f6..ff14502529b 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -934,19 +934,19 @@ void mips_cpu_list(void) } #ifndef CONFIG_USER_ONLY -static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb = 1; env->tlb->map_address = &no_mmu_map_address; } -static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb = 1; env->tlb->map_address = &fixed_mmu_map_address; } -static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); env->tlb->map_address = &r4k_map_address; @@ -958,25 +958,25 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; } -static void mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); switch (def->mmu_type) { - case MMU_TYPE_NONE: - no_mmu_init(env, def); - break; - case MMU_TYPE_R4000: - r4k_mmu_init(env, def); - break; - case MMU_TYPE_FMT: - fixed_mmu_init(env, def); - break; - case MMU_TYPE_R3000: - case MMU_TYPE_R6000: - case MMU_TYPE_R8000: - default: - cpu_abort(env_cpu(env), "MMU type not supported\n"); + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env_cpu(env), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ From patchwork Mon Dec 14 18:37:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA9C9C4361B for ; Mon, 14 Dec 2020 18:39:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AFADE2255F for ; Mon, 14 Dec 2020 18:39:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2408697AbgLNSje (ORCPT ); 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id e16sm36965915wra.94.2020.12.14.10.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:22 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 08/16] target/mips: Move mmu_init() functions to tlb_helper.c Date: Mon, 14 Dec 2020 19:37:31 +0100 Message-Id: <20201214183739.500368-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-15-f4bug@amsat.org> --- target/mips/internal.h | 1 + target/mips/tlb_helper.c | 46 ++++++++++++++++++++++++++++++ target/mips/translate_init.c.inc | 48 -------------------------------- 3 files changed, 47 insertions(+), 48 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index c1401492c46..968a3a8db8f 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -207,6 +207,7 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); /* helper.c */ +void mmu_init(CPUMIPSState *env, const mips_def_t *def); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 2e52539a511..94a482e3dbe 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -120,6 +120,52 @@ int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, return TLBRET_NOMATCH; } +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1; + env->tlb->map_address = &no_mmu_map_address; +} + +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1; + env->tlb->map_address = &fixed_mmu_map_address; +} + +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); + env->tlb->map_address = &r4k_map_address; + env->tlb->helper_tlbwi = r4k_helper_tlbwi; + env->tlb->helper_tlbwr = r4k_helper_tlbwr; + env->tlb->helper_tlbp = r4k_helper_tlbp; + env->tlb->helper_tlbr = r4k_helper_tlbr; + env->tlb->helper_tlbinv = r4k_helper_tlbinv; + env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; +} + +void mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); + + switch (def->mmu_type) { + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env_cpu(env), "MMU type not supported\n"); + } +} + static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) { /* diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index ff14502529b..a788f5a6b6d 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -933,54 +933,6 @@ void mips_cpu_list(void) } } -#ifndef CONFIG_USER_ONLY -static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb = 1; - env->tlb->map_address = &no_mmu_map_address; -} - -static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb = 1; - env->tlb->map_address = &fixed_mmu_map_address; -} - -static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); - env->tlb->map_address = &r4k_map_address; - env->tlb->helper_tlbwi = r4k_helper_tlbwi; - env->tlb->helper_tlbwr = r4k_helper_tlbwr; - env->tlb->helper_tlbp = r4k_helper_tlbp; - env->tlb->helper_tlbr = r4k_helper_tlbr; - env->tlb->helper_tlbinv = r4k_helper_tlbinv; - env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; -} - -static void mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); - - switch (def->mmu_type) { - case MMU_TYPE_NONE: - no_mmu_init(env, def); - break; - case MMU_TYPE_R4000: - r4k_mmu_init(env, def); - break; - case MMU_TYPE_FMT: - fixed_mmu_init(env, def); - break; - case MMU_TYPE_R3000: - case MMU_TYPE_R6000: - case MMU_TYPE_R8000: - default: - cpu_abort(env_cpu(env), "MMU type not supported\n"); - } -} -#endif /* CONFIG_USER_ONLY */ - static void fpu_init (CPUMIPSState *env, const mips_def_t *def) { int i; From patchwork Mon Dec 14 18:37:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4213FC2BBCA for ; Mon, 14 Dec 2020 18:41:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B58822581 for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id i7sm20396778wrv.12.2020.12.14.10.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:27 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/16] target/mips: Rename translate_init.c as cpu-defs.c Date: Mon, 14 Dec 2020 19:37:32 +0100 Message-Id: <20201214183739.500368-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This file is not TCG specific, contains CPU definitions and is consumed by cpu.c. Rename it as such. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu.c | 2 +- target/mips/{translate_init.c.inc => cpu-defs.c.inc} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (100%) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a54be034a2b..4191c0741f4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -311,7 +311,7 @@ static bool mips_cpu_has_work(CPUState *cs) return has_work; } -#include "translate_init.c.inc" +#include "cpu-defs.c.inc" static void mips_cpu_reset(DeviceState *dev) { diff --git a/target/mips/translate_init.c.inc b/target/mips/cpu-defs.c.inc similarity index 100% rename from target/mips/translate_init.c.inc rename to target/mips/cpu-defs.c.inc From patchwork Mon Dec 14 18:37:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88328C4361B for ; Mon, 14 Dec 2020 18:39:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 396A72255F for ; Mon, 14 Dec 2020 18:39:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2408802AbgLNSjp (ORCPT ); Mon, 14 Dec 2020 13:39:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2408537AbgLNSjQ (ORCPT ); Mon, 14 Dec 2020 13:39:16 -0500 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88703C061793 for ; Mon, 14 Dec 2020 10:38:34 -0800 (PST) Received: by mail-wr1-x442.google.com with SMTP id a11so9707504wrr.13 for ; Mon, 14 Dec 2020 10:38:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LfYo5MaDY/iw8/2Abe7qf6wWPlyXVqcAmraXknKsAuI=; b=cDfL6rFJmoXL5vtpNF/4gnVblMRdchArkhxPQyCm3J2TZeP57Jcvrf5TIbIrVGIUeT 35nGhFPTcFlGqxFusVNpIQlEjtGgbkvzQIr+L9MnVklUn/V5secx8J6xPA5GHYOY5qna nFlJwbfJ51llCxurlCT8mDUQkPXNIBZuW7Qpa4O1304oeGInFXN5/C6MmL5myfYLE4WJ mGjVrgqzk0p6Jin1wWS95Wbq7VGZVjmsNQKunn2SmQdefd5mIluNkKGBoEaQOVNJlXY1 UvxRg5mRSj2T1apqPMkD46FISkHhgdZY2lI54fRnk9jU6IpjeUZ7jCpcgGOq5nO79xbg nyag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=LfYo5MaDY/iw8/2Abe7qf6wWPlyXVqcAmraXknKsAuI=; b=CL7kEOnsv5pmFmXppSI7L9a4R+AW+4GhOJ5MmTfZCIhhpyNwfUEIbd7KLkPAydAO+T Ksjz0jxIoqNUCKHMihDN8N7OEsOjw99Pe5s2t97/sB47xKVklhR+rNzajAhiVSFJKi+7 WXDjb61tjgED3jiUGfmbRBl3nojifT0DG4jUkC1TaCm7CE6eB8R/VSjHEjnSDsm2j97E WMDsvt7c4ZOyOFizhPHbwk1TPTVF8cy6U66f8nD7mH44BngWwzX+7LZX+QgZNjL3LQSZ XScau+zWcWYfnGUlfxNujspv47IJ2G4uF95TtotI21KwNZrXSBKhXaQhAuVkVnFxPbo4 K5/w== X-Gm-Message-State: AOAM531hG2oxV4X/A8CcwBM9j0YPCvXKqIXXdJPmrICVj9ZCzv8UHQCR uA2vDmkwO2Mnne7u4TvF2/Q= X-Google-Smtp-Source: ABdhPJxPEIZTvdb4fQSO7SAH8bxWAMxU5T9x6Cy3p1ighhXZQ87LEqC4RFNJudb1413UkAGHmoxApA== X-Received: by 2002:a5d:61c4:: with SMTP id q4mr30479856wrv.304.1607971113318; Mon, 14 Dec 2020 10:38:33 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id o7sm16373552wrw.62.2020.12.14.10.38.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:32 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 10/16] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() Date: Mon, 14 Dec 2020 19:37:33 +0100 Message-Id: <20201214183739.500368-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org generate_exception_err(err=0) is simply generate_exception_end(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index d2614796214..2662cf26fe7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2956,7 +2956,7 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64 arg) static inline void check_cp0_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { - generate_exception_err(ctx, EXCP_CpU, 0); + generate_exception_end(ctx, EXCP_CpU); } } @@ -3162,10 +3162,10 @@ static inline void check_mt(DisasContext *ctx) static inline void check_cp0_mt(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { - generate_exception_err(ctx, EXCP_CpU, 0); + generate_exception_end(ctx, EXCP_CpU); } else { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { - generate_exception_err(ctx, EXCP_RI, 0); + generate_exception_end(ctx, EXCP_RI); } } } From patchwork Mon Dec 14 18:37:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1726C2BB40 for ; Mon, 14 Dec 2020 18:41:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 59DD122525 for ; Mon, 14 Dec 2020 18:41:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2408823AbgLNSkC (ORCPT ); Mon, 14 Dec 2020 13:40:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2408629AbgLNSjZ (ORCPT ); Mon, 14 Dec 2020 13:39:25 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A59EBC06179C for ; Mon, 14 Dec 2020 10:38:44 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id w206so9537969wma.0 for ; Mon, 14 Dec 2020 10:38:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z4msl+4E6QtN6RCQD089Ehf2sv+vjVAWY6z4uBcfgdk=; b=DrDZm/9e0lVMSvZGjsIYjHK94ow+Jg5D8TItRlY9LizKyMcpKEvRgNUACXmaxqgSm/ rG16dqW9KtMQQ4EUwmY6ebTXQC+UAAV9zxqB8CoaYZx1l8VuToAuCWUjxhlYvabVB1X8 L1rdGB4P1fUIPm+pYAfsNjlG/iicbg6rAkFKGNcTqzpQm0c8sdLJerwqElgw1M3tJ6G6 xnZ44g/I12U9vLGVJbrctPB3k8joVqHIcOjVvfRUZ3cHezjvT+bPTbuOylBVikUyu3N8 FlFKlM98G+kNm1e7mr9DPkOVWKHbfuvCkQp07yVSDl9dCzdPbJJmTYQaFnJhJFFbfSkZ tHMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=z4msl+4E6QtN6RCQD089Ehf2sv+vjVAWY6z4uBcfgdk=; b=sYyUSXEHGv5sZ63QpN77CJTEDX3G4uOVjpbg9AzgIDPV3k61Ey4ES7HCzdtMZ0mkJK RpcMb+oTyeozpww5FtNJY5aoa58gkPIM+ywl8/sbmTUR5x+gfToGkYXUqd6uosl1g4cX 10QZzL7AG4sELlux1L34xxpY6//qnGNnrrBZl1SsRPTTkYqgvFfoMih+Hx3lxBZApvPc YQG3dfZIxo4+DH4E24MFeWpK/2JxC312+ekfifjy2x+elL4jufSgWcemuueX827JnOl0 twX/HtNRCV153TANx5uaetmtrt2bZuuu7sL5evkxc7YuS3Smd8JU7ZqvO3F65dIrR6zC 3z1A== X-Gm-Message-State: AOAM530gf6MY8kKSX62aUnQnZ4v+gYhAyEVEZJyA0Wl/cqzrZkslsW9X nMFjglivT3VZaLQUNLzcc9umqdHzU40= X-Google-Smtp-Source: ABdhPJwl6pcDop1GdGO4Cb9M9Dsjwa8SEcn5CnQdkLcnNoCGQzV5Bj0mR7LYdZNaxsMtDUxaCAAh4A== X-Received: by 2002:a7b:cb93:: with SMTP id m19mr30063317wmi.45.1607971123469; Mon, 14 Dec 2020 10:38:43 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id v7sm31858058wma.26.2020.12.14.10.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:42 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 12/16] target/mips/translate: Extract DisasContext structure Date: Mon, 14 Dec 2020 19:37:35 +0100 Message-Id: <20201214183739.500368-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Extract DisasContext to a new 'translate.h' header so different translation files (ISA, ASE, extensions) can use it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-2-f4bug@amsat.org> --- target/mips/translate.h | 50 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 38 +------------------------------ 2 files changed, 51 insertions(+), 37 deletions(-) create mode 100644 target/mips/translate.h diff --git a/target/mips/translate.h b/target/mips/translate.h new file mode 100644 index 00000000000..fcda1a99001 --- /dev/null +++ b/target/mips/translate.h @@ -0,0 +1,50 @@ +/* + * MIPS translation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef TARGET_MIPS_TRANSLATE_H +#define TARGET_MIPS_TRANSLATE_H + +#include "exec/translator.h" + +typedef struct DisasContext { + DisasContextBase base; + target_ulong saved_pc; + target_ulong page_start; + uint32_t opcode; + uint64_t insn_flags; + int32_t CP0_Config1; + int32_t CP0_Config2; + int32_t CP0_Config3; + int32_t CP0_Config5; + /* Routine used to access memory */ + int mem_idx; + MemOp default_tcg_memop_mask; + uint32_t hflags, saved_hflags; + target_ulong btarget; + bool ulri; + int kscrexist; + bool rxi; + int ie; + bool bi; + bool bp; + uint64_t PAMask; + bool mvh; + bool eva; + bool sc; + int CP0_LLAddr_shift; + bool ps; + bool vp; + bool cmgcr; + bool mrp; + bool nan2008; + bool abs2008; + bool saar; + bool mi; + int gi; +} DisasContext; + +#endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 49570a95615..0db0fce3789 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -36,6 +36,7 @@ #include "exec/log.h" #include "qemu/qemu-print.h" #include "fpu_helper.h" +#include "translate.h" #define MIPS_DEBUG_DISAS 0 @@ -2554,43 +2555,6 @@ static TCGv mxu_CR; tcg_temp_free_i32(helper_tmp); \ } while (0) -typedef struct DisasContext { - DisasContextBase base; - target_ulong saved_pc; - target_ulong page_start; - uint32_t opcode; - uint64_t insn_flags; - int32_t CP0_Config1; - int32_t CP0_Config2; - int32_t CP0_Config3; - int32_t CP0_Config5; - /* Routine used to access memory */ - int mem_idx; - MemOp default_tcg_memop_mask; - uint32_t hflags, saved_hflags; - target_ulong btarget; - bool ulri; - int kscrexist; - bool rxi; - int ie; - bool bi; - bool bp; - uint64_t PAMask; - bool mvh; - bool eva; - bool sc; - int CP0_LLAddr_shift; - bool ps; - bool vp; - bool cmgcr; - bool mrp; - bool nan2008; - bool abs2008; - bool saar; - bool mi; - int gi; -} DisasContext; - #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 From patchwork Mon Dec 14 18:37:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79EA2C2BB48 for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id q1sm31550246wrj.8.2020.12.14.10.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:47 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 13/16] target/mips/translate: Add declarations for generic code Date: Mon, 14 Dec 2020 19:37:36 +0100 Message-Id: <20201214183739.500368-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-3-f4bug@amsat.org> --- target/mips/translate.h | 38 ++++++++++++++++++++++++++++++++ target/mips/translate.c | 48 +++++++++++++---------------------------- 2 files changed, 53 insertions(+), 33 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index fcda1a99001..989d6c43207 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -10,6 +10,8 @@ #include "exec/translator.h" +#define MIPS_DEBUG_DISAS 0 + typedef struct DisasContext { DisasContextBase base; target_ulong saved_pc; @@ -47,4 +49,40 @@ typedef struct DisasContext { int gi; } DisasContext; +/* MIPS major opcodes */ +#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) + +void generate_exception_err(DisasContext *ctx, int excp, int err); +void generate_exception_end(DisasContext *ctx, int excp); +void gen_reserved_instruction(DisasContext *ctx); +void check_insn(DisasContext *ctx, uint64_t flags); +#ifdef TARGET_MIPS64 +void check_mips_64(DisasContext *ctx); +#endif + +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset); +void gen_load_gpr(TCGv t, int reg); +void gen_store_gpr(TCGv t, int reg); + +extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv bcond; + +#define LOG_DISAS(...) \ + do { \ + if (MIPS_DEBUG_DISAS) { \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \ + } \ + } while (0) + +#define MIPS_INVAL(op) \ + do { \ + if (MIPS_DEBUG_DISAS) { \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, \ + TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \ + ctx->base.pc_next, ctx->opcode, op, \ + ctx->opcode >> 26, ctx->opcode & 0x3F, \ + ((ctx->opcode >> 16) & 0x1F)); \ + } \ + } while (0) + #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 0db0fce3789..318642cbcfe 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -38,11 +38,6 @@ #include "fpu_helper.h" #include "translate.h" -#define MIPS_DEBUG_DISAS 0 - -/* MIPS major opcodes */ -#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) - enum { /* indirect opcode tables */ OPC_SPECIAL = (0x00 << 26), @@ -2491,9 +2486,10 @@ enum { }; /* global register indices */ -static TCGv cpu_gpr[32], cpu_PC; +TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; -static TCGv cpu_dspctrl, btarget, bcond; +static TCGv cpu_dspctrl, btarget; +TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; @@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] = { }; #endif -#define LOG_DISAS(...) \ - do { \ - if (MIPS_DEBUG_DISAS) { \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \ - } \ - } while (0) - -#define MIPS_INVAL(op) \ - do { \ - if (MIPS_DEBUG_DISAS) { \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, \ - TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \ - ctx->base.pc_next, ctx->opcode, op, \ - ctx->opcode >> 26, ctx->opcode & 0x3F, \ - ((ctx->opcode >> 16) & 0x1F)); \ - } \ - } while (0) - /* General purpose registers moves. */ -static inline void gen_load_gpr(TCGv t, int reg) +void gen_load_gpr(TCGv t, int reg) { if (reg == 0) { tcg_gen_movi_tl(t, 0); @@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg) } } -static inline void gen_store_gpr(TCGv t, int reg) +void gen_store_gpr(TCGv t, int reg) { if (reg != 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); @@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx) } } -static inline void generate_exception_err(DisasContext *ctx, int excp, int err) +void generate_exception_err(DisasContext *ctx, int excp, int err) { TCGv_i32 texcp = tcg_const_i32(excp); TCGv_i32 terr = tcg_const_i32(err); @@ -2779,11 +2757,16 @@ static inline void generate_exception(DisasContext *ctx, int excp) gen_helper_0e0i(raise_exception, excp); } -static inline void generate_exception_end(DisasContext *ctx, int excp) +void generate_exception_end(DisasContext *ctx, int excp) { generate_exception_err(ctx, excp, 0); } +void gen_reserved_instruction(DisasContext *ctx) +{ + generate_exception_end(ctx, EXCP_RI); +} + /* Floating point register moves. */ static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { @@ -3013,7 +2996,7 @@ static inline void check_dsp_r3(DisasContext *ctx) * This code generates a "reserved instruction" exception if the * CPU does not support the instruction set corresponding to flags. */ -static inline void check_insn(DisasContext *ctx, uint64_t flags) +void check_insn(DisasContext *ctx, uint64_t flags) { if (unlikely(!(ctx->insn_flags & flags))) { gen_reserved_instruction(ctx); @@ -3064,7 +3047,7 @@ static inline void check_ps(DisasContext *ctx) * This code generates a "reserved instruction" exception if 64-bit * instructions are not enabled. */ -static inline void check_mips_64(DisasContext *ctx) +void check_mips_64(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { gen_reserved_instruction(ctx); @@ -3390,8 +3373,7 @@ OP_LD_ATOMIC(lld, ld64); #endif #undef OP_LD_ATOMIC -static void gen_base_offset_addr(DisasContext *ctx, TCGv addr, - int base, int offset) +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset) { if (base == 0) { tcg_gen_movi_tl(addr, offset); From patchwork Mon Dec 14 18:37:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA702C4361B for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id a14sm24486383wrn.3.2020.12.14.10.38.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:52 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 14/16] target/mips: Declare generic FPU functions in 'translate.h' Date: Mon, 14 Dec 2020 19:37:37 +0100 Message-Id: <20201214183739.500368-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some FPU translation functions / registers can be used by ISA / ASE / extensions out of the big translate.c file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.h | 7 +++++++ target/mips/translate.c | 12 ++++++------ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 989d6c43207..a30fbf21ff9 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -59,12 +59,19 @@ void check_insn(DisasContext *ctx, uint64_t flags); #ifdef TARGET_MIPS64 void check_mips_64(DisasContext *ctx); #endif +void check_cp1_enabled(DisasContext *ctx); void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset); void gen_load_gpr(TCGv t, int reg); void gen_store_gpr(TCGv t, int reg); +void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); +void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); +int get_fp_bit(int cc); + extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv_i32 fpu_fcr0, fpu_fcr31; +extern TCGv_i64 fpu_f64[32]; extern TCGv bcond; #define LOG_DISAS(...) \ diff --git a/target/mips/translate.c b/target/mips/translate.c index 318642cbcfe..08ed542f4d4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2492,8 +2492,8 @@ static TCGv cpu_dspctrl, btarget; TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; -static TCGv_i32 fpu_fcr0, fpu_fcr31; -static TCGv_i64 fpu_f64[32]; +TCGv_i32 fpu_fcr0, fpu_fcr31; +TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; #if defined(TARGET_MIPS64) @@ -2809,7 +2809,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) } } -static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { tcg_gen_mov_i64(t, fpu_f64[reg]); @@ -2818,7 +2818,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) } } -static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { tcg_gen_mov_i64(fpu_f64[reg], t); @@ -2832,7 +2832,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) } } -static inline int get_fp_bit(int cc) +int get_fp_bit(int cc) { if (cc) { return 24 + cc; @@ -2907,7 +2907,7 @@ static inline void check_cp0_enabled(DisasContext *ctx) } } -static inline void check_cp1_enabled(DisasContext *ctx) +void check_cp1_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { generate_exception_err(ctx, EXCP_CpU, 1); From patchwork Mon Dec 14 18:37:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FC0AC4361B for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id m81sm33713025wmf.29.2020.12.14.10.38.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:57 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 15/16] target/mips: Extract FPU specific definitions to translate.h Date: Mon, 14 Dec 2020 19:37:38 +0100 Message-Id: <20201214183739.500368-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Extract FPU specific definitions that can be used by ISA / ASE / extensions to translate.h header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.h | 71 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 70 ---------------------------------------- 2 files changed, 71 insertions(+), 70 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index a30fbf21ff9..a9eab69249f 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -52,6 +52,77 @@ typedef struct DisasContext { /* MIPS major opcodes */ #define MASK_OP_MAJOR(op) (op & (0x3F << 26)) +#define OPC_CP1 (0x11 << 26) + +/* Coprocessor 1 (rs field) */ +#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) + +/* Values for the fmt field in FP instructions */ +enum { + /* 0 - 15 are reserved */ + FMT_S = 16, /* single fp */ + FMT_D = 17, /* double fp */ + FMT_E = 18, /* extended fp */ + FMT_Q = 19, /* quad fp */ + FMT_W = 20, /* 32-bit fixed */ + FMT_L = 21, /* 64-bit fixed */ + FMT_PS = 22, /* paired single fp */ + /* 23 - 31 are reserved */ +}; + +enum { + OPC_MFC1 = (0x00 << 21) | OPC_CP1, + OPC_DMFC1 = (0x01 << 21) | OPC_CP1, + OPC_CFC1 = (0x02 << 21) | OPC_CP1, + OPC_MFHC1 = (0x03 << 21) | OPC_CP1, + OPC_MTC1 = (0x04 << 21) | OPC_CP1, + OPC_DMTC1 = (0x05 << 21) | OPC_CP1, + OPC_CTC1 = (0x06 << 21) | OPC_CP1, + OPC_MTHC1 = (0x07 << 21) | OPC_CP1, + OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */ + OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1, + OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1, + OPC_BZ_V = (0x0B << 21) | OPC_CP1, + OPC_BNZ_V = (0x0F << 21) | OPC_CP1, + OPC_S_FMT = (FMT_S << 21) | OPC_CP1, + OPC_D_FMT = (FMT_D << 21) | OPC_CP1, + OPC_E_FMT = (FMT_E << 21) | OPC_CP1, + OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1, + OPC_W_FMT = (FMT_W << 21) | OPC_CP1, + OPC_L_FMT = (FMT_L << 21) | OPC_CP1, + OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1, + OPC_BC1EQZ = (0x09 << 21) | OPC_CP1, + OPC_BC1NEZ = (0x0D << 21) | OPC_CP1, + OPC_BZ_B = (0x18 << 21) | OPC_CP1, + OPC_BZ_H = (0x19 << 21) | OPC_CP1, + OPC_BZ_W = (0x1A << 21) | OPC_CP1, + OPC_BZ_D = (0x1B << 21) | OPC_CP1, + OPC_BNZ_B = (0x1C << 21) | OPC_CP1, + OPC_BNZ_H = (0x1D << 21) | OPC_CP1, + OPC_BNZ_W = (0x1E << 21) | OPC_CP1, + OPC_BNZ_D = (0x1F << 21) | OPC_CP1, +}; + +#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F)) +#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16))) + +enum { + OPC_BC1F = (0x00 << 16) | OPC_BC1, + OPC_BC1T = (0x01 << 16) | OPC_BC1, + OPC_BC1FL = (0x02 << 16) | OPC_BC1, + OPC_BC1TL = (0x03 << 16) | OPC_BC1, +}; + +enum { + OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2, + OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2, +}; + +enum { + OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4, + OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4, +}; + void generate_exception_err(DisasContext *ctx, int excp, int err); void generate_exception_end(DisasContext *ctx, int excp); void gen_reserved_instruction(DisasContext *ctx); diff --git a/target/mips/translate.c b/target/mips/translate.c index 08ed542f4d4..cc876019bf7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -43,7 +43,6 @@ enum { OPC_SPECIAL = (0x00 << 26), OPC_REGIMM = (0x01 << 26), OPC_CP0 = (0x10 << 26), - OPC_CP1 = (0x11 << 26), OPC_CP2 = (0x12 << 26), OPC_CP3 = (0x13 << 26), OPC_SPECIAL2 = (0x1C << 26), @@ -996,75 +995,6 @@ enum { OPC_WAIT = 0x20 | OPC_C0, }; -/* Coprocessor 1 (rs field) */ -#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) - -/* Values for the fmt field in FP instructions */ -enum { - /* 0 - 15 are reserved */ - FMT_S = 16, /* single fp */ - FMT_D = 17, /* double fp */ - FMT_E = 18, /* extended fp */ - FMT_Q = 19, /* quad fp */ - FMT_W = 20, /* 32-bit fixed */ - FMT_L = 21, /* 64-bit fixed */ - FMT_PS = 22, /* paired single fp */ - /* 23 - 31 are reserved */ -}; - -enum { - OPC_MFC1 = (0x00 << 21) | OPC_CP1, - OPC_DMFC1 = (0x01 << 21) | OPC_CP1, - OPC_CFC1 = (0x02 << 21) | OPC_CP1, - OPC_MFHC1 = (0x03 << 21) | OPC_CP1, - OPC_MTC1 = (0x04 << 21) | OPC_CP1, - OPC_DMTC1 = (0x05 << 21) | OPC_CP1, - OPC_CTC1 = (0x06 << 21) | OPC_CP1, - OPC_MTHC1 = (0x07 << 21) | OPC_CP1, - OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */ - OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1, - OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1, - OPC_BZ_V = (0x0B << 21) | OPC_CP1, - OPC_BNZ_V = (0x0F << 21) | OPC_CP1, - OPC_S_FMT = (FMT_S << 21) | OPC_CP1, - OPC_D_FMT = (FMT_D << 21) | OPC_CP1, - OPC_E_FMT = (FMT_E << 21) | OPC_CP1, - OPC_Q_FMT = (FMT_Q << 21) | OPC_CP1, - OPC_W_FMT = (FMT_W << 21) | OPC_CP1, - OPC_L_FMT = (FMT_L << 21) | OPC_CP1, - OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1, - OPC_BC1EQZ = (0x09 << 21) | OPC_CP1, - OPC_BC1NEZ = (0x0D << 21) | OPC_CP1, - OPC_BZ_B = (0x18 << 21) | OPC_CP1, - OPC_BZ_H = (0x19 << 21) | OPC_CP1, - OPC_BZ_W = (0x1A << 21) | OPC_CP1, - OPC_BZ_D = (0x1B << 21) | OPC_CP1, - OPC_BNZ_B = (0x1C << 21) | OPC_CP1, - OPC_BNZ_H = (0x1D << 21) | OPC_CP1, - OPC_BNZ_W = (0x1E << 21) | OPC_CP1, - OPC_BNZ_D = (0x1F << 21) | OPC_CP1, -}; - -#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F)) -#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16))) - -enum { - OPC_BC1F = (0x00 << 16) | OPC_BC1, - OPC_BC1T = (0x01 << 16) | OPC_BC1, - OPC_BC1FL = (0x02 << 16) | OPC_BC1, - OPC_BC1TL = (0x03 << 16) | OPC_BC1, -}; - -enum { - OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2, - OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2, -}; - -enum { - OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4, - OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4, -}; - #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21))) enum { From patchwork Mon Dec 14 18:37:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 11972741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 629C7C4361B for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id 94sm33793630wrq.22.2020.12.14.10.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:39:02 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 16/16] target/mips: Only build TCG code when CONFIG_TCG is set Date: Mon, 14 Dec 2020 19:37:39 +0100 Message-Id: <20201214183739.500368-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-20-f4bug@amsat.org> --- target/mips/meson.build | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 5a49951c6d7..596eb1aeeb3 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,9 +1,11 @@ mips_ss = ss.source_set() mips_ss.add(files( 'cpu.c', + 'gdbstub.c', +)) +mips_ss.add(when: 'CONFIG_TCG', if_true: files( 'dsp_helper.c', 'fpu_helper.c', - 'gdbstub.c', 'lmmi_helper.c', 'msa_helper.c', 'op_helper.c', @@ -15,11 +17,13 @@ mips_softmmu_ss = ss.source_set() mips_softmmu_ss.add(files( 'addr.c', - 'cp0_helper.c', 'cp0_timer.c', 'machine.c', 'mips-semi.c', )) +mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( + 'cp0_helper.c', +)) target_arch += {'mips': mips_ss} target_softmmu_arch += {'mips': mips_softmmu_ss}