From patchwork Thu Nov 8 09:04:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 10673803 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B1C21057 for ; Thu, 8 Nov 2018 09:06:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 590D32B659 for ; Thu, 8 Nov 2018 09:06:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 499962BA97; Thu, 8 Nov 2018 09:06:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE6FB2B659 for ; Thu, 8 Nov 2018 09:06:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726653AbeKHSju (ORCPT ); Thu, 8 Nov 2018 13:39:50 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:50551 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726359AbeKHSjs (ORCPT ); Thu, 8 Nov 2018 13:39:48 -0500 Received: by mail-wm1-f68.google.com with SMTP id 124-v6so453279wmw.0 for ; Thu, 08 Nov 2018 01:05:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jRCk5lNBlPCD7GwKBzaRehaZeMJbLJXp2+/KqxIsFvY=; b=PRCeYAKI1JDWmpfIB+fVwGmz1XhZopfERjhSMfAfj3b0fJndvCuqDwWV6yzY1OtbFK 0W//QSrqpdNuwU+HsEqHP9pCgjJsWcXAJay1v5nz294M2/jrG/HVUvpKpy0mHF2fRCeq M0S3gqspgYb9Z1kMebrHkdqa0KPLAVfu6Vbzg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jRCk5lNBlPCD7GwKBzaRehaZeMJbLJXp2+/KqxIsFvY=; b=X4BSafc+0QcXNbCZRwnQhTE4H0ub5vq6wlMz2NmgNIj8weWHANx6Y7WkKqKvlIuEzO cNUDoQRGUJZREI009FR70ZC/2eztUAkpEdqXpjC0bK/N2SW9HryYWSMdEYkX3tUFjemJ 0C3hwqpP8xrFQ8evoiuy6O8yGWJovP+yoStOXyIiC9EkGyMMXqA+atvVmcxDtjJpWbGA 9Wr3OVQbdvrxum4wpDWdO3eb90ELZmi1GgQIyOEciWGkIWXLN0rEaBoILlQDCvKCXIOV IK9IEfEVUASjZRC/5YcW+VCgYhmjDUYuh7/GdtsrQACF9ugqh+VpR+OLSZ1kn7WpURjg ZDfQ== X-Gm-Message-State: AGRZ1gKqeguMVrYIBT+GKbQNM71Mq/iibk/7/5yNkWYnPOUvfVye4kig YPGII+HWScMjsYF9gj4T6Ff0lw== X-Google-Smtp-Source: AJdET5fTS06uzWUmAt5qrVnJNaHoFWBuVdlyggZVVgrWQkFkHAKhOM7cxVKHTm9+CO0iMvwifDK43A== X-Received: by 2002:a1c:b4c1:: with SMTP id d184-v6mr412831wmf.143.1541667916129; Thu, 08 Nov 2018 01:05:16 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1094:149:440c:9368:8cda:a020]) by smtp.gmail.com with ESMTPSA id l140-v6sm6974469wmb.24.2018.11.08.01.05.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Nov 2018 01:05:15 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH v2 1/4] dt-bindings: hwlock: Document STM32 hwspinlock bindings Date: Thu, 8 Nov 2018 10:04:59 +0100 Message-Id: <20181108090502.14543-2-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181108090502.14543-1-benjamin.gaignard@st.com> References: <20181108090502.14543-1-benjamin.gaignard@st.com> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add bindings for STM32 hardware spinlock device Signed-off-by: Benjamin Gaignard --- version 2 : - change clock name from hwspinlock to hsem to be align with hardware documentation .../bindings/hwlock/st,stm32-hwspinlock.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt new file mode 100644 index 000000000000..6e933b218574 --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt @@ -0,0 +1,23 @@ +STM32 Hardware Spinlock Device Binding +------------------------------------- + +Required properties : +- compatible : should be "st,stm32-hwspinlock". +- reg : the register address of hwspinlock. +- #hwlock-cells : hwlock users only use the hwlock id to represent a specific + hwlock, so the number of cells should be <1> here. +- clock-names : Must contain "hwspinlock". +- clocks : Must contain a phandle entry for the clock in clock-names, see the + common clock bindings. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example of hwlock provider: + hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hsem"; + }; From patchwork Thu Nov 8 09:05:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 10673779 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A83E813BF for ; Thu, 8 Nov 2018 09:05:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 981962B659 for ; Thu, 8 Nov 2018 09:05:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8BFEF2BA97; Thu, 8 Nov 2018 09:05:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 007332BA2B for ; Thu, 8 Nov 2018 09:05:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726926AbeKHSjv (ORCPT ); Thu, 8 Nov 2018 13:39:51 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:34090 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726663AbeKHSju (ORCPT ); Thu, 8 Nov 2018 13:39:50 -0500 Received: by mail-wm1-f67.google.com with SMTP id f1-v6so1032681wmg.1 for ; Thu, 08 Nov 2018 01:05:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vfYBXlI8TGzQiJThszSCkUGyt2x6cRpuleHBiD2O0WI=; b=gKwZFQEdxyx71OjEc1WYHh9hL7tMQAk1Q8NN1gKz3OPhXyowjVnmGmtP0pclDo03UO jjKBlQLxFIkeyqHRGQsU/p+AQxRhePTpYb9qaM1xBbr821jcgAfPA1Av1uKR1HzXbFeP acI/vnI+Lg+psXV1HGPrLaaUyj1gdfRBbrkuk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vfYBXlI8TGzQiJThszSCkUGyt2x6cRpuleHBiD2O0WI=; b=GZKfmsNyGzqeaIuGeLAClUd/cN9/7F5bzLa+TzV/hRIg7kSU0SsEvl05bb0mGceije 9vEL0hT9uAXFHnF3upzc2U4OQHIqcoIG0WM3qGHSaNU11LP5js8XNlpb9kh6i6/5CMo8 wOZl2on6djjXobKmW8kc8ZSLiS0TjjqXIZMSCa8bWC/z5Vo96xiSuG6CkdxTMe2ZwT8X 4iVu0SMA87NzhvhTkcHooe+3ew44GlsiTqBPXcP/IHz4iWgM366DFOiEFobaQ/9vHi+c J5T/5UiTqb+qvxMBLqPTbY8EfGaIhGiMUi5oB8cgE4x3apm5Lu0yNctbjFV9sAijDCXs jEjw== X-Gm-Message-State: AGRZ1gLR28dJfuC9FGfnxKcvSbEjcgm3bYT4ii8r8TBztzDhbtex6b1f F0npyNox0ILkCMKvLiD8HAw3Dg== X-Google-Smtp-Source: AJdET5daqR3GTzFPF6l1if10VOkqfNJEXMu/mgNdH/Wxr1L2Ju2kHGfkTLvH6nFDdqH4PTUsvvOX4A== X-Received: by 2002:a1c:5706:: with SMTP id l6-v6mr443683wmb.51.1541667918008; Thu, 08 Nov 2018 01:05:18 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1094:149:440c:9368:8cda:a020]) by smtp.gmail.com with ESMTPSA id l140-v6sm6974469wmb.24.2018.11.08.01.05.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Nov 2018 01:05:17 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH v2 2/4] hwspinlock: add STM32 hwspinlock device Date: Thu, 8 Nov 2018 10:05:00 +0100 Message-Id: <20181108090502.14543-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181108090502.14543-1-benjamin.gaignard@st.com> References: <20181108090502.14543-1-benjamin.gaignard@st.com> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support of hardware semaphores for stm32mp1 SoC. The hardware block provides 32 semaphores. Signed-off-by: Benjamin Gaignard --- version 2 : - change clock name from hwspinlock to hsem to be align with hardware documentation - remove useless licence terms from header - fix alphabetic order issues - do not abort remove function if hwspin_lock_unregister() failed drivers/hwspinlock/Kconfig | 9 +++ drivers/hwspinlock/Makefile | 1 + drivers/hwspinlock/stm32_hwspinlock.c | 144 ++++++++++++++++++++++++++++++++++ 3 files changed, 154 insertions(+) create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig index e895d29500ee..7869c67e5b6b 100644 --- a/drivers/hwspinlock/Kconfig +++ b/drivers/hwspinlock/Kconfig @@ -49,6 +49,15 @@ config HWSPINLOCK_SPRD If unsure, say N. +config HWSPINLOCK_STM32 + tristate "STM32 Hardware Spinlock device" + depends on MACH_STM32MP157 + depends on HWSPINLOCK + help + Say y here to support the STM32 Hardware Spinlock device. + + If unsure, say N. + config HSEM_U8500 tristate "STE Hardware Semaphore functionality" depends on HWSPINLOCK diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile index b87c01a506a4..ed053e3f02be 100644 --- a/drivers/hwspinlock/Makefile +++ b/drivers/hwspinlock/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_QCOM) += qcom_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_SIRF) += sirf_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_SPRD) += sprd_hwspinlock.o +obj-$(CONFIG_HWSPINLOCK_STM32) += stm32_hwspinlock.o obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o diff --git a/drivers/hwspinlock/stm32_hwspinlock.c b/drivers/hwspinlock/stm32_hwspinlock.c new file mode 100644 index 000000000000..7eb36a5bbf68 --- /dev/null +++ b/drivers/hwspinlock/stm32_hwspinlock.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics SA 2018 + * Author: Benjamin Gaignard for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hwspinlock_internal.h" + +#define STM32_MUTEX_COREID BIT(8) +#define STM32_MUTEX_LOCK_BIT BIT(31) +#define STM32_MUTEX_NUM_LOCKS 32 + +struct stm32_hwspinlock { + struct clk *clk; + struct hwspinlock_device bank; +}; + +static int stm32_hwspinlock_trylock(struct hwspinlock *lock) +{ + void __iomem *lock_addr = lock->priv; + u32 status; + + writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, lock_addr); + status = readl(lock_addr); + + return status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID); +} + +static void stm32_hwspinlock_unlock(struct hwspinlock *lock) +{ + void __iomem *lock_addr = lock->priv; + + writel(STM32_MUTEX_COREID, lock_addr); +} + +static const struct hwspinlock_ops stm32_hwspinlock_ops = { + .trylock = stm32_hwspinlock_trylock, + .unlock = stm32_hwspinlock_unlock, +}; + +static int stm32_hwspinlock_probe(struct platform_device *pdev) +{ + struct stm32_hwspinlock *hw; + void __iomem *io_base; + struct resource *res; + size_t array_size; + int i, ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + io_base = devm_ioremap_resource(&pdev->dev, res); + if (!io_base) + return -ENOMEM; + + array_size = STM32_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); + hw = devm_kzalloc(&pdev->dev, sizeof(*hw) + array_size, GFP_KERNEL); + if (!hw) + return -ENOMEM; + + hw->clk = devm_clk_get(&pdev->dev, "hsem"); + if (IS_ERR(hw->clk)) + return PTR_ERR(hw->clk); + + for (i = 0; i < STM32_MUTEX_NUM_LOCKS; i++) + hw->bank.lock[i].priv = io_base + i * sizeof(u32); + + platform_set_drvdata(pdev, hw); + pm_runtime_enable(&pdev->dev); + + ret = hwspin_lock_register(&hw->bank, &pdev->dev, &stm32_hwspinlock_ops, + 0, STM32_MUTEX_NUM_LOCKS); + + if (ret) + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int stm32_hwspinlock_remove(struct platform_device *pdev) +{ + struct stm32_hwspinlock *hw = platform_get_drvdata(pdev); + int ret; + + ret = hwspin_lock_unregister(&hw->bank); + if (ret) + dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); + + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused stm32_hwspinlock_runtime_suspend(struct device *dev) +{ + struct stm32_hwspinlock *hw = dev_get_drvdata(dev); + + clk_disable_unprepare(hw->clk); + + return 0; +} + +static int __maybe_unused stm32_hwspinlock_runtime_resume(struct device *dev) +{ + struct stm32_hwspinlock *hw = dev_get_drvdata(dev); + + clk_prepare_enable(hw->clk); + + return 0; +} + +static const struct dev_pm_ops stm32_hwspinlock_pm_ops = { + SET_RUNTIME_PM_OPS(stm32_hwspinlock_runtime_suspend, + stm32_hwspinlock_runtime_resume, + NULL) +}; + +static const struct of_device_id stm32_hwpinlock_ids[] = { + { .compatible = "st,stm32-hwspinlock", }, + {}, +}; +MODULE_DEVICE_TABLE(of, stm32_hwpinlock_ids); + +static struct platform_driver stm32_hwspinlock_driver = { + .probe = stm32_hwspinlock_probe, + .remove = stm32_hwspinlock_remove, + .driver = { + .name = "stm32_hwspinlock", + .of_match_table = stm32_hwpinlock_ids, + .pm = &stm32_hwspinlock_pm_ops, + }, +}; +module_platform_driver(stm32_hwspinlock_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Hardware spinlock driver for STM32 SoCs"); +MODULE_AUTHOR("Benjamin Gaignard "); From patchwork Thu Nov 8 09:05:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 10673801 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB39613BF for ; Thu, 8 Nov 2018 09:06:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9AD3F2B659 for ; Thu, 8 Nov 2018 09:06:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8E9CC2BA97; Thu, 8 Nov 2018 09:06:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 43C982B659 for ; Thu, 8 Nov 2018 09:06:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726890AbeKHSjv (ORCPT ); Thu, 8 Nov 2018 13:39:51 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:56260 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726846AbeKHSjv (ORCPT ); Thu, 8 Nov 2018 13:39:51 -0500 Received: by mail-wm1-f65.google.com with SMTP id s10-v6so436219wmc.5 for ; Thu, 08 Nov 2018 01:05:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tQkj1hz0jEEKFJdYxtoN3LCnWHFTEXeYAE7pWLaze8c=; b=bZP5HsXKn+NmVZUSWhMsRAUIB1J4stGd5tz0mcnKqJ8haMeq5yBEqxBOjzyK8AaaAT JBJ3ueWEg6b6sV9/RspHgteD14PuGQJvmvdkoNdoE08d1fT9H/ymvM88SjucAmv2IRgM yvlf5K+Ernu/tqAZ3JjtWOhJQLwrMBq8TLn2c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tQkj1hz0jEEKFJdYxtoN3LCnWHFTEXeYAE7pWLaze8c=; b=A7G+YzSMhJw6HTyLRXvKe9v9h1SfrfBODWMsgIPCI187NX4X2dDZNxXN9wwqzSNycA Ppy6LJqbuCITrTly1YPOfBBJQRVCJgZFsH+6VL7Wn6Od8HEyfmQ8I3WyZ/4qTUxg/mwk 5io78hPvjT3Urh/sJwEq/zgmhd63SlLpQ5n4QXIq0wybC4l6cqYhBNVX7fCr95KyVkLx FuSZUNkLmkQTGLRd603EF6VAooMTPO7XTcC0lrpZj1QZWqU66Zqdmvd2Si0pXxH7amou Z3d/ADdEbqrXwy2QCnCpinwgs8ve3qKBWx1lf+wPiOM3J7RZPv2Mljz9cDYdnikHutNL 9Ibw== X-Gm-Message-State: AGRZ1gJmHu1dvqfS//f5ap5Fp6bZ5vKGI5T1gr53rZ5Pi9BH8WwNkzxJ JfK6flxYE0DqtUQ9Me6F3SJy8w== X-Google-Smtp-Source: AJdET5dWLP0Ce4B9uITjiq/lmAggodgFZlChTXhroWfVryZH8jjR7e4xWMzgmBWrk3AvoTdTZjH9bg== X-Received: by 2002:a1c:8314:: with SMTP id f20-v6mr446270wmd.120.1541667919767; Thu, 08 Nov 2018 01:05:19 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1094:149:440c:9368:8cda:a020]) by smtp.gmail.com with ESMTPSA id l140-v6sm6974469wmb.24.2018.11.08.01.05.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Nov 2018 01:05:19 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH v2 3/4] ARM: dts: stm32: Add hwspinlock node for stm32mp157 SoC Date: Thu, 8 Nov 2018 10:05:01 +0100 Message-Id: <20181108090502.14543-4-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181108090502.14543-1-benjamin.gaignard@st.com> References: <20181108090502.14543-1-benjamin.gaignard@st.com> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Declare hwspinlock device for stm32mp157 SoC Signed-off-by: Benjamin Gaignard --- version 2 : - change clock name from hwspinlock to hsem to be align with hardware documentation arch/arm/boot/dts/stm32mp157c.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 185541a5b69f..98f824d8b0f0 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -803,6 +803,15 @@ status = "disabled"; }; + hsem: hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hwsem"; + status = "disabled"; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; From patchwork Thu Nov 8 09:05:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 10673781 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0FE41057 for ; Thu, 8 Nov 2018 09:05:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1DE32B659 for ; Thu, 8 Nov 2018 09:05:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D5B342BA97; Thu, 8 Nov 2018 09:05:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8ED0F2B659 for ; Thu, 8 Nov 2018 09:05:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726649AbeKHSjx (ORCPT ); Thu, 8 Nov 2018 13:39:53 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:56262 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726836AbeKHSjx (ORCPT ); Thu, 8 Nov 2018 13:39:53 -0500 Received: by mail-wm1-f65.google.com with SMTP id s10-v6so436307wmc.5 for ; Thu, 08 Nov 2018 01:05:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7C/wrspMfUQvsFMTcgDRLQWNrIa3gG/vxf/pbqlMaK8=; b=GFUvTNHosU9EGyVuBqbiVyi/VR8Q1jV/Q7erazAt4wlxRAbU/4G+zA8uahY1+BZmSF LA9GoVdAOQg+ysjc/Qx1d58HPqtMRA/Z/jA9HnVi2qRMb+oByD6bymWrzK2OzP4pG52g EpzWWHFiljYmWJ847nAWMLssfJo19wqjuMhWg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7C/wrspMfUQvsFMTcgDRLQWNrIa3gG/vxf/pbqlMaK8=; b=Szj4LaDHS/hzU5U0uLV9GSSRLS/6Rv5RgLt5ToOl6QZ1H7nV4o7ragHrA2GxIdqQ0u KXjGAFdAEQaBjc+fYmkcvX93u3i9C7NsGTqXIpwjk0JorNhAaJv/ygtqxIR2ibXI4u/a PaLv6zViEmSlEfiJc1/AeOhZX4zNkWjbghN4/Yl3fHjgOUUPkhX+NZHPYOQfbVuE7QUA s29cGulWKuE9BXRq51mQCCO+6QUpO+mnjD8veawjQQSXRDuOofan4aGpS9jclJGNgt12 9PgCzVpC5OBy2iPW84niqALQV8Kha758I0Yn+xZiB5c6XFv8xUk+TGOtBJqe6goMXybf aSjA== X-Gm-Message-State: AGRZ1gKvsAIQf/hACZxeRRm6RVIA4IrQXx9ned+vCpBKhseV9IyAOn2D mkNO9nmVTxd/THxZdU3plXBkzg== X-Google-Smtp-Source: AJdET5eo7NLKsq4nCro/TskDB1tEsDKTt/G/XujosQSzN7bJZQt7DssrB8rqYu0lQxZHrJtkrl0aRQ== X-Received: by 2002:a1c:84:: with SMTP id 126-v6mr410351wma.96.1541667921577; Thu, 08 Nov 2018 01:05:21 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1094:149:440c:9368:8cda:a020]) by smtp.gmail.com with ESMTPSA id l140-v6sm6974469wmb.24.2018.11.08.01.05.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Nov 2018 01:05:21 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH v2 4/4] ARM: dts: stm32: enable hwspinlock on stm32mp157c-ed1 Date: Thu, 8 Nov 2018 10:05:02 +0100 Message-Id: <20181108090502.14543-5-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181108090502.14543-1-benjamin.gaignard@st.com> References: <20181108090502.14543-1-benjamin.gaignard@st.com> Sender: linux-remoteproc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Activate hwspinlock for stm32mp157c-ed1 Signed-off-by: Benjamin Gaignard --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index f77bea49c079..158a337b3129 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -94,3 +94,7 @@ vdda1v1-supply = <®11>; vdda1v8-supply = <®18>; }; + +&hsem { + status = "okay"; +};