From patchwork Thu Nov 8 11:26:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10674029 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CC9614E2 for ; Thu, 8 Nov 2018 11:26:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B4DE28B57 for ; Thu, 8 Nov 2018 11:26:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4FED12AC2E; Thu, 8 Nov 2018 11:26:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CD58528B57 for ; Thu, 8 Nov 2018 11:26:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727324AbeKHVBj (ORCPT ); Thu, 8 Nov 2018 16:01:39 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:34046 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbeKHVBi (ORCPT ); Thu, 8 Nov 2018 16:01:38 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wA8BPwpw025662; Thu, 8 Nov 2018 05:25:58 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1541676358; bh=bVIQo3ZWc1LkxowL3VZwE7p5BNrMzbAcQF5KeYBH/2A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=m3jUOa9GBRqjx9CAzPHE8GmbySlLmwut9G71bO/h8SIBd7z6nH5NQJ8OMu6Wo+nKI zVfyWwY/GEbgMfT/9kmVACQEoZxvWNxdyOO1sE+RhJIM+vVhRHPmsRxLFcQp4/zm/C bk2aWxypRiLysOMFU3a0hHJvaep3NDlkvgHPPeaw= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wA8BPwdW016521 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Nov 2018 05:25:58 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 8 Nov 2018 05:25:58 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 8 Nov 2018 05:25:58 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wA8BPqhU011714; Thu, 8 Nov 2018 05:25:56 -0600 From: Vignesh R To: Tero Kristo , Rob Herring CC: Nishanth Menon , Mark Rutland , , , , Vignesh R Subject: [PATCH 1/2] dt-bindings: pinctrl: k3-am6: Introduce pinmux definitions Date: Thu, 8 Nov 2018 16:56:46 +0530 Message-ID: <20181108112647.7205-2-vigneshr@ti.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108112647.7205-1-vigneshr@ti.com> References: <20181108112647.7205-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tero Kristo The dt-bindings header for TI K3-AM6 SoCs define a set of macros for defining pinmux configs in human readable form, instead of raw-coded hex values. Signed-off-by: Tero Kristo Signed-off-by: Lokesh Vutla Signed-off-by: Vignesh R --- MAINTAINERS | 1 + include/dt-bindings/pinctrl/k3-am6.h | 49 ++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 include/dt-bindings/pinctrl/k3-am6.h diff --git a/MAINTAINERS b/MAINTAINERS index fb58c64dda49..7fd59955fd21 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2204,6 +2204,7 @@ S: Supported F: Documentation/devicetree/bindings/arm/ti/k3.txt F: arch/arm64/boot/dts/ti/Makefile F: arch/arm64/boot/dts/ti/k3-* +F: include/dt-bindings/pinctrl/k3-am6.h ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE M: Santosh Shilimkar diff --git a/include/dt-bindings/pinctrl/k3-am6.h b/include/dt-bindings/pinctrl/k3-am6.h new file mode 100644 index 000000000000..42e22ee57600 --- /dev/null +++ b/include/dt-bindings/pinctrl/k3-am6.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for TI K3-AM6 pinctrl bindings. + * + * Copyright (C) 2018 Texas Instruments + */ +#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM6_H +#define _DT_BINDINGS_PINCTRL_TI_K3_AM6_H + +/* K3 mux mode options for each pin. See TRM for options */ +#define MUX_MODE0 0 +#define MUX_MODE1 1 +#define MUX_MODE2 2 +#define MUX_MODE3 3 +#define MUX_MODE4 4 +#define MUX_MODE5 5 +#define MUX_MODE6 6 +#define MUX_MODE7 7 +#define MUX_MODE15 15 + +#define PULL_DISABLE (1 << 16) +#define PULL_UP (1 << 17) +#define INPUT_EN (1 << 18) +#define SLEWCTRL_200MHZ 0 +#define SLEWCTRL_150MHZ (1 << 19) +#define SLEWCTRL_100MHZ (2 << 19) +#define SLEWCTRL_50MHZ (3 << 19) +#define TX_DIS (1 << 21) +#define ISO_OVR (1 << 22) +#define ISO_BYPASS (1 << 23) +#define DS_EN (1 << 24) +#define DS_INPUT (1 << 25) +#define DS_FORCE_OUT_HIGH (1 << 26) +#define DS_PULL_UP_DOWN_EN 0 +#define DS_PULL_UP_DOWN_DIS (1 << 27) +#define DS_PULL_UP_SEL (1 << 28) +#define WAKEUP_ENABLE (1 << 29) + +#define PIN_OUTPUT (PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (PULL_UP) +#define PIN_OUTPUT_PULLDOWN 0 +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN) + +#define AM65X_IOPAD(pa, val) (((pa) & 0x1fff)) (val) +#define AM65X_WKUP_IOPAD(pa, val) (((pa) & 0x1fff)) (val) + +#endif From patchwork Thu Nov 8 11:26:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 10674023 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7642B13BF for ; Thu, 8 Nov 2018 11:26:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6008628B57 for ; Thu, 8 Nov 2018 11:26:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 50D2F2AC2E; Thu, 8 Nov 2018 11:26:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4654E28B57 for ; Thu, 8 Nov 2018 11:26:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726274AbeKHVB2 (ORCPT ); Thu, 8 Nov 2018 16:01:28 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:53258 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbeKHVB2 (ORCPT ); Thu, 8 Nov 2018 16:01:28 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id wA8BQ1he003566; Thu, 8 Nov 2018 05:26:01 -0600 Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wA8BQ1P1038749 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 8 Nov 2018 05:26:01 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Thu, 8 Nov 2018 05:26:00 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Thu, 8 Nov 2018 05:26:00 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wA8BPqhV011714; Thu, 8 Nov 2018 05:25:58 -0600 From: Vignesh R To: Tero Kristo , Rob Herring CC: Nishanth Menon , Mark Rutland , , , , Vignesh R Subject: [PATCH 2/2] arm64: dts: ti: k3-am65: Add pinctrl regions Date: Thu, 8 Nov 2018 16:56:47 +0530 Message-ID: <20181108112647.7205-3-vigneshr@ti.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181108112647.7205-1-vigneshr@ti.com> References: <20181108112647.7205-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tero Kristo Add pinctrl regions for the main and wkup mmr. The range for main pinctrl region contains a gap at offset 0x2e4, and because of this, the pinctrl range is split into two sections. Signed-off-by: Tero Kristo Signed-off-by: Vignesh R --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 + 3 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index adcd6341e40c..f7c2a60d5c80 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -69,4 +69,20 @@ clock-frequency = <48000000>; current-speed = <115200>; }; + + main_pmx0: pinmux@11c000 { + compatible = "pinctrl-single"; + reg = <0x0 0x11c000 0x0 0x2e4>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_pmx1: pinmux@11c2e8 { + compatible = "pinctrl-single"; + reg = <0x0 0x11c2e8 0x0 0x24>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 8d7b47f9dfbf..19b46f40789b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -34,6 +34,14 @@ }; }; + wkup_pmx0: pinmux@4301c000 { + compatible = "pinctrl-single"; + reg = <0x4301c000 0x118>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + wkup_uart0: serial@42300000 { compatible = "ti,am654-uart"; reg = <0x42300000 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 3d4bf369d030..873dca1d0813 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { model = "Texas Instruments K3 AM654 SoC";