From patchwork Tue Dec 22 06:33:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 11985895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DAC9C433E0 for ; Tue, 22 Dec 2020 06:51:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E95F622B2D for ; Tue, 22 Dec 2020 06:51:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E95F622B2D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 698D86E141; Tue, 22 Dec 2020 06:51:35 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id E80226E141 for ; Tue, 22 Dec 2020 06:51:31 +0000 (UTC) IronPort-SDR: EhT4XK8zMNuPAtjE72qQfxv+PYbqp4/1hz2QY0dzwThFClEefFzX69R8JT8DCa0ogr9Qf2wxyv x4nnyfJDCzFA== X-IronPort-AV: E=McAfee;i="6000,8403,9842"; a="162883458" X-IronPort-AV: E=Sophos;i="5.78,438,1599548400"; d="scan'208";a="162883458" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2020 22:51:31 -0800 IronPort-SDR: NbDa/HGmT1/fcO9Ve+CvqVRY+6OfeJ36iK7uIJRfLwipWREiVufbd0Gr4V/XTL9qrXAKNFvqvz hnoWOBR4UnNA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,438,1599548400"; d="scan'208";a="356209217" Received: from amanna.iind.intel.com ([10.223.74.76]) by orsmga002.jf.intel.com with ESMTP; 21 Dec 2020 22:51:30 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Dec 2020 12:03:58 +0530 Message-Id: <20201222063400.9509-2-animesh.manna@intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20201222063400.9509-1-animesh.manna@intel.com> References: <20201222063400.9509-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/dsb: multi dsb instance support in prepare() and cleanup() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Command buffer allocation is done for all 3 dsb instances for every pipe and cleanup code is modified accordingly. v1: Initial version. v2: Improved commit description. Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_atomic.c | 9 +- drivers/gpu/drm/i915/display/intel_display.c | 6 +- .../drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dsb.c | 99 ++++++++++--------- 4 files changed, 65 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index e00fdc47c0eb..3833f3b4851b 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -226,6 +226,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) { const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state); struct intel_crtc_state *crtc_state; + int i; crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); if (!crtc_state) @@ -252,7 +253,9 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state->wm.need_postvbl_update = false; crtc_state->fb_bits = 0; crtc_state->update_planes = 0; - crtc_state->dsb = NULL; + + for (i = 0; i < MAX_DSB_PER_PIPE; i++) + crtc_state->dsb[i] = NULL; return &crtc_state->uapi; } @@ -293,8 +296,10 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(state); + int i; - drm_WARN_ON(crtc->dev, crtc_state->dsb); + for (i = 0; i < MAX_DSB_PER_PIPE; i++) + drm_WARN_ON(crtc->dev, crtc_state->dsb[i]); __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); intel_crtc_free_hw_state(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 78452de5e12f..3afe8a22c784 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16256,7 +16256,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) struct intel_crtc *crtc; u64 put_domains[I915_MAX_PIPES] = {}; intel_wakeref_t wakeref = 0; - int i; + int i, j; intel_atomic_commit_fence_wait(state); @@ -16386,7 +16386,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * cleanup. So copy and reset the dsb structure to sync with * commit_done and later do dsb cleanup in cleanup_work. */ - old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); + for (j = 0; j < MAX_DSB_PER_PIPE; j++) + old_crtc_state->dsb[j] = + fetch_and_zero(&new_crtc_state->dsb[j]); } /* Underruns don't always raise interrupts, so check manually */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 5bc5bfbc4551..06ae7470ab8c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1124,7 +1124,7 @@ struct intel_crtc_state { enum transcoder mst_master_transcoder; /* For DSB related info */ - struct intel_dsb *dsb; + struct intel_dsb *dsb[MAX_DSB_PER_PIPE]; u32 psr2_man_track_ctl; }; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 566fa72427b3..cef1015cc04f 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -92,7 +92,7 @@ static bool intel_dsb_disable_engine(struct drm_i915_private *i915, void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, i915_reg_t reg, u32 val) { - struct intel_dsb *dsb = crtc_state->dsb; + struct intel_dsb *dsb = crtc_state->dsb[0]; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 *buf; @@ -174,7 +174,7 @@ void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, struct intel_dsb *dsb; u32 *buf; - dsb = crtc_state->dsb; + dsb = crtc_state->dsb[0]; if (!dsb) { intel_de_write(dev_priv, reg, val); return; @@ -202,7 +202,7 @@ void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, */ void intel_dsb_commit(const struct intel_crtc_state *crtc_state) { - struct intel_dsb *dsb = crtc_state->dsb; + struct intel_dsb *dsb = crtc_state->dsb[0]; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -266,49 +266,52 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state) struct i915_vma *vma; u32 *buf; intel_wakeref_t wakeref; + int i; if (!HAS_DSB(i915)) return; - dsb = kmalloc(sizeof(*dsb), GFP_KERNEL); - if (!dsb) { - drm_err(&i915->drm, "DSB object creation failed\n"); - return; - } - - wakeref = intel_runtime_pm_get(&i915->runtime_pm); - - obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE); - if (IS_ERR(obj)) { - drm_err(&i915->drm, "Gem object creation failed\n"); - kfree(dsb); - goto out; - } - - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); - if (IS_ERR(vma)) { - drm_err(&i915->drm, "Vma creation failed\n"); - i915_gem_object_put(obj); - kfree(dsb); - goto out; - } - - buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); - if (IS_ERR(buf)) { - drm_err(&i915->drm, "Command buffer creation failed\n"); - i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); - kfree(dsb); - goto out; - } - - dsb->id = DSB1; - dsb->vma = vma; - dsb->cmd_buf = buf; - dsb->free_pos = 0; - dsb->ins_start_offset = 0; - crtc_state->dsb = dsb; + for (i = 0 ; i < MAX_DSB_PER_PIPE; i++) { + dsb = kmalloc(sizeof(*dsb), GFP_KERNEL); + if (!dsb) { + drm_err(&i915->drm, "DSB%d obj creation failed\n", i); + continue; + } + + wakeref = intel_runtime_pm_get(&i915->runtime_pm); + + obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE); + if (IS_ERR(obj)) { + drm_err(&i915->drm, "Gem object creation failed\n"); + kfree(dsb); + goto out; + } + + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); + if (IS_ERR(vma)) { + drm_err(&i915->drm, "Vma creation failed\n"); + i915_gem_object_put(obj); + kfree(dsb); + goto out; + } + + buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); + if (IS_ERR(buf)) { + drm_err(&i915->drm, "Command buffer creation failed\n"); + i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); + kfree(dsb); + goto out; + } + + dsb->id = i; + dsb->vma = vma; + dsb->cmd_buf = buf; + dsb->free_pos = 0; + dsb->ins_start_offset = 0; + crtc_state->dsb[i] = dsb; out: - intel_runtime_pm_put(&i915->runtime_pm, wakeref); + intel_runtime_pm_put(&i915->runtime_pm, wakeref); + } } /** @@ -320,10 +323,14 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state) */ void intel_dsb_cleanup(struct intel_crtc_state *crtc_state) { - if (!crtc_state->dsb) - return; + int i; - i915_vma_unpin_and_release(&crtc_state->dsb->vma, I915_VMA_RELEASE_MAP); - kfree(crtc_state->dsb); - crtc_state->dsb = NULL; + for (i = 0; i < MAX_DSB_PER_PIPE; i++) { + if (!crtc_state->dsb[i]) + continue; + + i915_vma_unpin_and_release(&crtc_state->dsb[i]->vma, I915_VMA_RELEASE_MAP); + kfree(crtc_state->dsb[i]); + crtc_state->dsb[i] = NULL; + } } From patchwork Tue Dec 22 06:33:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 11985897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 749BDC433DB for ; Tue, 22 Dec 2020 06:51:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 32A8622B2D for ; Tue, 22 Dec 2020 06:51:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 32A8622B2D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BDCBC6E16D; Tue, 22 Dec 2020 06:51:35 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id BC0566E141 for ; Tue, 22 Dec 2020 06:51:33 +0000 (UTC) IronPort-SDR: sEWqoR1U4hKD4VGRaGLYTb9c0/4CK6D72Gior77jeLsKtf97eZUSRcdIfjY1BfqGtCaFlcBUEr s506exNLaR8Q== X-IronPort-AV: E=McAfee;i="6000,8403,9842"; a="162883460" X-IronPort-AV: E=Sophos;i="5.78,438,1599548400"; d="scan'208";a="162883460" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2020 22:51:33 -0800 IronPort-SDR: ZRpMlj/iWC5OcDQUER7Xxf2ovnXBC+PsJBW9Cnct72mLGwShzc7DV8/HTWecyIl0I1ibU8v6h4 D2gGw8I75M8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,438,1599548400"; d="scan'208";a="356209237" Received: from amanna.iind.intel.com ([10.223.74.76]) by orsmga002.jf.intel.com with ESMTP; 21 Dec 2020 22:51:32 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Dec 2020 12:03:59 +0530 Message-Id: <20201222063400.9509-3-animesh.manna@intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20201222063400.9509-1-animesh.manna@intel.com> References: <20201222063400.9509-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm/i915/dsb: multi dsb instance support in dsb-write() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To support multiple dsb instances per pipe dsb-id is passed as argumnet in dsb-write() which will write into respective dsb cmd-buffer. v1: Initial version. v2: Improved commit description. Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_color.c | 40 +++++++++++++--------- drivers/gpu/drm/i915/display/intel_dsb.c | 10 +++--- drivers/gpu/drm/i915/display/intel_dsb.h | 4 +-- 3 files changed, 31 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 172d398081ee..02f31bcf0d24 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -728,9 +728,12 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; /* Program the max register to clamp values > 1.0. */ - intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16); - intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16); - intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16); + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 0), 1 << 16, + DSB1); + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 1), 1 << 16, + DSB1); + intel_dsb_reg_write(crtc_state, PREC_PAL_EXT_GC_MAX(pipe, 2), 1 << 16, + DSB1); /* * Program the gc max 2 register to clamp values > 1.0. @@ -739,11 +742,11 @@ static void ivb_load_lut_ext_max(const struct intel_crtc_state *crtc_state) */ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 0), - 1 << 16); + 1 << 16, DSB1); intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 1), - 1 << 16); + 1 << 16, DSB1); intel_dsb_reg_write(crtc_state, PREC_PAL_EXT2_GC_MAX(pipe, 2), - 1 << 16); + 1 << 16, DSB1); } } @@ -931,9 +934,12 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state, enum pipe pipe = crtc->pipe; /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */ - intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red); - intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green); - intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue); + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red, + DSB1); + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green, + DSB1); + intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue, + DSB1); } static void @@ -953,15 +959,15 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256). */ intel_dsb_reg_write(crtc_state, PREC_PAL_MULTI_SEG_INDEX(pipe), - PAL_PREC_AUTO_INCREMENT); + PAL_PREC_AUTO_INCREMENT, DSB1); for (i = 0; i < 9; i++) { const struct drm_color_lut *entry = &lut[i]; intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), - ilk_lut_12p4_ldw(entry)); + ilk_lut_12p4_ldw(entry), DSB1); intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_MULTI_SEG_DATA(pipe), - ilk_lut_12p4_udw(entry)); + ilk_lut_12p4_udw(entry), DSB1); } } @@ -986,13 +992,13 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) * seg2[0] being unused by the hardware. */ intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe), - PAL_PREC_AUTO_INCREMENT); + PAL_PREC_AUTO_INCREMENT, DSB1); for (i = 1; i < 257; i++) { entry = &lut[i * 8]; intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), - ilk_lut_12p4_ldw(entry)); + ilk_lut_12p4_ldw(entry), DSB1); intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), - ilk_lut_12p4_udw(entry)); + ilk_lut_12p4_udw(entry), DSB1); } /* @@ -1010,9 +1016,9 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) for (i = 0; i < 256; i++) { entry = &lut[i * 8 * 128]; intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), - ilk_lut_12p4_ldw(entry)); + ilk_lut_12p4_ldw(entry), DSB1); intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe), - ilk_lut_12p4_udw(entry)); + ilk_lut_12p4_udw(entry), DSB1); } /* The last entry in the LUT is to be programmed in GCMAX */ diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index cef1015cc04f..2a9df1d7cbc5 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -82,6 +82,7 @@ static bool intel_dsb_disable_engine(struct drm_i915_private *i915, * @crtc_state: intel_crtc_state structure * @reg: register address. * @val: value. + * @id: dsb id. * * This function is used for writing register-value pair in command * buffer of DSB for auto-increment register. During command buffer overflow, @@ -90,9 +91,9 @@ static bool intel_dsb_disable_engine(struct drm_i915_private *i915, */ void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, - i915_reg_t reg, u32 val) + i915_reg_t reg, u32 val, enum dsb_id id) { - struct intel_dsb *dsb = crtc_state->dsb[0]; + struct intel_dsb *dsb = crtc_state->dsb[id]; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 *buf; @@ -160,6 +161,7 @@ void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, * @crtc_state: intel_crtc_state structure * @reg: register address. * @val: value. + * @id: dsb id. * * This function is used for writing register-value pair in command * buffer of DSB. During command buffer overflow, a warning is thrown @@ -167,14 +169,14 @@ void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, * through mmio write. */ void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, - i915_reg_t reg, u32 val) + i915_reg_t reg, u32 val, enum dsb_id id) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_dsb *dsb; u32 *buf; - dsb = crtc_state->dsb[0]; + dsb = crtc_state->dsb[id]; if (!dsb) { intel_de_write(dev_priv, reg, val); return; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 654a11f24b80..0040941d6a56 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -43,9 +43,9 @@ struct intel_dsb { void intel_dsb_prepare(struct intel_crtc_state *crtc_state); void intel_dsb_cleanup(struct intel_crtc_state *crtc_state); void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, - i915_reg_t reg, u32 val); + i915_reg_t reg, u32 val, enum dsb_id id); void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, - i915_reg_t reg, u32 val); + i915_reg_t reg, u32 val, enum dsb_id id); void intel_dsb_commit(const struct intel_crtc_state *crtc_state); #endif From patchwork Tue Dec 22 06:34:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 11985899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2A09C433DB for ; Tue, 22 Dec 2020 06:51:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 879F822B2D for ; Tue, 22 Dec 2020 06:51:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 879F822B2D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F5BC6E150; Tue, 22 Dec 2020 06:51:41 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8EE4F6E150 for ; Tue, 22 Dec 2020 06:51:35 +0000 (UTC) IronPort-SDR: bJa/a2z2E1FRQI7E85yw7rp0nXLURsoQYHPv7tTx274gGr0u0iGZvfzSavpoJHEKAxv33TRApb UMIfcgFwvozA== X-IronPort-AV: E=McAfee;i="6000,8403,9842"; a="162883463" X-IronPort-AV: E=Sophos;i="5.78,438,1599548400"; d="scan'208";a="162883463" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2020 22:51:35 -0800 IronPort-SDR: +4QnPwL3tNYRiNcrl/TRtwEfK9zvqe05adlH9CbMq0OtNiNpqQ3dUWdgnvDZZrvj6nrYya7Q9Q FFD0Wr9Q+vNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,438,1599548400"; d="scan'208";a="356209252" Received: from amanna.iind.intel.com ([10.223.74.76]) by orsmga002.jf.intel.com with ESMTP; 21 Dec 2020 22:51:34 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Dec 2020 12:04:00 +0530 Message-Id: <20201222063400.9509-4-animesh.manna@intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20201222063400.9509-1-animesh.manna@intel.com> References: <20201222063400.9509-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/dsb: multi dsb instance support in dsb-commit() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To support multiple dsb instances per pipe dsb-id is passed as argumnet in dsb-commit() and respective cmd-buffer will be updated in actual hardware. v1: Initial version. v2: Improved commit description. Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_dsb.c | 74 +++++++++++++----------- 1 file changed, 39 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 2a9df1d7cbc5..be301cb292dc 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -210,46 +210,50 @@ void intel_dsb_commit(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(dev); enum pipe pipe = crtc->pipe; u32 tail; + int i; - if (!(dsb && dsb->free_pos)) - return; + for (i = 0; i < MAX_DSB_PER_PIPE; i++) { + dsb = crtc_state->dsb[i]; + if (!(dsb && dsb->free_pos)) + continue; - if (!intel_dsb_enable_engine(dev_priv, pipe, dsb->id)) - goto reset; + if (!intel_dsb_enable_engine(dev_priv, pipe, dsb->id)) + goto reset; - if (is_dsb_busy(dev_priv, pipe, dsb->id)) { - drm_err(&dev_priv->drm, - "HEAD_PTR write failed - dsb engine is busy.\n"); - goto reset; - } - intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), - i915_ggtt_offset(dsb->vma)); - - tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES); - if (tail > dsb->free_pos * 4) - memset(&dsb->cmd_buf[dsb->free_pos], 0, - (tail - dsb->free_pos * 4)); - - if (is_dsb_busy(dev_priv, pipe, dsb->id)) { - drm_err(&dev_priv->drm, - "TAIL_PTR write failed - dsb engine is busy.\n"); - goto reset; - } - drm_dbg_kms(&dev_priv->drm, - "DSB execution started - head 0x%x, tail 0x%x\n", - i915_ggtt_offset(dsb->vma), tail); - intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), - i915_ggtt_offset(dsb->vma) + tail); - if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) { - drm_err(&dev_priv->drm, - "Timed out waiting for DSB workload completion.\n"); - goto reset; - } + if (is_dsb_busy(dev_priv, pipe, dsb->id)) { + drm_err(&dev_priv->drm, + "HEAD_PTR write failed - dsb engine is busy\n"); + goto reset; + } + intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), + i915_ggtt_offset(dsb->vma)); + + tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES); + if (tail > dsb->free_pos * 4) + memset(&dsb->cmd_buf[dsb->free_pos], 0, + (tail - dsb->free_pos * 4)); + + if (is_dsb_busy(dev_priv, pipe, dsb->id)) { + drm_err(&dev_priv->drm, + "TAIL_PTR write failed - dsb engine is busy\n"); + goto reset; + } + drm_dbg_kms(&dev_priv->drm, + "DSB execution started - head 0x%x, tail 0x%x\n", + i915_ggtt_offset(dsb->vma), tail); + intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), + i915_ggtt_offset(dsb->vma) + tail); + if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) { + drm_err(&dev_priv->drm, + "Timed out waiting for DSB workload completion\n"); + goto reset; + } reset: - dsb->free_pos = 0; - dsb->ins_start_offset = 0; - intel_dsb_disable_engine(dev_priv, pipe, dsb->id); + dsb->free_pos = 0; + dsb->ins_start_offset = 0; + intel_dsb_disable_engine(dev_priv, pipe, dsb->id); + } } /**