From patchwork Sun Dec 27 14:56:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jiaqingtong97@163.com X-Patchwork-Id: 11990665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAFBEC433E0 for ; Sun, 27 Dec 2020 17:34:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 802CD206DC for ; Sun, 27 Dec 2020 17:34:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726087AbgL0Res (ORCPT ); Sun, 27 Dec 2020 12:34:48 -0500 Received: from mail-m971.mail.163.com ([123.126.97.1]:52324 "EHLO mail-m971.mail.163.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726065AbgL0Rer (ORCPT ); Sun, 27 Dec 2020 12:34:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=9UBbU UXlO3sE92vjyKPWDgov2Z/zk5/Sljqb/Cc2CYs=; b=gowCZMtaoFW8tr9uccXd2 l4rcAvWq0O0wUL2eROnaYZS2JnhVMj1vbr5NwkTMfYTSRXLs8ZHtOIeW2vsGetmz b2WFah4Lid1g+7P7WdAyUmFXyx816NqATUEukxKVGLKZkDwmeJpGxo7E6TGg3M3b ugoXjBOuE9wZga4e76wB6U= Received: from JiadeiMac-Pro.lan (unknown [112.64.60.201]) by smtp1 (Coremail) with SMTP id GdxpCgD3MCjKoOhfoDD_Ag--.52426S2; Sun, 27 Dec 2020 22:57:15 +0800 (CST) From: jiaqingtong97@163.com To: tsbogend@alpha.franken.de, mark.tomlinson@alliedtelesis.co.nz, paulburton@kernel.org, jiaxun.yang@flygoat.com Cc: linux-mips@vger.kernel.org, Jia Qingtong Subject: [PATCH v2] MIPS: OCTEON: Add WAR_OCTEON_BARRIER workaround config Date: Sun, 27 Dec 2020 22:56:51 +0800 Message-Id: <20201227145651.4513-1-jiaqingtong97@163.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201219153957.GB5012@alpha.franken.de> References: <20201219153957.GB5012@alpha.franken.de> MIME-Version: 1.0 X-CM-TRANSID: GdxpCgD3MCjKoOhfoDD_Ag--.52426S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7tF4ftw1kWw1fWF1DJw4DCFg_yoW8AF1kpa yqkw4kGr4kWFyfJ39xC3s7W3s3Jan5Grya9Fyj9r1jq3W5uasrZrZ3tr98t348Ww4DAayr uF93W3WUJFn7AFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jP9N3UUUUU= X-Originating-IP: [112.64.60.201] X-CM-SenderInfo: 5mld1xpqjw00rjzxqiywtou0bp/1tbiKAsIb17WDo2-4QAAsR Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Jia Qingtong Some Cavium Octeon CPUs(Octeon & Octeon Plus) suffer from a bug that causes a single wmb ordering barrier to be ineffective, requiring the use of 2 in sequence to provide an effective barrier. This patch make workaroud as a config for CPUs who didn't suffer from that bug. Signed-off-by: Jia Qingtong --- arch/mips/cavium-octeon/Kconfig | 9 +++++++++ arch/mips/include/asm/sync.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 4984e462be30..0dc910683df9 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -1,6 +1,15 @@ # SPDX-License-Identifier: GPL-2.0 if CPU_CAVIUM_OCTEON +config WAR_OCTEON_BARRIER + bool "Enable Octeon & Octeon Plus barrier workaround" + default "y" + help + Some Cavium Octeon CPUs(Octeon & Octeon Plus) + suffer from a bug that causes a single wmb ordering barrier + to be ineffective, requiring the use of 2 in sequence + to provide an effective barrier. + config CAVIUM_CN63XXP1 bool "Enable CN63XXP1 errata workarounds" default "n" diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h index aabd097933fe..b24a2f82ef19 100644 --- a/arch/mips/include/asm/sync.h +++ b/arch/mips/include/asm/sync.h @@ -158,7 +158,7 @@ * Note that this expression is evaluated by the assembler (not the compiler), * and that the assembler evaluates '==' as 0 or -1, not 0 or 1. */ -#ifdef CONFIG_CPU_CAVIUM_OCTEON +#ifdef CONFIG_WAR_OCTEON_BARRIER # define __SYNC_rpt(type) (1 - (type == __SYNC_wmb)) #else # define __SYNC_rpt(type) 1