From patchwork Sat Jan 2 20:59:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11995285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 890CEC433E0 for ; Sat, 2 Jan 2021 21:01:20 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 33F142075F for ; Sat, 2 Jan 2021 21:01:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 33F142075F Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=googlemail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=I6NAQRrt66QPsfKZyZKbEtaKEr6O/We55OVB8quRtMg=; b=xoDap2l+8EDLNp03+3CYKbHMi mj21vVV/mjSrV8Ll2YUYv5izI9UzonKag4UDhG3TLJXWCv2kqIJDHLvPc0dF3BnliA2kH76u0GQme 5GtBDdlW/8iTkwKmx72R3zalO0PCMmgwb3hPoHhu9ueJTQKs5Q9zP8sp/lKCO21KCnXDfcOcmd0v4 RewwxWw5JjYCcRAZwFehnuvNJ2tVhBZ0CJvpBHwT+U116kBsfRkJz1HaU8gqxJJWdMxGvWD0jVuxJ 20V8F+wrtpFoDdzy0zAOgk/kEfcngllOW76Wxr1Djc5d2dRN9nv4nyxEWo/Z+mU3lEGI/mSczfj3f bNEp2D/vQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kvnzf-0002wy-Iv; Sat, 02 Jan 2021 20:59:23 +0000 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kvnza-0002uP-3e; Sat, 02 Jan 2021 20:59:19 +0000 Received: by mail-ed1-x531.google.com with SMTP id y24so22944588edt.10; Sat, 02 Jan 2021 12:59:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ywgU0RqknLqPrZiMHs7nQjxQoQ/2d1Llugr9rRHrcUE=; b=nTzXSsLMgjBkPOAji4+eKD2k58N7k6whoOZN/Tj/TQWrTcRDD4obYaEI30ntGHCnNO 0W1mCPQYL8N0tDfY0DwySC1trF4Sf+Q3kAa0C5rWnWOHs65XBuOjz94R7I0i9wOdNxHL 9FbZAttDo2a9kydgIuTwxQn8IXb5Be2HkAqfeiB9sFYXw003GpRKmGJ5ZouXAFJ1VWDk LlMnw98aZ1AY/cLqbh15fYBYTPgVnmPL6VHuTRsjdvnRHaqW8YTkPdZ6p0pEZBusRKFV Zt5pbHgIMX7IkkDk6FAXBaqEdo5tGK0i+Gxfws85YUdlj9ueFF1WcXxfu2sFYQkZLqAv kRuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ywgU0RqknLqPrZiMHs7nQjxQoQ/2d1Llugr9rRHrcUE=; b=tk7xb2EGeVQrPEKA7UOogdcMsJgEcthRSKupQqedb4HJ+Wz+ZMQz30Flzz4OuKolrv VW/r+DdRNoKzi3F/l0zFqmzBuDzWDzckftN0iuKIoNOEN3ca0On/NZCHiA412aa74BQr LrNroEE3EIzL0ABpV06Jo4VpCFV3S8mHPGhESzD2eIdhjDyCR5dHKmuWLMRCLGbaac47 c7+mQJ+jXzTxwxG36j/LOUXpb3T3t9mKRU6Mwpf0QziFSmZ/OS0IGivN9VxX2/n2xMcz LDVBNDrlDlF0pOSV54EPhBcFTnG2uM4SZxKqmqPzfIjmJjSs2qwCwN6Ys6rJuro0AyNw 4Rog== X-Gm-Message-State: AOAM531FSufQLJZKK/gLHB9hRaPxFElOtbojRCUFZnEI5UWCtlmJNzbZ mtwvpOsm3yhKwXntGjKVCL4= X-Google-Smtp-Source: ABdhPJw3+ko0VZX14qsFf/BNsYrFexeTS/1D1ZEDnK/05bBIvDZ7G0qwLteAixk33fJQF6HJwa/0Sg== X-Received: by 2002:aa7:d494:: with SMTP id b20mr66478539edr.330.1609621155953; Sat, 02 Jan 2021 12:59:15 -0800 (PST) Received: from localhost.localdomain (p200300f13724fd00428d5cfffeb99db8.dip0.t-ipconnect.de. [2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id v18sm41420617edx.30.2021.01.02.12.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Jan 2021 12:59:15 -0800 (PST) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Subject: [PATCH v2 1/5] dt-bindings: sram: Add compatible strings for the Meson AO ARC SRAM Date: Sat, 2 Jan 2021 21:59:00 +0100 Message-Id: <20210102205904.2691120-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210102205904.2691120-1-martin.blumenstingl@googlemail.com> References: <20210102205904.2691120-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210102_155918_189597_E4528552 X-CRM114-Status: GOOD ( 11.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ohad@wizery.com, devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Amlogic Meson8, Meson8b and Meson8m2 SoCs embed an ARC EM4 core typically used for managing system suspend. A section of the SoCs SRAM is mapped as memory for this ARC core. Add new compatible strings for the SRAM section for the ARC core memory. Signed-off-by: Martin Blumenstingl Acked-by: Rob Herring --- Documentation/devicetree/bindings/sram/sram.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 19d116ff9ddc..6d65771e979c 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -72,6 +72,8 @@ patternProperties: - allwinner,sun4i-a10-sram-d - allwinner,sun9i-a80-smp-sram - allwinner,sun50i-a64-sram-c + - amlogic,meson8-ao-arc-sram + - amlogic,meson8b-ao-arc-sram - amlogic,meson8-smp-sram - amlogic,meson8b-smp-sram - amlogic,meson-gxbb-scp-shmem From patchwork Sat Jan 2 20:59:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11995293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D925BC433E0 for ; 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[2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id v18sm41420617edx.30.2021.01.02.12.59.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Jan 2021 12:59:16 -0800 (PST) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Subject: [PATCH v2 2/5] dt-bindings: Amlogic: add the documentation for the SECBUS2 registers Date: Sat, 2 Jan 2021 21:59:01 +0100 Message-Id: <20210102205904.2691120-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210102205904.2691120-1-martin.blumenstingl@googlemail.com> References: <20210102205904.2691120-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210102_155918_148823_C9770533 X-CRM114-Status: GOOD ( 14.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ohad@wizery.com, devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which contains registers for various IP blocks such as pin-controller bits for the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits. The registers can be accessed directly when not running in "secure mode". When "secure mode" is enabled then these registers have to be accessed through secure monitor calls. So far these SoCs are always known to boot in "non-secure mode". Add a binding documentation using syscon (as these registers are shared across different IPs) for the SECBUS2 registers. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring --- .../arm/amlogic/amlogic,meson-mx-secbus2.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml new file mode 100644 index 000000000000..eee7cda9f91b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface + +maintainers: + - Martin Blumenstingl + +description: | + The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which + contains registers for various IP blocks such as pin-controller bits for + the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits. + The registers can be accessed directly when not running in "secure mode". + When "secure mode" is enabled then these registers have to be accessed + through secure monitor calls. + +properties: + compatible: + items: + - enum: + - amlogic,meson8-secbus2 + - amlogic,meson8b-secbus2 + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + secbus2: system-controller@4000 { + compatible = "amlogic,meson8-secbus2", "syscon"; + reg = <0x4000 0x2000>; + }; From patchwork Sat Jan 2 20:59:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11995289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D00E3C433E9 for ; Sat, 2 Jan 2021 21:01:21 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 899D12075F for ; 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[2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id v18sm41420617edx.30.2021.01.02.12.59.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Jan 2021 12:59:17 -0800 (PST) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Subject: [PATCH v2 3/5] dt-bindings: remoteproc: Add the documentation for Meson AO ARC rproc Date: Sat, 2 Jan 2021 21:59:02 +0100 Message-Id: <20210102205904.2691120-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210102205904.2691120-1-martin.blumenstingl@googlemail.com> References: <20210102205904.2691120-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210102_155919_026930_F9728940 X-CRM114-Status: GOOD ( 15.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ohad@wizery.com, devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC EM4 controller for always-on operations, typically used for managing system suspend. Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring --- .../remoteproc/amlogic,meson-mx-ao-arc.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml new file mode 100644 index 000000000000..d892d29a656b --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/remoteproc/amlogic,meson-mx-ao-arc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson AO ARC Remote Processor bindings + +description: + Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC core + controller for always-on operations, typically used for managing + system suspend. Meson6 and older use a ARC core based on the ARCv1 + ISA, while Meson8, Meson8b and Meson8m2 use an ARC EM4 (ARCv2 ISA) + core. + +maintainers: + - Martin Blumenstingl + +properties: + compatible: + items: + - enum: + - amlogic,meson8-ao-arc + - amlogic,meson8b-ao-arc + - const: amlogic,meson-mx-ao-arc + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + The name of the firmware which should be loaded for this remote + processor. + + reg: + description: + Address ranges of the remap and CPU control addresses for the + remote processor. + minItems: 2 + + reg-names: + items: + - const: remap + - const: cpu + + resets: + minItems: 1 + + clocks: + minItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandles to a reserved SRAM region which is used as the memory of + the ARC core. The region should be defined as child nodes of the + AHB SRAM node as per the generic bindings in + Documentation/devicetree/bindings/sram/sram.yaml + + amlogic,secbus2: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to the SECBUS2 region which contains some configuration + bits of this remote processor + +required: + - compatible + - reg + - reg-names + - resets + - clocks + - sram + - amlogic,secbus2 + +additionalProperties: false + +examples: + - | + remoteproc@1c { + compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; + reg = <0x1c 0x8>, <0x38 0x8>; + reg-names = "remap", "cpu"; + resets = <&media_cpu_reset>; + clocks = <&media_cpu_clock>; + sram = <&ahb_sram_ao_arc>; + amlogic,secbus2 = <&secbus2>; + }; + +... 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[2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id v18sm41420617edx.30.2021.01.02.12.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Jan 2021 12:59:18 -0800 (PST) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Subject: [PATCH v2 4/5] remoteproc: meson-mx-ao-arc: Add a driver for the AO ARC remote procesor Date: Sat, 2 Jan 2021 21:59:03 +0100 Message-Id: <20210102205904.2691120-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210102205904.2691120-1-martin.blumenstingl@googlemail.com> References: <20210102205904.2691120-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210102_155920_163269_57243C47 X-CRM114-Status: GOOD ( 28.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ohad@wizery.com, devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Amlogic Meson6, Meson8, Meson8b and Meson8m2 embed an ARC core in the Always-On (AO) power-domain. This is typically used for waking up the ARM cores after system suspend. The configuration is spread across three different registers: - AO_REMAP_REG0 which must be programmed to zero, it's actual purpose is unknown. There is a second remap register which is not used in the vendor kernel (which served as reference for this driver). - AO_CPU_CNTL is used to start and stop the ARC core. - AO_SECURE_REG0 in the SECBUS2 register area with unknown purpose. To boot the ARC core we also need to enable it's gate clock and trigger a reset. The actual code for this ARC core can come from an ELF binary, for example by building the Zephyr RTOS for an ARC EM4 core and then taking "zephyr.elf" as firmware. This executable does not have any "rsc table" so we are skipping rproc_elf_load_rsc_table (rproc_ops.parse_fw) and rproc_elf_find_loaded_rsc_table (rproc_ops.find_loaded_rsc_table). Signed-off-by: Martin Blumenstingl --- drivers/remoteproc/Kconfig | 11 ++ drivers/remoteproc/Makefile | 1 + drivers/remoteproc/meson_mx_ao_arc.c | 240 +++++++++++++++++++++++++++ 3 files changed, 252 insertions(+) create mode 100644 drivers/remoteproc/meson_mx_ao_arc.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 9e7efe542f69..0e7fb91635fe 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -125,6 +125,17 @@ config KEYSTONE_REMOTEPROC It's safe to say N here if you're not interested in the Keystone DSPs or just want to use a bare minimum kernel. +config MESON_MX_AO_ARC_REMOTEPROC + tristate "Amlogic Meson6/8/8b/8m2 AO ARC remote processor support" + depends on HAS_IOMEM + depends on (ARM && ARCH_MESON) || COMPILE_TEST + select GENERIC_ALLOCATOR + help + Say m or y here to have support for the AO ARC remote processor + on Amlogic Meson6/Meson8/Meson8b/Meson8m2 SoCs. This is + typically used for system suspend. + If unusre say N. + config PRU_REMOTEPROC tristate "TI PRU remoteproc support" depends on TI_PRUSS diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index bb26c9e4ef9c..ce1abeb30907 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_OMAP_REMOTEPROC) += omap_remoteproc.o obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o +obj-$(CONFIG_MESON_MX_AO_ARC_REMOTEPROC)+= meson_mx_ao_arc.o obj-$(CONFIG_PRU_REMOTEPROC) += pru_rproc.o obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o diff --git a/drivers/remoteproc/meson_mx_ao_arc.c b/drivers/remoteproc/meson_mx_ao_arc.c new file mode 100644 index 000000000000..1deb03ca30f4 --- /dev/null +++ b/drivers/remoteproc/meson_mx_ao_arc.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2020 Martin Blumenstingl + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "remoteproc_internal.h" + +#define AO_REMAP_REG0 0x0 +#define AO_REMAP_REG1 0x4 + +#define AO_CPU_CNTL 0x0 + #define AO_CPU_CNTL_MEM_ADDR_UPPER GENMASK(28, 16) + #define AO_CPU_CNTL_HALT BIT(9) + #define AO_CPU_CNTL_UNKNONWN BIT(8) + #define AO_CPU_CNTL_RUN BIT(0) + +#define AO_CPU_STAT 0x4 + +#define AO_SECURE_REG0 0x0 + #define AO_SECURE_REG0_UNKNOWN GENMASK(23, 8) + +#define MESON_AO_RPROC_SRAM_USABLE_BITS GENMASK(31, 20) +#define MESON_AO_RPROC_MEMORY_OFFSET 0x10000000 + +struct meson_mx_ao_arc_rproc_priv { + void __iomem *remap_base; + void __iomem *cpu_base; + unsigned long sram_va; + phys_addr_t sram_pa; + size_t sram_size; + struct gen_pool *sram_pool; + struct reset_control *arc_reset; + struct clk *arc_pclk; + struct regmap *secbus2_regmap; +}; + +static int meson_mx_ao_arc_rproc_start(struct rproc *rproc) +{ + struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv; + phys_addr_t phys_addr; + int ret; + + ret = clk_prepare_enable(priv->arc_pclk); + if (ret) + return ret; + + writel(0, priv->remap_base + AO_REMAP_REG0); + usleep_range(10, 100); + + regmap_update_bits(priv->secbus2_regmap, AO_SECURE_REG0, + AO_SECURE_REG0_UNKNOWN, 0); + + ret = reset_control_reset(priv->arc_reset); + if (ret) { + clk_disable_unprepare(priv->arc_pclk); + return ret; + } + + usleep_range(10, 100); + + /* convert from 0xd9000000 to 0xc9000000 as the vendor driver does */ + phys_addr = priv->sram_pa - MESON_AO_RPROC_MEMORY_OFFSET; + + writel(FIELD_PREP(AO_CPU_CNTL_MEM_ADDR_UPPER, + FIELD_GET(MESON_AO_RPROC_SRAM_USABLE_BITS, phys_addr)) | + AO_CPU_CNTL_UNKNONWN | AO_CPU_CNTL_RUN, + priv->cpu_base + AO_CPU_CNTL); + usleep_range(20, 200); + + return 0; +} + +static int meson_mx_ao_arc_rproc_stop(struct rproc *rproc) +{ + struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv; + + writel(AO_CPU_CNTL_HALT, priv->cpu_base + AO_CPU_CNTL); + + clk_disable_unprepare(priv->arc_pclk); + + return 0; +} + +static void *meson_mx_ao_arc_rproc_da_to_va(struct rproc *rproc, u64 da, + size_t len) +{ + struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv; + + if ((da + len) >= priv->sram_size) + return NULL; + + return (void *)priv->sram_va + da; +} + +static struct rproc_ops meson_mx_ao_arc_rproc_ops = { + .start = meson_mx_ao_arc_rproc_start, + .stop = meson_mx_ao_arc_rproc_stop, + .da_to_va = meson_mx_ao_arc_rproc_da_to_va, + .get_boot_addr = rproc_elf_get_boot_addr, + .load = rproc_elf_load_segments, + .sanity_check = rproc_elf_sanity_check, +}; + +static int meson_mx_ao_arc_rproc_probe(struct platform_device *pdev) +{ + struct meson_mx_ao_arc_rproc_priv *priv; + struct platform_device *secbus2_pdev; + struct device *dev = &pdev->dev; + const char *fw_name; + struct rproc *rproc; + int ret; + + ret = device_property_read_string(dev, "firmware-name", &fw_name); + if (ret) + fw_name = NULL; + + rproc = devm_rproc_alloc(dev, "meson-mx-ao-arc", + &meson_mx_ao_arc_rproc_ops, fw_name, + sizeof(*priv)); + if (!rproc) + return -ENOMEM; + + rproc->has_iommu = false; + priv = rproc->priv; + + priv->sram_pool = of_gen_pool_get(dev->of_node, "sram", 0); + if (!priv->sram_pool) { + dev_err(dev, "Could not get SRAM pool\n"); + return -ENODEV; + } + + priv->sram_size = gen_pool_avail(priv->sram_pool); + + priv->sram_va = gen_pool_alloc(priv->sram_pool, priv->sram_size); + if (!priv->sram_va) { + dev_err(dev, "Could not alloc memory in SRAM pool\n"); + return -ENOMEM; + } + + priv->sram_pa = gen_pool_virt_to_phys(priv->sram_pool, priv->sram_va); + if (priv->sram_pa & ~MESON_AO_RPROC_SRAM_USABLE_BITS) { + dev_err(dev, "SRAM address contains unusable bits\n"); + ret = -EINVAL; + goto err_free_genpool; + } + + priv->secbus2_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "amlogic,secbus2"); + if (IS_ERR(priv->secbus2_regmap)) { + dev_err(dev, "Failed to find SECBUS2 regmap\n"); + ret = PTR_ERR(priv->secbus2_regmap); + goto err_free_genpool; + } + + priv->remap_base = devm_platform_ioremap_resource_byname(pdev, "remap"); + if (IS_ERR(priv->remap_base)) { + ret = PTR_ERR(priv->remap_base); + goto err_free_genpool; + } + + priv->cpu_base = devm_platform_ioremap_resource_byname(pdev, "cpu"); + if (IS_ERR(priv->cpu_base)) { + ret = PTR_ERR(priv->cpu_base); + goto err_free_genpool; + } + + priv->arc_reset = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(priv->arc_reset)) { + dev_err(dev, "Failed to get ARC reset\n"); + ret = PTR_ERR(priv->arc_reset); + goto err_free_genpool; + } + + priv->arc_pclk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->arc_pclk)) { + dev_err(dev, "Failed to get the ARC PCLK\n"); + ret = PTR_ERR(priv->arc_pclk); + goto err_free_genpool; + } + + platform_set_drvdata(pdev, rproc); + + ret = rproc_add(rproc); + if (ret) + goto err_free_genpool; + + return 0; + +err_free_genpool: + gen_pool_free(priv->sram_pool, priv->sram_va, priv->sram_size); + return ret; +} + +static int meson_mx_ao_arc_rproc_remove(struct platform_device *pdev) +{ + struct rproc *rproc = platform_get_drvdata(pdev); + struct meson_mx_ao_arc_rproc_priv *priv = rproc->priv; + + rproc_del(rproc); + gen_pool_free(priv->sram_pool, priv->sram_va, priv->sram_size); + + return 0; +} + +static const struct of_device_id meson_mx_ao_arc_rproc_match[] = { + { .compatible = "amlogic,meson8-ao-arc" }, + { .compatible = "amlogic,meson8b-ao-arc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, meson_mx_ao_arc_rproc_match); + +static struct platform_driver meson_mx_ao_arc_rproc_driver = { + .probe = meson_mx_ao_arc_rproc_probe, + .remove = meson_mx_ao_arc_rproc_remove, + .driver = { + .name = "meson-mx-ao-arc-rproc", + .of_match_table = of_match_ptr(meson_mx_ao_arc_rproc_match), + }, +}; +module_platform_driver(meson_mx_ao_arc_rproc_driver); + +MODULE_DESCRIPTION("Amlogic Meson6/8/8b/8m2 AO ARC remote processor driver"); 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[2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id v18sm41420617edx.30.2021.01.02.12.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Jan 2021 12:59:19 -0800 (PST) From: Martin Blumenstingl To: linux-remoteproc@vger.kernel.org, linux-amlogic@lists.infradead.org Subject: [PATCH v2 5/5] ARM: dts: meson: add the AO ARC remote processor Date: Sat, 2 Jan 2021 21:59:04 +0100 Message-Id: <20210102205904.2691120-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210102205904.2691120-1-martin.blumenstingl@googlemail.com> References: <20210102205904.2691120-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210102_155921_288005_997895E1 X-CRM114-Status: GOOD ( 13.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ohad@wizery.com, devicetree@vger.kernel.org, Martin Blumenstingl , linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The 32-bit Amlogic Meson SoCs embed an ARC processor in the Always-On power domain which is typically used for managing system suspend. The memory for this ARC core is taken from the AHB SRAM area. Depending on the actual SoC a different ARC core is used: - Meson6 and earlier: some ARCv1 ISA based core (probably an ARC625) - Meson8 and later: an ARC EM4 (ARCv2 ISA) based core Add the device-tree node for this remote-processor along with the required SRAM sections, clocks and reset-lines. Also use the SoC-specific compatible string to manage any differences (should they exist). On Meson8, Meson8b and Meson8m2 the "secbus2" IO region is needed as some bits need to be programmed there. Add this IO region for those SoCs as well. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong --- arch/arm/boot/dts/meson.dtsi | 7 +++++++ arch/arm/boot/dts/meson8.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 21 +++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index e0ca5f08d07d..8bae6ed0abb2 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -200,6 +200,13 @@ aobus: aobus@c8100000 { #size-cells = <1>; ranges = <0x0 0xc8100000 0x100000>; + ao_arc_rproc: remoteproc@1c { + compatible= "amlogic,meson-mx-ao-arc"; + reg = <0x1c 0x8>, <0x38 0x8>; + reg-names = "remap", "cpu"; + status = "disabled"; + }; + ir_receiver: ir-receiver@480 { compatible= "amlogic,meson6-ir"; reg = <0x480 0x20>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 420324ea2ad7..157a950a55d3 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -369,6 +369,14 @@ mux { }; }; +&ao_arc_rproc { + compatible= "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; + amlogic,secbus2 = <&secbus2>; + sram = <&ao_arc_sram>; + resets = <&reset RESET_MEDIA_CPU>; + clocks = <&clkc CLKID_AO_MEDIA_CPU>; +}; + &cbus { reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; @@ -496,6 +504,12 @@ mux { }; &ahb_sram { + ao_arc_sram: ao-arc-sram@0 { + compatible = "amlogic,meson8-ao-arc-sram"; + reg = <0x0 0x8000>; + pool; + }; + smp-sram@1ff80 { compatible = "amlogic,meson8-smp-sram"; reg = <0x1ff80 0x8>; @@ -631,6 +645,13 @@ &sdhc { clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; }; +&secbus { + secbus2: system-controller@4000 { + compatible = "amlogic,meson8-secbus2", "syscon"; + reg = <0x4000 0x2000>; + }; +}; + &sdio { compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index dbf7963b6c87..c02b03cbcdf4 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -320,6 +320,14 @@ mux { }; }; +&ao_arc_rproc { + compatible= "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; + amlogic,secbus2 = <&secbus2>; + sram = <&ao_arc_sram>; + resets = <&reset RESET_MEDIA_CPU>; + clocks = <&clkc CLKID_AO_MEDIA_CPU>; +}; + &cbus { reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; @@ -464,6 +472,12 @@ mux { }; &ahb_sram { + ao_arc_sram: ao-arc-sram@0 { + compatible = "amlogic,meson8b-ao-arc-sram"; + reg = <0x0 0x8000>; + pool; + }; + smp-sram@1ff80 { compatible = "amlogic,meson8b-smp-sram"; reg = <0x1ff80 0x8>; @@ -628,6 +642,13 @@ &sdhc { clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; }; +&secbus { + secbus2: system-controller@4000 { + compatible = "amlogic,meson8b-secbus2", "syscon"; + reg = <0x4000 0x2000>; + }; +}; + &sdio { compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;