From patchwork Mon Jan 4 13:28:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11996783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9F11C433E0 for ; Mon, 4 Jan 2021 13:30:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70742207AE for ; Mon, 4 Jan 2021 13:30:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726749AbhADN3z (ORCPT ); Mon, 4 Jan 2021 08:29:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725921AbhADN3y (ORCPT ); Mon, 4 Jan 2021 08:29:54 -0500 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F606C061795; Mon, 4 Jan 2021 05:29:14 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id n16so7707281wmc.0; Mon, 04 Jan 2021 05:29:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N0ICd7gjWpI+u44o7fGulyQewlvcHmYQ4mPyDcl0N/Y=; b=KYr5DfgA5liPJkd48Mrj1k+lb8ObI4YW8MoTs/LZJSQY1rQkG5bQuKaPlkHHq/2WdC Uz4QdeAVD43drFI2JM32/IE/V0IgPHiI0yI7H5Nnd2cUk3LiLtB3kYk+dAMNZVErqt0Z WIsDVjV1229ydaJNNxe27vSHnLa6SdUW38jlpTTBm+ElH+mhieunnn3xO5M5oiM0zppP 2fDAYZZPc33b5kH5CbUew073VctIkaL3zwyKY5z00NXmacvlWXkmqSmJAeiIlpOTrTtE Io3rotHVY1oDq0/Bqw7KzUg48kRlw3ToWBgS5mInL0mTVTfsXw9VhyGPdxEqbjvSPBlb gecA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N0ICd7gjWpI+u44o7fGulyQewlvcHmYQ4mPyDcl0N/Y=; b=sBbTqJjSrLGT40eOAIWOIKdpZZ44MYWVQV6h35bNMCWU2K4dZY6vbqoObvZxL3ra6e XLskUrwi7Nm5sKLO7Oo8wrzqTejgq/WDa66h/vkca4Hsemh74EiM523oOJhB8pgZmKSL 9lkFPQ6IqC2HaR04jEmhBqhk1IFPkhdvxAp5VwXCynQ2H8t3xagBqYgmlWiTbJBlykok 3G0keKpYHBrSVwGHSwQXW6oKIBXiGQMC/FhWdyXyxoyuq51ynSPkRwbGsXHKNHhLmOE/ zgK8tUjHltCUXR+1D0Vsb3YSVKkc/5Y6i94y4zHfQ0asp91gQmUzhqU9a35IRWskU29P NFIA== X-Gm-Message-State: AOAM532sZJ+QjDubQ88cOx4xPepGzTvgfamxsTuk5qlU/4vMaO8UiCUd yM3DISKWrDwO2cBUTUk5mWY= X-Google-Smtp-Source: ABdhPJywuE2u9mR3LAhtBrTJHq+1D8WBmP3LHVUQJhGBFbugfODpsKR6wzD1kLMNzPlpsdtU8xmBMw== X-Received: by 2002:a1c:ba07:: with SMTP id k7mr27284102wmf.34.1609766952936; Mon, 04 Jan 2021 05:29:12 -0800 (PST) Received: from localhost.localdomain (p200300f13724fd00428d5cfffeb99db8.dip0.t-ipconnect.de. [2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c4sm99916521wrw.72.2021.01.04.05.29.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 05:29:12 -0800 (PST) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 1/5] clk: meson: meson8b: don't use MPLL1 as parent of vclk_in_sel Date: Mon, 4 Jan 2021 14:28:02 +0100 Message-Id: <20210104132806.720558-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> References: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org MPLL1 is needed for audio output. Drop it from the vclk_in_sel parent list so we only use the (mutable) vid_pll_final_div tree or one of the (fixed) FCLK_DIV{3,4,5} clocks. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index a844d35b553a..f8bd211db720 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1154,6 +1154,10 @@ static struct clk_regmap meson8b_vid_pll_final_div = { }, }; +/* + * parent 0x6 is meson8b_mpll1 but we don't use it here because it's reserved + * for the audio outputs. + */ static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { &meson8b_vid_pll_final_div.hw, &meson8b_fclk_div4.hw, @@ -1161,7 +1165,6 @@ static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { &meson8b_fclk_div5.hw, &meson8b_vid_pll_final_div.hw, &meson8b_fclk_div7.hw, - &meson8b_mpll1.hw, }; static struct clk_regmap meson8b_vclk_in_sel = { From patchwork Mon Jan 4 13:28:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11996781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B28E2C433E6 for ; Mon, 4 Jan 2021 13:30:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 86C8E207B1 for ; Mon, 4 Jan 2021 13:30:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726465AbhADNaB (ORCPT ); Mon, 4 Jan 2021 08:30:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726098AbhADN34 (ORCPT ); Mon, 4 Jan 2021 08:29:56 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7436FC061796; Mon, 4 Jan 2021 05:29:15 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id y17so32160059wrr.10; Mon, 04 Jan 2021 05:29:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ju+fvznWpdnqKgL0XY4kkDus/LAK39t8IpQPOIIruIQ=; b=McBUAzMdLiwYXD5jLCbq0wTAXfCoJ093gSi/QpaxlQr0YZKpvEOIWm95LBuOwPAWMo cFTd/0EBuKZP2EKuzGxry+pOeCmeXVoqYjwImBgDg7+lAdgeL6ZFqICN1eoNwbwIASVa yRQWBi6E5ghBLs6J81QGYsdYfteZGCY5KAjMmeHseB8hjVqYxWEgDCq5OYdrNY3/Gmfg YM2QkFqj4c2qHqnr7Pg2/N70/kffN/Uv3LaA/pfsFVVD+XsQgDXcZ+BECc8UWUw/fFS9 5D/qd3KjxpYfMn6qG4zl7o9zcfF1pS8K6EXYt32LNIuCNZ6ssIIXKFLiTvj76STyxO3R j8QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ju+fvznWpdnqKgL0XY4kkDus/LAK39t8IpQPOIIruIQ=; b=toPu6+l+RFEy07RDReqgGhbyTdIiWhT8e+05aLgwAycNPB2UWfJHi2OAqiXS/a0fAi lrQnktz2T2NvXTFxDYTefWnfcGCRgmEK4rSow3WtqVDM89GYJoqtLX03QbPyY4kDUEwy U6EBZpUBTkGAskmzRD+5Y7CI7hejjHa7+p2KXuU9ToeMyA0eAyBw9ojz/m/wQjnnrZP8 wmmoSkVdGrN5tOn+z8cehrtZiQl3uFT1ipYaFutdlwIkgj7TkCrjgbjaonpJxtEPgaL0 1H2YjsrnwFxtMa91/Vtpxj71O4utkHHd78B+gjVvGzd7Gn3CMoe8eG/EB7HbGk+tQWHx Y6Nw== X-Gm-Message-State: AOAM533lzXpFEdVBWjCVBD/S/6Z26oBPgheESWL0Ek7UJLIcjDOK/uAa X3hgU+Sw3fM3DaI/HPbimtg= X-Google-Smtp-Source: ABdhPJy587NnvO7AefdsF/KjjG1iHKv9GXok92rFrI/AXc+PCpiFAKZ+4KV++7y69fgEPyBWbaMgNQ== X-Received: by 2002:adf:fbc5:: with SMTP id d5mr79255592wrs.82.1609766953904; Mon, 04 Jan 2021 05:29:13 -0800 (PST) Received: from localhost.localdomain (p200300f13724fd00428d5cfffeb99db8.dip0.t-ipconnect.de. [2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c4sm99916521wrw.72.2021.01.04.05.29.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 05:29:13 -0800 (PST) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 2/5] clk: meson: meson8b: define the rate range for the hdmi_pll_dco clock Date: Mon, 4 Jan 2021 14:28:03 +0100 Message-Id: <20210104132806.720558-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> References: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org According to the public S805 datasheet the HDMI PLL VCO frequency has to be between 1.2GHz and 3.0GHz. Add this range in our driver so we won't get too low (which means the PLL won't lock) or too high. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index f8bd211db720..16ab595ab1a4 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3781,6 +3781,11 @@ static void __init meson8b_clkc_init_common(struct device_node *np, return; } + /* The HDMI PLL VCO is limited to 1.2G~3.0GHz */ + clk_hw_set_rate_range(clk_hw_onecell_data->hws[CLKID_HDMI_PLL_DCO], + 1200 * 1000UL * 1000UL, + 3000 * 1000UL * 1000UL); + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_onecell_data); if (ret) From patchwork Mon Jan 4 13:28:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11996779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A03AC43381 for ; Mon, 4 Jan 2021 13:30:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C315F207AE for ; Mon, 4 Jan 2021 13:30:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726657AbhADN35 (ORCPT ); Mon, 4 Jan 2021 08:29:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726969AbhADN34 (ORCPT ); Mon, 4 Jan 2021 08:29:56 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07C01C061798; Mon, 4 Jan 2021 05:29:16 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id k10so18468321wmi.3; Mon, 04 Jan 2021 05:29:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yU3i8q3LKfNlAY9hUH3bx+fqfznLSPg6/fe82VNqq7E=; b=AMtwZS2an8TZOKdgEL4gqeYjLriuWPqWRgYbrgrbbN40Xtqp44B8JLfh21SaF1Lvo0 4Mhpet6kOwKrWQy/Qg7Eo6+hfr9ySEzMcWNp4IXPI3oiuWxKEtqYqxlbs+PpEdaZkxPR 7e2f9JwBINuQ7UHZKKsDcMN9NNi/UPfm2aYqcut1mwGu79RYC013VAPScPi9Z+h7iDhF /5YW/WsJtc4efxS6mVyxN+IWNJvc5xl3fGsda90wiG9IG9n/xDfNd+ZB/WPtrNCtywxT EE3njDXCQuXdY9X2Y2Xi/iWy3q0iPT0e734llu2PhPOrG7M1cm2mPFVnwORl7gkD+0+3 kiAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yU3i8q3LKfNlAY9hUH3bx+fqfznLSPg6/fe82VNqq7E=; b=bE9VXxHZxZ0xnWwvHbvfnNQvo+Tb+2+sN0FnF5Gzop8+beCovbiGpxyjEzUSc7QOt0 FC2JVBN+sd1HxnuzKNAaob1gFiSFMMV+uKVQkWiPgdSEpPSSwhdwTzE5SOqdHNZsE/Cx VscIOZI+RPVvPWvRWKN3kJMtWTohbV9eB0Nt2BuvvBlgTeeMFYD2fo8yMzwGJW7lqd3J MRTGB6ClAvkmLwBJVZJ7xQah+cHhIcZcrtTZzPGGvvLUYrLH7Ox0jY0Xf0Lo6kD/L8Ko C3bheX/iGUrMXsispkqLFUjFnsRRUnSsNhkLAAq6FsV0JcdqXfaOMf60WN9hibLFXjap ZQUg== X-Gm-Message-State: AOAM533u+xZxVTu+BgH+xryi4Yo+XmCZldPcPX0HzaRV7Ux7mVxnnqfp D9qW/bcs83HW1GX7qaGPcVQbZT14Qo8= X-Google-Smtp-Source: ABdhPJyVpXksZHxu5YZkIIRBN6VRNV0RdPiMJnbeiaBdMGsMHagAhSvke15twbTrOcTpAUNR0RhXfg== X-Received: by 2002:a1c:741a:: with SMTP id p26mr27847111wmc.47.1609766954825; Mon, 04 Jan 2021 05:29:14 -0800 (PST) Received: from localhost.localdomain (p200300f13724fd00428d5cfffeb99db8.dip0.t-ipconnect.de. [2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c4sm99916521wrw.72.2021.01.04.05.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 05:29:14 -0800 (PST) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 3/5] clk: meson: meson8b: add the video clock divider tables Date: Mon, 4 Jan 2021 14:28:04 +0100 Message-Id: <20210104132806.720558-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> References: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add all known clock dividers from Amlogic's 3.10 vendor kernel. If not stated otherwise the values given in the tables are the only ones used by the 3.10 vendor kernel even if the hardware is capable of other dividers as well: - vid_pll_pre_div can divide by 5 or 6 and if u-boot did not initialize this clock then it divides by 1 by default (only 5 and 6 are used at runtime by the vendor kernel though) - vid_pll_post_div is either 1 or 2 - vid_pll_final_div is either 1, 2 or 4 Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 16ab595ab1a4..1ae771bac4a5 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1084,11 +1084,19 @@ static struct clk_regmap meson8b_vid_pll_in_en = { }, }; +static const struct clk_div_table vid_pll_pre_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 4, .div = 5 }, + { .val = 5, .div = 6 }, + { /* sentinel */ } +}; + static struct clk_regmap meson8b_vid_pll_pre_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_VID_DIVIDER_CNTL, .shift = 4, .width = 3, + .table = vid_pll_pre_div_table, }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_pre_div", @@ -1101,11 +1109,18 @@ static struct clk_regmap meson8b_vid_pll_pre_div = { }, }; +static const struct clk_div_table vid_pll_post_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { /* sentinel */ } +}; + static struct clk_regmap meson8b_vid_pll_post_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_VID_DIVIDER_CNTL, .shift = 12, .width = 3, + .table = vid_pll_post_div_table, }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_post_div", @@ -1137,11 +1152,19 @@ static struct clk_regmap meson8b_vid_pll = { }, }; +static const struct clk_div_table meson8b_vid_pll_final_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 3, .div = 4 }, + { /* sentinel */ } +}; + static struct clk_regmap meson8b_vid_pll_final_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_VID_CLK_DIV, .shift = 0, .width = 8, + .table = meson8b_vid_pll_final_div_table, }, .hw.init = &(struct clk_init_data){ .name = "vid_pll_final_div", From patchwork Mon Jan 4 13:28:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11996785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDB70C433E9 for ; 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[2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c4sm99916521wrw.72.2021.01.04.05.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 05:29:15 -0800 (PST) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 4/5] clk: meson: meson8b: add the HDMI PLL M/N parameters Date: Mon, 4 Jan 2021 14:28:05 +0100 Message-Id: <20210104132806.720558-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> References: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The 3.10 vendor kernel uses only specific HDMI PLL M/N parameter combinations. The PLL won't lock for values smaller than 50 if the internal doubling (which is yet unknown how to use it) is disabled. However, when this doubling is enabled then the values smaller than 50 will lock just fine. The only restriction for values greater than 50 is that the resulting frequency must not exceed the 3.0GHz limit. These values are taken from the endlessm 3.10 kernel which includes some additional M/N combinations for some VESA and 75Hz display modes. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 1ae771bac4a5..8061c11389a9 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -118,6 +118,28 @@ static struct clk_regmap meson8b_fixed_pll = { }, }; +static const struct pll_params_table hdmi_pll_params_table[] = { + PLL_PARAMS(34, 1), + PLL_PARAMS(40, 1), + PLL_PARAMS(42, 1), + PLL_PARAMS(44, 1), + PLL_PARAMS(45, 1), + PLL_PARAMS(49, 1), + PLL_PARAMS(52, 1), + PLL_PARAMS(54, 1), + PLL_PARAMS(56, 1), + PLL_PARAMS(59, 1), + PLL_PARAMS(60, 1), + PLL_PARAMS(61, 1), + PLL_PARAMS(62, 1), + PLL_PARAMS(64, 1), + PLL_PARAMS(66, 1), + PLL_PARAMS(68, 1), + PLL_PARAMS(71, 1), + PLL_PARAMS(82, 1), + { /* sentinel */ } +}; + static struct clk_regmap meson8b_hdmi_pll_dco = { .data = &(struct meson_clk_pll_data){ .en = { @@ -150,6 +172,7 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { .shift = 29, .width = 1, }, + .table = hdmi_pll_params_table, }, .hw.init = &(struct clk_init_data){ /* sometimes also called "HPLL" or "HPLL PLL" */ From patchwork Mon Jan 4 13:28:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11996787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAC72C433DB for ; Mon, 4 Jan 2021 13:30:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A1B3121BE5 for ; Mon, 4 Jan 2021 13:30:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727233AbhADNaF (ORCPT ); Mon, 4 Jan 2021 08:30:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727146AbhADNaF (ORCPT ); Mon, 4 Jan 2021 08:30:05 -0500 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE0CBC06179E; Mon, 4 Jan 2021 05:29:17 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id m5so32122019wrx.9; Mon, 04 Jan 2021 05:29:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W3+FsMu1lbDQIio4q7FHNE16t5hT0RLiFsiQpXFdTmY=; b=sqHg7vBu1o3BP2QxT91WFHqL2g78BS1u6AhfTN1DAkUWS/9BRZESyjjDNMxwDMnVyf 6h6WgnhWuLJysE321kCGfYiOs8lrr21ar0YGTec0NMno+kiNkA/+Pd3gXb6tBEmqtApu n/CuH3vijrjaJTYWLSdTyZrIVYyiQr9u8ev/MQJDalyMxaUhwom/w45rR8ZmXWKmyh/r Q7t4lJiexvj7GMPUg5mJjgwSD+E7nbahizVC/ypNXgl+F31hseHKX5vJsrCehEY+7pr+ TS4fHpgEe5UOhq1/S38ee4GQsvTRIy+RouigMdbidLUKavr640bEEgsyeth/inzAUupV 3zWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W3+FsMu1lbDQIio4q7FHNE16t5hT0RLiFsiQpXFdTmY=; b=p6sYXuEskAfit0JyL6BPNHK1ZvRIb7dE/OLz++25P7aFSv7XcsqrKEDa/meWS/R0Mk jBnkG4y8v6awQIIIZPM9sODBb+XfDllDUJ/Jk0IQgwu6Z5lB2iLj536HFAG/TFsVP5Mi o70xG2NH0LEMG8G7smnJlM2Xfpfhp7X/uEZMpdNiL43ZE4pXs/eA66u+IfGrrgzQBT8e OyQkiJe94H0FT3z9VZUn3x34eLjIX2IOX86L5u11Y30b/k7osA3j+LCuvV1cQskAeX8F QWZBtU6v3/zfn8rMNzBBX3JHxC9BMo6n9UdnWSj3r12rBCWl4xmfWUdDJR/XRuG/YrZ4 a9Cg== X-Gm-Message-State: AOAM530JOxxFOfaQ48lLfH7EKhkh9RlZ1ZiK6FiPJCILt912uvG2Vz8C 7486bG+Xr6aN0t4zWpc+wjw= X-Google-Smtp-Source: ABdhPJwr2OufeuaiYtWIqCrZpai6io4a/I1J3LEe+4dG378mGHo/Cv0TSdnz6GxnNT8ny39ULqVJuQ== X-Received: by 2002:a5d:42d0:: with SMTP id t16mr80111924wrr.230.1609766956653; Mon, 04 Jan 2021 05:29:16 -0800 (PST) Received: from localhost.localdomain (p200300f13724fd00428d5cfffeb99db8.dip0.t-ipconnect.de. [2003:f1:3724:fd00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c4sm99916521wrw.72.2021.01.04.05.29.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 05:29:16 -0800 (PST) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 5/5] clk: meson: meson8b: add the vid_pll_lvds_en gate clock Date: Mon, 4 Jan 2021 14:28:06 +0100 Message-Id: <20210104132806.720558-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> References: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org HHI_VID_DIVIDER_CNTL[11] must be enabled for the video clock tree to work. This bit is described as "LVDS_CLK_EN". It is not 100% clear where this bit has to be placed in the hierarchy. But since the "LVDS_OUT" of the HDMI PLL uses it's own set of registers it's more likely that this "LVDS_CLK_EN" bit actually enables the input of the "hdmi_pll_lvds_out" clock to the "vid_pll_in_sel" tree. Add a gate definition for this bit (which will not be exported) so that the kernel can manage all required bits to enable and disable the video clocks. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 23 ++++++++++++++++++++++- drivers/clk/meson/meson8b.h | 3 ++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 8061c11389a9..450579779de0 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1068,6 +1068,23 @@ static struct clk_regmap meson8b_l2_dram_clk_gate = { }, }; +/* also called LVDS_CLK_EN */ +static struct clk_regmap meson8b_vid_pll_lvds_en = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VID_DIVIDER_CNTL, + .bit_idx = 11, + }, + .hw.init = &(struct clk_init_data){ + .name = "vid_pll_lvds_en", + .ops = &clk_regmap_gate_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &meson8b_hdmi_pll_lvds_out.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap meson8b_vid_pll_in_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_VID_DIVIDER_CNTL, @@ -1084,7 +1101,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { * Meson8m2: vid2_pll */ .parent_hws = (const struct clk_hw *[]) { - &meson8b_hdmi_pll_lvds_out.hw + &meson8b_vid_pll_lvds_en.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2954,6 +2971,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = { [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, [CLKID_CTS_I958] = &meson8b_cts_i958.hw, + [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -3171,6 +3189,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, [CLKID_CTS_I958] = &meson8b_cts_i958.hw, + [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -3390,6 +3409,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = { [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, [CLKID_CTS_I958] = &meson8b_cts_i958.hw, + [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -3588,6 +3608,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_cts_mclk_i958_div, &meson8b_cts_mclk_i958, &meson8b_cts_i958, + &meson8b_vid_pll_lvds_en, }; static const struct meson8b_clk_reset_line { diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index b1a5074cf148..954d97cf6c5a 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -182,8 +182,9 @@ #define CLKID_CTS_MCLK_I958_DIV 211 #define CLKID_VCLK_EN 214 #define CLKID_VCLK2_EN 215 +#define CLKID_VID_PLL_LVDS_EN 216 -#define CLK_NR_CLKS 216 +#define CLK_NR_CLKS 217 /* * include the CLKID and RESETID that have