From patchwork Thu Jan 7 02:30:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Giulio Benetti X-Patchwork-Id: 12002611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CAD5C433E6 for ; Thu, 7 Jan 2021 02:33:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 12B90230FE for ; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxL4Y-0006tS-Nw; Thu, 07 Jan 2021 02:30:46 +0000 Received: from smtpcmd11116.aruba.it ([62.149.156.116]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxL4S-0006rz-4p for linux-arm-kernel@lists.infradead.org; Thu, 07 Jan 2021 02:30:42 +0000 Received: from ubuntu.localdomain ([146.241.198.163]) by Aruba Outgoing Smtp with ESMTPSA id xL4LkiX9OkRIKxL4OkeM1R; Thu, 07 Jan 2021 03:30:36 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1609986636; bh=D5liGHuYvej/2Vs0D+XFNKOleokAhu+S68gzN0VDH9U=; h=From:To:Subject:Date:MIME-Version; b=hdu9yx6qP/HwdpHOlT+OFDXh85hLzsAK6PxWG2FaYWYImwwH2WPzsV6f/fvgyrL0D wTVbQ320IkluX5Zb/CUGxawPt3l8GYFs4KpUpNfA42hFLC0qBjX/m+peXRFwEzhXh2 BHJm33fCOelKRpEm5To6YX+qz0thuQFGQJWEjoat3ZG6Ffa9Mu0ompBcYQeMpq0Mua IFAbaD+lZ3+Y/tWHB1bL5ih+5n9Ei2n76HHN6prqFtmgva82GdOixH0YP3sr2w0/NJ BeWzulF7GXUJV9fRz6+BMEVoPLJ+S1w4wXk18bDQrfIfMeRALWy2vi6TVuDQRqIRJ/ JYnSbIukC4ycA== From: Giulio Benetti To: Maxime Ripard Subject: [PATCH v2 1/2] drm/sun4i: tcon: fix inverted DCLK polarity Date: Thu, 7 Jan 2021 03:30:31 +0100 Message-Id: <20210107023032.560182-2-giulio.benetti@benettiengineering.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107023032.560182-1-giulio.benetti@benettiengineering.com> References: <3685133.SLcexNTYsu@kista> <20210107023032.560182-1-giulio.benetti@benettiengineering.com> MIME-Version: 1.0 X-CMAE-Envelope: MS4wfDPwNH/FgacnF1sUUyqDtIHhJPzsiAY1wJSQ4dQfBax5aRm4Zi6mwJSLaQbhE5CmjOpGqBGUngrQgHGJt0GdkgiakP6SHa4P3QKO4/VWFMK+FjxxhrCv +TXHBPT8FJkM9S9Mfigu6+teKRKk8UOV853vWLWc2fEVeV6moKSNRJUSB0mX0r20rqAmtMIpNY4xiug2H0HEmTnODCUPC41h2wb5FquH1gPAkwYBl7fYWht3 rQQRUUuw+s1g0pfIvALKMbCzbwJTjtWWu+xbgcLQBvQ3kspe5mXfe1EGGIOch4y5DbFPjPeWxqscUc+giXhqlRBdv9zrhEpYOE6mY49x1Xm9fDnBeUTlWNmP Fnn9FbMQEu5cNSmjs43Y9CvD2WqNef8KcOUh9NikYV+7n3+fKjiTMTUYL1QOikDAtB0vpJpqk8DCN14j66gd4+b1mstREjDgfI57bns/zCkA299KW6BsZJpr UmNtk2nAzw8xQ2oeawoite2lq3Y1D6FJ2vlIfS+syyK4k0pQFYlZIITHVylsDH2R97VQ78XNbvv5+21NRTLtoFj90KbJgP6H4HEgHQ== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210106_213040_485844_31EA3E4D X-CRM114-Status: GOOD ( 10.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jernej Skrabec , airlied@linux.ie, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, wens@csie.org, linux-arm-kernel@lists.infradead.org, daniel@ffwll.ch, treding@nvidia.com, Giulio Benetti , Marjan Pascolo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Giulio Benetti During commit 88bc4178568b ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") DRM_BUS_FLAG_* macros have been changed to avoid ambiguity but just because of this ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning _SAMPLE_ not _DRIVE_. This lead to DLCK inversion, so let's swap DCLK phase to fix it. Fixes: 88bc4178568b ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") Signed-off-by: Giulio Benetti --- V1->V2: use Fixes: tag in commit log as suggested by Jernej --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index eaaf5d70e352..52598bb0fb0b 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -585,10 +585,10 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, * and DOTCLOCK drivers. */ if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) - clk_set_phase(tcon->dclk, 240); + clk_set_phase(tcon->dclk, 0); if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) - clk_set_phase(tcon->dclk, 0); + clk_set_phase(tcon->dclk, 240); regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | From patchwork Thu Jan 7 02:30:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Giulio Benetti X-Patchwork-Id: 12002609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B050BC433DB for ; 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d=aruba.it; s=a1; t=1609986637; bh=TsdBOWdkASmq0ug4ZNOIO/B3vCFbiRe6dDUb+k/UQ4E=; h=From:To:Subject:Date:MIME-Version:Content-Type; b=mBzxjfQ2sku8+pC+vRYFNCnlDuKEX6L0W8ywr4Je/g3x17XR0tttSskK7ZBp1kCq6 CgjVsGHs4SLLXdgjxRuBpLvVF7mQAGCyryzuH4HZ1QCMi3obxbiiAkd36l0sWSF+Hr Ulc3WfKZv1/xz+aNru8Oa7ttmBievwGle9YdsVDAQhIW3fE+AQVG4spJ5cxAGYnxpJ dq48yBq9Zb4ywoaZiMqbxSEdBDyErbK2HPxMu1IW2NHchjNH/POyZt/o0+hE6Kiwr1 YcKLSUpAWZMoPTevdbimvG13iDbR9j/995Gl1n9L05sGRoBWCGY3ny1WKqgEUR7fvk ETHLZFan0AGxg== From: Giulio Benetti To: Maxime Ripard Subject: [PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling Date: Thu, 7 Jan 2021 03:30:32 +0100 Message-Id: <20210107023032.560182-3-giulio.benetti@benettiengineering.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210107023032.560182-1-giulio.benetti@benettiengineering.com> References: <3685133.SLcexNTYsu@kista> <20210107023032.560182-1-giulio.benetti@benettiengineering.com> MIME-Version: 1.0 X-CMAE-Envelope: MS4wfAiJ3v+tQqxZQm2L6MNuPUOmMXkyJgh41Q4J9f+nBGG2LDgpAgSXBGMzr/p67u+hk99UQ0KVAMFRmU2+lQK+F9LAuUjNqX725Tk2dJvTsix5pYBTFRFf To80IhdgB2N9FkcNVVTJiuJdzT/hTMScgbVaJkXY2NKXERyqzRDy6Q/7s+tfpVlPiZOflTVlnGJlgiCK19eBHsV7aIUw/zEk+/ICmSx3lkxE6cWUKawo/4Eo NhkbfK39gAjs8kyxhc5HwkiK06fXqu6j6mHV2qCJNwosXad3+/qscyiSh3xk7XC6zQjNRJ0591VK6S9YZWwVZ0dq4D7mW2zgNmXdcthqwuTUey8/r7sreux1 +hvCRL3YyrM7bGGve480+86qMVPZe1s0aYQnUwuN7ySo9jbYUgZTsJESRn5qREVS66SxM4En5p/xyIrUE3pxhcQw5J+Hvo3ebH6HyPcptyH/Jew+xeq+BT/C yFhYF0nIqMkxO1xi2V4rVadpJFMN/h44qf+mPpPo97B6dE5+TX7r4RL/MewgeSCRgSxQSou+pPzr7EY8nRMgq0MNERn+qoUFsd6BEQ== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210106_213040_474203_016EF2C0 X-CRM114-Status: GOOD ( 12.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jernej Skrabec , airlied@linux.ie, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, wens@csie.org, linux-arm-kernel@lists.infradead.org, daniel@ffwll.ch, treding@nvidia.com, Giulio Benetti , Marjan Pascolo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Giulio Benetti It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to invert DCLK polarity and this makes thing really easier than before. So let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to bus_flags the same way is done for all the other signals. Cc: Maxime Ripard Signed-off-by: Giulio Benetti --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +------------------- drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 + 2 files changed, 2 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 52598bb0fb0b..30171ccd87e5 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -569,26 +569,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE; - /* - * On A20 and similar SoCs, the only way to achieve Positive Edge - * (Rising Edge), is setting dclk clock phase to 2/3(240°). - * By default TCON works in Negative Edge(Falling Edge), - * this is why phase is set to 0 in that case. - * Unfortunately there's no way to logically invert dclk through - * IO_POL register. - * The only acceptable way to work, triple checked with scope, - * is using clock phase set to 0° for Negative Edge and set to 240° - * for Positive Edge. - * On A33 and similar SoCs there would be a 90° phase option, - * but it divides also dclk by 2. - * Following code is a way to avoid quirks all around TCON - * and DOTCLOCK drivers. - */ if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) - clk_set_phase(tcon->dclk, 0); - - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) - clk_set_phase(tcon->dclk, 240); + val |= SUN4I_TCON0_IO_POL_DCLK_POSITIVE; regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index cfbf4e6c1679..0ce71d10a31b 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -113,6 +113,7 @@ #define SUN4I_TCON0_IO_POL_REG 0x88 #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28) #define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27) +#define SUN4I_TCON0_IO_POL_DCLK_POSITIVE BIT(26) #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25) #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)