From patchwork Wed Jan 20 02:43:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yilun X-Patchwork-Id: 12031293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBC12C433DB for ; Wed, 20 Jan 2021 02:49:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6CEA123109 for ; Wed, 20 Jan 2021 02:49:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388641AbhATCsw (ORCPT ); Tue, 19 Jan 2021 21:48:52 -0500 Received: from mga17.intel.com ([192.55.52.151]:3813 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731344AbhATCsq (ORCPT ); Tue, 19 Jan 2021 21:48:46 -0500 IronPort-SDR: kkhR90n0FHtHAR7BBlTXcalBcLAw5YFQg90jSLa9tRVlejw4B1qzegqvDShbUKIKUixWyPzDCP hVl6gwipRxnw== X-IronPort-AV: E=McAfee;i="6000,8403,9869"; a="158808452" X-IronPort-AV: E=Sophos;i="5.79,359,1602572400"; d="scan'208";a="158808452" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2021 18:48:05 -0800 IronPort-SDR: lOAppi37a2Ant2Zyd3AdA2GnHBbqwySsUAehzJBk8TfZ9s69bNlWHeEAVgjVBLjg6rsb14RX0F +FxGS6imR+Zw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,359,1602572400"; d="scan'208";a="355871053" Received: from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.141]) by fmsmga008.fm.intel.com with ESMTP; 19 Jan 2021 18:48:03 -0800 From: Xu Yilun To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: gregkh@linuxfoundation.org, trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com Subject: [PATCH v7 1/2] fpga: dfl: add the userspace I/O device support for DFL devices Date: Wed, 20 Jan 2021 10:43:25 +0800 Message-Id: <1611110606-10380-2-git-send-email-yilun.xu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611110606-10380-1-git-send-email-yilun.xu@intel.com> References: <1611110606-10380-1-git-send-email-yilun.xu@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch supports the DFL drivers be written in userspace. This is realized by exposing the userspace I/O device interfaces. The driver leverages the uio_pdrv_genirq, it adds the uio_pdrv_genirq platform device with the DFL device's resources, and let the generic UIO platform device driver provide support to userspace access to kernel interrupts and memory locations. The driver now supports the ether group feature. To support a new DFL feature been directly accessed via UIO, its feature id should be added to the driver's id_table. Signed-off-by: Xu Yilun Reviewed-by: Tom Rix Acked-by: Wu Hao --- v2: switch to the new matching algorithem. It matches DFL devices which could not be handled by other DFL drivers. refacor the code about device resources filling. fix some comments. v3: split the dfl.c changes out of this patch. some minor fixes v4: drop the idea of a generic matching algorithem, instead we specify each matching device in id_table. to make clear that only one irq is supported, the irq handling code is refactored. v5: refactor the irq resource code. v6: fix the res[] zero initialization issue. improve the return code for probe(). v7: use platform_device_register_resndata() for pdev creation. remove some unnecessary head file includings. some minor fixes. --- drivers/fpga/Kconfig | 10 ++++++ drivers/fpga/Makefile | 1 + drivers/fpga/dfl-uio-pdev.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 drivers/fpga/dfl-uio-pdev.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 5ff9438..0a21bf2 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -203,6 +203,16 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000 the card. It also instantiates the SPI master (spi-altera) for the card's BMC (Board Management Controller). +config FPGA_DFL_UIO_PDEV + tristate "FPGA DFL Driver for Userspace I/O platform devices" + depends on FPGA_DFL && UIO_PDRV_GENIRQ + help + Enable this to allow DFL drivers to be written in userspace. It + adds the uio_pdrv_genirq platform device with the DFL feature's + resources, and lets the generic UIO platform device driver provide + support for userspace access to kernel interrupts and memory + locations. + config FPGA_DFL_PCI tristate "FPGA DFL PCIe Device Driver" depends on PCI && FPGA_DFL diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 18dc9885..8847fe0 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o dfl-afu-objs += dfl-afu-error.o obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o +obj-$(CONFIG_FPGA_DFL_UIO_PDEV) += dfl-uio-pdev.o # Drivers for FPGAs which implement DFL obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o diff --git a/drivers/fpga/dfl-uio-pdev.c b/drivers/fpga/dfl-uio-pdev.c new file mode 100644 index 0000000..9572ffd --- /dev/null +++ b/drivers/fpga/dfl-uio-pdev.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DFL driver for Userspace I/O platform devices + * + * Copyright (C) 2020 Intel Corporation, Inc. + */ +#include +#include +#include +#include +#include + +#define DRIVER_NAME "dfl-uio-pdev" + +static int dfl_uio_pdev_probe(struct dfl_device *ddev) +{ + struct resource res[2] = { { 0 } }; + struct uio_info uio_pdata = { 0 }; + struct platform_device *uio_pdev; + struct device *dev = &ddev->dev; + unsigned int num_res = 1; + + res[0].parent = &ddev->mmio_res; + res[0].flags = IORESOURCE_MEM; + res[0].start = ddev->mmio_res.start; + res[0].end = ddev->mmio_res.end; + + if (ddev->num_irqs) { + if (ddev->num_irqs > 1) + dev_warn(dev, + "%d irqs for %s, but UIO only supports the first one\n", + ddev->num_irqs, dev_name(dev)); + + res[1].flags = IORESOURCE_IRQ; + res[1].start = ddev->irqs[0]; + res[1].end = ddev->irqs[0]; + num_res++; + } + + uio_pdata.name = DRIVER_NAME; + uio_pdata.version = "0"; + + uio_pdev = platform_device_register_resndata(dev, + "uio_pdrv_genirq", + PLATFORM_DEVID_AUTO, + res, num_res, + &uio_pdata, + sizeof(uio_pdata)); + if (IS_ERR(uio_pdev)) + return PTR_ERR(uio_pdev); + + dev_set_drvdata(dev, uio_pdev); + + return 0; +} + +static void dfl_uio_pdev_remove(struct dfl_device *ddev) +{ + struct platform_device *uio_pdev = dev_get_drvdata(&ddev->dev); + + platform_device_unregister(uio_pdev); +} + +#define FME_FEATURE_ID_ETH_GROUP 0x10 + +static const struct dfl_device_id dfl_uio_pdev_ids[] = { + { FME_ID, FME_FEATURE_ID_ETH_GROUP }, + { } +}; +MODULE_DEVICE_TABLE(dfl, dfl_uio_pdev_ids); + +static struct dfl_driver dfl_uio_pdev_driver = { + .drv = { + .name = DRIVER_NAME, + }, + .id_table = dfl_uio_pdev_ids, + .probe = dfl_uio_pdev_probe, + .remove = dfl_uio_pdev_remove, +}; +module_dfl_driver(dfl_uio_pdev_driver); + +MODULE_DESCRIPTION("DFL driver for Userspace I/O platform devices"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Jan 20 02:43:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yilun X-Patchwork-Id: 12031297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF78EC433E0 for ; Wed, 20 Jan 2021 02:49:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 66BB72313B for ; Wed, 20 Jan 2021 02:49:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730726AbhATCsx (ORCPT ); Tue, 19 Jan 2021 21:48:53 -0500 Received: from mga17.intel.com ([192.55.52.151]:3819 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388619AbhATCst (ORCPT ); Tue, 19 Jan 2021 21:48:49 -0500 IronPort-SDR: p5iyAp8MsYvWLYr9t8lP+1C1wJvhMOaLlqJq9NSZMjscsMBGW0JewC1858NPDkesrp0nsDBX+4 1kRUP6kgbfcw== X-IronPort-AV: E=McAfee;i="6000,8403,9869"; a="158808458" X-IronPort-AV: E=Sophos;i="5.79,359,1602572400"; d="scan'208";a="158808458" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2021 18:48:08 -0800 IronPort-SDR: 1SVqAj3W3yzn564qBozYFExqlpsnBU5pclLYoaNWmJNyZkYZw5Zyv4wJjgQ6fn0Qzh1Pkybny1 /GMmCh+R5g+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,359,1602572400"; d="scan'208";a="355871066" Received: from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.141]) by fmsmga008.fm.intel.com with ESMTP; 19 Jan 2021 18:48:07 -0800 From: Xu Yilun To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: gregkh@linuxfoundation.org, trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com Subject: [PATCH v7 2/2] Documentation: fpga: dfl: Add description for DFL UIO support Date: Wed, 20 Jan 2021 10:43:26 +0800 Message-Id: <1611110606-10380-3-git-send-email-yilun.xu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611110606-10380-1-git-send-email-yilun.xu@intel.com> References: <1611110606-10380-1-git-send-email-yilun.xu@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch adds description for UIO support for dfl devices on DFL bus. Signed-off-by: Xu Yilun --- v2: no doc in v1, add it for v2. v3: some documentation fixes. v4: documentation change since the driver matching is changed. v5: no change. v6: improve the title of the userspace driver support section. some word improvement. v7: rebased to next-20210119 --- Documentation/fpga/dfl.rst | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index c41ac76..f96a6fb 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -7,6 +7,7 @@ Authors: - Enno Luebbers - Xiao Guangrong - Wu Hao +- Xu Yilun The Device Feature List (DFL) FPGA framework (and drivers according to this framework) hides the very details of low layer hardwares and provides @@ -530,6 +531,30 @@ Being able to specify more than one DFL per BAR has been considered, but it was determined the use case did not provide value. Specifying a single DFL per BAR simplifies the implementation and allows for extra error checking. + +Userspace driver support for DFL devices +======================================== +The purpose of an FPGA is to be reprogrammed with newly developed hardware +components. New hardware can instantiate a new private feature in the DFL, and +then get a DFL device in their system. In some cases users may need a userspace +driver for the DFL device: + +* Users may need to run some diagnostic test for their hardwares. +* Users may prototype the kernel driver in user space. +* Some hardware is designed for specific purposes and does not fit into one of + the standard kernel subsystems. + +This requires direct access to MMIO space and interrupt handling from +userspace. The dfl-uio-pdev module exposes the UIO device interfaces for this +purpose. It adds the uio_pdrv_genirq platform device with the resources of +the DFL feature, and lets the generic UIO platform device driver provide UIO +support to userspace. + +FPGA_DFL_UIO_PDEV should be selected to enable the dfl-uio-pdev module driver. +To support a new DFL feature been directly accessed via UIO, its feature id +should be added to the driver's id_table. + + Open discussion =============== FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration