From patchwork Fri Jan 22 11:52:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 12039111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F07DC433E0 for ; Fri, 22 Jan 2021 11:58:11 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 511FA22C9F for ; Fri, 22 Jan 2021 11:58:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 511FA22C9F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=y1n+p2DkaPyc8KKeHx+gV04jAX/T+7d61z/gqwPYI3A=; b=1hUKy91kR1D83FZ1y+S0t3Prq 4sAnEr/VuZWD+CHEa1D7B+BvAR8QdmC/DpwTN57Hkh/smsMUmB0zxqoH71BMS05o2ENPFk/PYUSJl DcG+F8txiP03molnxkD7GC1brXhihaELG8fYI6pRTb0GNLJ0Gqj1mUTq2/rLM5+nMZRDWueMlV+fq gnZoL4av2+SrNjZLs/+1lBs+DL2Ky1SU66RrfStxucODFNa1YaxNP11dXQ2aDCorj/yc2vLc4Insa Kct2J+Jr19I51tOg3WY5ktvxEoeoopqs18Pe5jF9e1aXMT8s0sGfKapr6LjoPmHw2qlFnPgYpyxM1 2m/jvNpmQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2v3N-0003TH-1N; Fri, 22 Jan 2021 11:56:37 +0000 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2v3F-0003Qr-QL for linux-arm-kernel@lists.infradead.org; Fri, 22 Jan 2021 11:56:31 +0000 Received: by mail-wr1-x42d.google.com with SMTP id g10so4834821wrx.1 for ; Fri, 22 Jan 2021 03:56:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0SgQac0tiwSnubcxGDua82/tHq+RVHRl87pjSP5itgM=; b=c/+lm4UV7z4yrpevZBw5MXVbSHJfG5GvTYXmR523SsGeYoSjX+jOx59hx0TYoUsns6 Ict0mSd2fZU4yt/FVPoKw/R/mbLQ8F5Wem25jFZQVmCmSll0JDtLuUbhwlD0DVmoitZ1 aj8CSe9+sfkxxiDLIynYlR5PUqgH3yj7sppaM7GwCdms7piu1hXvNh00PX9kvSScWCBQ RwKf/LiIAqjTHqz/PGpJu5oJltalvLPVZfYD0YAGhuGxe9j1+/39N7ejCX5yp47AiScG 6HZ0DppJ5pDNc/r04nIS65fIXwrP1ALy7IRZjxbVA0gVJ/XXXs5wHnrG9SmT/5S9DUxW z/vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0SgQac0tiwSnubcxGDua82/tHq+RVHRl87pjSP5itgM=; b=YpVDG0PjGge8oSbIuGGNtRcs4u+LeFvGbOLkazLoiWH5aUn+4I2Y6A30tjurbtnabZ jaXQZ0v1mSgDA4/PnQt79d9aCLSw6/flFOAM3wMpBOg7vwz/NVJW37t777brOFPW7l9E RwXwiDeNOtq6vlzG5zqTgVeFQ28gi3zyjnxvy4Nlnh/r852Ni/FR39UYn/LgB3zyYhew VR5ZV+fWbzthiRtZ3T/C8mZ24teU2z4UbdeVtNPlvew9ZYSLQO1In1lIW07QFSxTdqfh QwvE6AIXYrsTNfqwjjHEmByvLQojlAooqHNaNpNLTVvjvl/skFpZ+76AwuTTSJ2dvOQM I4hg== X-Gm-Message-State: AOAM533cx7+CbPLFPHLsizc0maQrZ1X7rbimJ/9/de9nzGLG7AouNiCI 2HMi5lqdSu6BmVZptYTZuxMGAw== X-Google-Smtp-Source: ABdhPJwQhy/pUuxgwb7y2QDYJj2WfJIWjTPpeXGb67NOjvpLAu1UsjCylvROLm7OF+CedXFEccK+Pg== X-Received: by 2002:adf:9b92:: with SMTP id d18mr4293974wrc.170.1611316588567; Fri, 22 Jan 2021 03:56:28 -0800 (PST) Received: from localhost.localdomain ([2001:1715:4e26:a7e0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id s25sm13293901wrs.49.2021.01.22.03.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jan 2021 03:56:28 -0800 (PST) From: Jean-Philippe Brucker To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Subject: [PATCH 1/3] iommu/arm-smmu-v3: Split arm_smmu_tlb_inv_range() Date: Fri, 22 Jan 2021 12:52:56 +0100 Message-Id: <20210122115257.2502526-2-jean-philippe@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210122115257.2502526-1-jean-philippe@linaro.org> References: <20210122115257.2502526-1-jean-philippe@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210122_065630_183131_4F7AAC96 X-CRM114-Status: GOOD ( 18.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jean-Philippe Brucker , vivek.gautam@arm.com, eric.auger@redhat.com, iommu@lists.linux-foundation.org, Jonathan.Cameron@huawei.com, zhangfei.gao@linaro.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Extract some of the cmd initialization and the ATC invalidation from arm_smmu_tlb_inv_range(), to allow an MMU notifier to invalidate a VA range by ASID. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 62 ++++++++++++--------- 1 file changed, 35 insertions(+), 27 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 740a3d487591..a27b074d5c0c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1934,40 +1934,27 @@ static void arm_smmu_tlb_inv_context(void *cookie) arm_smmu_atc_inv_domain(smmu_domain, 0, 0, 0); } -static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size, - size_t granule, bool leaf, +static void arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, + unsigned long iova, size_t size, + size_t granule, struct arm_smmu_domain *smmu_domain) { struct arm_smmu_device *smmu = smmu_domain->smmu; - unsigned long start = iova, end = iova + size, num_pages = 0, tg = 0; + unsigned long end = iova + size, num_pages = 0, tg = 0; size_t inv_range = granule; struct arm_smmu_cmdq_batch cmds = {}; - struct arm_smmu_cmdq_ent cmd = { - .tlbi = { - .leaf = leaf, - }, - }; - if (!size) return; - if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { - cmd.opcode = CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; - } else { - cmd.opcode = CMDQ_OP_TLBI_S2_IPA; - cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; - } - if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { /* Get the leaf page size */ tg = __ffs(smmu_domain->domain.pgsize_bitmap); /* Convert page size of 12,14,16 (log2) to 1,2,3 */ - cmd.tlbi.tg = (tg - 10) / 2; + cmd->tlbi.tg = (tg - 10) / 2; /* Determine what level the granule is at */ - cmd.tlbi.ttl = 4 - ((ilog2(granule) - 3) / (tg - 3)); + cmd->tlbi.ttl = 4 - ((ilog2(granule) - 3) / (tg - 3)); num_pages = size >> tg; } @@ -1985,11 +1972,11 @@ static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size, /* Determine the power of 2 multiple number of pages */ scale = __ffs(num_pages); - cmd.tlbi.scale = scale; + cmd->tlbi.scale = scale; /* Determine how many chunks of 2^scale size we have */ num = (num_pages >> scale) & CMDQ_TLBI_RANGE_NUM_MAX; - cmd.tlbi.num = num - 1; + cmd->tlbi.num = num - 1; /* range is num * 2^scale * pgsize */ inv_range = num << (scale + tg); @@ -1998,17 +1985,37 @@ static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size, num_pages -= num << scale; } - cmd.tlbi.addr = iova; - arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); + cmd->tlbi.addr = iova; + arm_smmu_cmdq_batch_add(smmu, &cmds, cmd); iova += inv_range; } arm_smmu_cmdq_batch_submit(smmu, &cmds); +} + +static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, + size_t granule, bool leaf, + struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_cmdq_ent cmd = { + .tlbi = { + .leaf = leaf, + }, + }; + + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + cmd.opcode = CMDQ_OP_TLBI_NH_VA; + cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; + } else { + cmd.opcode = CMDQ_OP_TLBI_S2_IPA; + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; + } + arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); /* * Unfortunately, this can't be leaf-only since we may have * zapped an entire table. */ - arm_smmu_atc_inv_domain(smmu_domain, 0, start, size); + arm_smmu_atc_inv_domain(smmu_domain, 0, iova, size); } static void arm_smmu_tlb_inv_page_nosync(struct iommu_iotlb_gather *gather, @@ -2024,7 +2031,7 @@ static void arm_smmu_tlb_inv_page_nosync(struct iommu_iotlb_gather *gather, static void arm_smmu_tlb_inv_walk(unsigned long iova, size_t size, size_t granule, void *cookie) { - arm_smmu_tlb_inv_range(iova, size, granule, false, cookie); + arm_smmu_tlb_inv_range_domain(iova, size, granule, false, cookie); } static const struct iommu_flush_ops arm_smmu_flush_ops = { @@ -2622,8 +2629,9 @@ static void arm_smmu_iotlb_sync(struct iommu_domain *domain, { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); - arm_smmu_tlb_inv_range(gather->start, gather->end - gather->start, - gather->pgsize, true, smmu_domain); + arm_smmu_tlb_inv_range_domain(gather->start, + gather->end - gather->start, + gather->pgsize, true, smmu_domain); } static phys_addr_t From patchwork Fri Jan 22 11:52:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 12039113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41C78C433E6 for ; Fri, 22 Jan 2021 11:58:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 06ABC22C9F for ; Fri, 22 Jan 2021 11:58:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 06ABC22C9F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2qtjEnQ7dRH6pnkDzWl9cL1/4J1vpo7jTqZL0DIUKqA=; b=fSVpQS1WQSyq5Gk6RXTavv/Il t2YKJvV/1nCHTVfgLaij12EYrcdm8GcYMIefryQge7VL2nrVMJe8nc4HB697Esa+MpZyLIyrZc4LV toYQZ7pK9hl6r9nY5b3ma1y5bLDB4AR5n+EX3RYVhIjzPG7jv81SfnhWBSEIftO01GMvnNwe5OZUN HK9Jow3Z7J7bhEfoBnSg03HygDRQET91Z5K+zBWXhUsmH3rPy88dYYaXj8XNQFwogOBfgHjO3b9MT M7tcLWwt3da7MO/lZ5Bbe0D+O446/jR5eYJkoJehBVlWFzm5XQb5qlMc+/wT2NQHcmB22mLvl8jv3 SjUsmVgsQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2v3R-0003Us-L5; Fri, 22 Jan 2021 11:56:41 +0000 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2v3G-0003RA-CI for linux-arm-kernel@lists.infradead.org; Fri, 22 Jan 2021 11:56:31 +0000 Received: by mail-wr1-x42d.google.com with SMTP id 7so4836370wrz.0 for ; Fri, 22 Jan 2021 03:56:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=owZkjSFOA0fuCp5k3fuGX+G2Hp6YSx1juCTT9XbA4kE=; b=Yfotiij4PbT44jIwb874ov94q9TaJDIr5uPZmkTQVPdRZWtdCst/v6l+xeo4jnWBMu MlaCnH3+Gxgv079JfZb4MTr/GSo8Yb9GWJYxYabZzRq52FufOyZVmHwxraQ/KzVJ92lb BtuQ/4V+F0ZHuIlCOhmXQGEvbOZyseb/36c95qb0YJ6y1KeUIKROkvjCPixnXwpQqx4k XTx2C6Z8u+pi8+F6APbGGv8P6Q2D+kfR50/YNse42JxmWoVZqPDnR5zq5I8Ei6fFB6Tt ZA5MiHUhwp1eHSEglPQgJIcmJ13JceHsZtcZ1y6nJnnvnG+hHOHBwirNFms2VxXD/BHt IwWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=owZkjSFOA0fuCp5k3fuGX+G2Hp6YSx1juCTT9XbA4kE=; b=faZ++WQbHAV6nAkf7OFPYia/N0b14eV7jW08rkKElmF7hCbrQ4/wsWoQDbiGu/F4ZP wt2sfk+375KBSYm/oPhSPfOnI23ZYxPjLcZgIyeFXJKXrqgCmMeHJGZvXcPdGrrxwIZn /UacQHXOkq2uXGweVfdBjWN9mKa8bUAP9RzzyRAgik5mIYWQExhw7JQfzdPDKgZ5QNhC zVPYsVng7nD9kzj1PIMAoyolqWA/17x0D13JdG1NvvVCgzbAwTI6dtX2gdNVX7A60sbs UEw5icbBBnWyqRRawfNuJBwbC+YkHjA1RyHrDUSpikYLXquIfXGy6FYQsYIZkWY99Dgr 6sBg== X-Gm-Message-State: AOAM533gY0TQGj6V6tc8Z6isj+vSrfrGb8aHjyua8NEeYBjnflBb6pu5 PT/KI8s7O3QxOER5/cWTJCB5Cg== X-Google-Smtp-Source: ABdhPJxmWG1lTuXpvqqZl1ip4r8FU//sAdGE7mIr6uOeJ1+qwBEyt54qF3kDGQgJMOB/K5vmESCGbg== X-Received: by 2002:adf:fd10:: with SMTP id e16mr3952999wrr.376.1611316589591; Fri, 22 Jan 2021 03:56:29 -0800 (PST) Received: from localhost.localdomain ([2001:1715:4e26:a7e0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id s25sm13293901wrs.49.2021.01.22.03.56.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jan 2021 03:56:29 -0800 (PST) From: Jean-Philippe Brucker To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Subject: [PATCH 2/3] iommu/arm-smmu-v3: Make BTM optional for SVA Date: Fri, 22 Jan 2021 12:52:57 +0100 Message-Id: <20210122115257.2502526-3-jean-philippe@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210122115257.2502526-1-jean-philippe@linaro.org> References: <20210122115257.2502526-1-jean-philippe@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210122_065630_440802_27EF7FBC X-CRM114-Status: GOOD ( 15.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jean-Philippe Brucker , vivek.gautam@arm.com, eric.auger@redhat.com, iommu@lists.linux-foundation.org, Jonathan.Cameron@huawei.com, zhangfei.gao@linaro.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When BTM isn't supported by the SMMU, send invalidations on the command queue. Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 14 +++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 14 ++++++++++++++ 3 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index a6536c2b32d0..652d03ad8ae6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -743,6 +743,9 @@ extern struct arm_smmu_ctx_desc quiet_cd; int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, struct arm_smmu_ctx_desc *cd); void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid); +void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, + size_t granule, bool leaf, + struct arm_smmu_domain *smmu_domain); bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd); int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, unsigned long iova, size_t size); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 642ce2c225b5..ad8cf62a8f83 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -16,6 +16,7 @@ struct arm_smmu_mmu_notifier { struct mmu_notifier mn; struct arm_smmu_ctx_desc *cd; bool cleared; + bool tlb_inv_command; refcount_t refs; struct list_head list; struct arm_smmu_domain *domain; @@ -182,9 +183,13 @@ static void arm_smmu_mm_invalidate_range(struct mmu_notifier *mn, unsigned long start, unsigned long end) { struct arm_smmu_mmu_notifier *smmu_mn = mn_to_smmu(mn); + struct arm_smmu_domain *smmu_domain = smmu_mn->domain; + size_t size = end - start + 1; - arm_smmu_atc_inv_domain(smmu_mn->domain, mm->pasid, start, - end - start + 1); + if (smmu_mn->tlb_inv_command) + arm_smmu_tlb_inv_range_asid(start, size, smmu_mn->cd->asid, + PAGE_SIZE, false, smmu_domain); + arm_smmu_atc_inv_domain(smmu_domain, mm->pasid, start, size); } static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) @@ -253,6 +258,9 @@ arm_smmu_mmu_notifier_get(struct arm_smmu_domain *smmu_domain, smmu_mn->domain = smmu_domain; smmu_mn->mn.ops = &arm_smmu_mmu_notifier_ops; + if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_BTM)) + smmu_mn->tlb_inv_command = true; + ret = mmu_notifier_register(&smmu_mn->mn, mm); if (ret) { kfree(smmu_mn); @@ -404,7 +412,7 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) unsigned long reg, fld; unsigned long oas; unsigned long asid_bits; - u32 feat_mask = ARM_SMMU_FEAT_BTM | ARM_SMMU_FEAT_COHERENCY; + u32 feat_mask = ARM_SMMU_FEAT_COHERENCY; if (vabits_actual == 52) feat_mask |= ARM_SMMU_FEAT_VAX; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index a27b074d5c0c..db545834493b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2018,6 +2018,20 @@ static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, arm_smmu_atc_inv_domain(smmu_domain, 0, iova, size); } +void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, + size_t granule, bool leaf, + struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_cmdq_ent cmd = { + .opcode = CMDQ_OP_TLBI_NH_VA, + .tlbi = { + .asid = asid, + .leaf = leaf, + }, + }; + arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); +} + static void arm_smmu_tlb_inv_page_nosync(struct iommu_iotlb_gather *gather, unsigned long iova, size_t granule, void *cookie) From patchwork Fri Jan 22 11:52:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 12039109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C96CDC433DB for ; Fri, 22 Jan 2021 11:58:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 88CF522CA1 for ; Fri, 22 Jan 2021 11:58:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 88CF522CA1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IanOkHhr+/0XQLah7kSRfcyCFTbFounQQDfjllC5dp4=; b=YAPSHIurbX4+ymEhKcMh5w+nC TEEfokRQNqeVXu1GckIVLHDcOIXvuE0555DCi7wxh/npo/zmnX3puuFRiEVZo1ebuMHdXrXLdKDEF yiBDjy15smAntsaEF9eqvK7AGsasfs+TeakhU/rmX0jENCGvsLhSOcagedp4NdYOUWIqmPxzBSgCd sYRsopgLeYn/QOflv1alG02SRb6Sahfu2j2wEfNhtRpl1oHkvXgtVwYeLuZ8v/gHX0QIegP4ipDF9 SlrvNdBjlk/yf6G856AU4zXzvlsSFc7GcmGpWe8wjOanfmnbvpJoiKS9ILhfi8x0pgUk68boBCcuz NwhpOjTng==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2v3V-0003Vo-Uz; Fri, 22 Jan 2021 11:56:45 +0000 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l2v3H-0003Rj-Em for linux-arm-kernel@lists.infradead.org; Fri, 22 Jan 2021 11:56:32 +0000 Received: by mail-wr1-x42d.google.com with SMTP id d16so4145224wro.11 for ; Fri, 22 Jan 2021 03:56:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oWZRXMZDgDlfj6/sL+CjFjPKysCEMdAVcP30NzlMW3A=; b=WhTGf3RimLURoo2pLZsYUSInopH1384+nX4wdx1eFJGM8B74DB6uj9savxXIaCOlWq S3l5wvl7QZw8vSwfuEpy6A4UYx2Gtup6Hghg18fDbwLB41loComV5CqYmzR0Jb1RCPA6 sotnsTmMKdUr9fQm9UlU4MOkerSOPc2z7RqrQ/7kW5Y6ELy60wswupNPKy2J9IsocZJ9 iuWT1M173gDLKZVde7+3rysBT5t0Yk6PiqpqgrJb/JXWlWVyGFky+PBjvVTiv0W2Dmm7 fBL7cR5bczmiYNd8TW1uO2Z4CwqThc/vbQOzwp/0i6ZHPK9OrEqHozQvOip2nkWf0YeE xFzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oWZRXMZDgDlfj6/sL+CjFjPKysCEMdAVcP30NzlMW3A=; b=jZfBob4iqVOr3hWPoz5jX/wNosQLsYMcwMZUJlodSBV6k3Xt8K8jVrdPNLpQZAYYkp +JrxV/NHGDdYjdjHTppnkVICseAOQC4wt4o5PkyU2o3KyD4KipvmAups3yVChj/WgNKO 9w5lkKyQftYgHqB4KWGAwFon6wpgESHXa1w5NynocuwPAPTobVmv8ulNXwQwt6Nr/Fgz vsSDtqJA7zRPeONx9CCtCLkbeaqY2hh9ZWwheMHLlmktrdIv4LzpeuvFFyEujmm60cQ/ mMVSE8mHxg6bpI5HmKXdnr8cqXx+AyqMKqVvaZ4l0dJ+h04zqpeKlHJgfgpc2CzpDK88 rGVA== X-Gm-Message-State: AOAM531HIM8h8c7ak5QLWGaBBvydLDoY9+tmyaFNnWgjxZiBr70hkViR GOUVh54UxPsKDeUfdPRQRLC2Aw== X-Google-Smtp-Source: ABdhPJzDxK+tf+jt3CZVne4oNGyBINi41Jm4IWEr/aLUZcceD2WqoWsTINI0w8feQa9ASZaalR8Pzg== X-Received: by 2002:adf:f403:: with SMTP id g3mr4180245wro.212.1611316590574; Fri, 22 Jan 2021 03:56:30 -0800 (PST) Received: from localhost.localdomain ([2001:1715:4e26:a7e0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id s25sm13293901wrs.49.2021.01.22.03.56.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jan 2021 03:56:30 -0800 (PST) From: Jean-Philippe Brucker To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Subject: [PATCH 3/3] iommu/arm-smmu-v3: Add support for VHE Date: Fri, 22 Jan 2021 12:52:58 +0100 Message-Id: <20210122115257.2502526-4-jean-philippe@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210122115257.2502526-1-jean-philippe@linaro.org> References: <20210122115257.2502526-1-jean-philippe@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210122_065631_538099_7BAA2162 X-CRM114-Status: GOOD ( 19.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jean-Philippe Brucker , vivek.gautam@arm.com, eric.auger@redhat.com, iommu@lists.linux-foundation.org, Jonathan.Cameron@huawei.com, zhangfei.gao@linaro.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org ARMv8.1 extensions added Virtualization Host Extensions (VHE), which allow to run a host kernel at EL2. When using normal DMA, Device and CPU address spaces are dissociated, and do not need to implement the same capabilities, so VHE hasn't been used in the SMMU until now. With shared address spaces however, ASIDs are shared between MMU and SMMU, and broadcast TLB invalidations issued by a CPU are taken into account by the SMMU. TLB entries on both sides need to have identical exception level in order to be cleared with a single invalidation. When the CPU is using VHE, enable VHE in the SMMU for all STEs. Normal DMA mappings will need to use TLBI_EL2 commands instead of TLBI_NH, but shouldn't be otherwise affected by this change. Acked-by: Will Deacon Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 32 ++++++++++++++++----- 2 files changed, 28 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 652d03ad8ae6..c01a65b4ae14 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -454,6 +454,8 @@ struct arm_smmu_cmdq_ent { #define CMDQ_OP_TLBI_NH_ASID 0x11 #define CMDQ_OP_TLBI_NH_VA 0x12 #define CMDQ_OP_TLBI_EL2_ALL 0x20 + #define CMDQ_OP_TLBI_EL2_ASID 0x21 + #define CMDQ_OP_TLBI_EL2_VA 0x22 #define CMDQ_OP_TLBI_S12_VMALL 0x28 #define CMDQ_OP_TLBI_S2_IPA 0x2a #define CMDQ_OP_TLBI_NSNH_ALL 0x30 @@ -639,6 +641,7 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_RANGE_INV (1 << 15) #define ARM_SMMU_FEAT_BTM (1 << 16) #define ARM_SMMU_FEAT_SVA (1 << 17) +#define ARM_SMMU_FEAT_E2H (1 << 18) u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index db545834493b..be762f8c1bc5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -273,9 +273,11 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31); break; case CMDQ_OP_TLBI_NH_VA: + cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); + fallthrough; + case CMDQ_OP_TLBI_EL2_VA: cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num); cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale); - cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf); cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl); @@ -297,6 +299,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) case CMDQ_OP_TLBI_S12_VMALL: cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); break; + case CMDQ_OP_TLBI_EL2_ASID: + cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); + break; case CMDQ_OP_ATC_INV: cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid); cmd[0] |= FIELD_PREP(CMDQ_ATC_0_GLOBAL, ent->atc.global); @@ -945,7 +950,8 @@ static int arm_smmu_page_response(struct device *dev, void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) { struct arm_smmu_cmdq_ent cmd = { - .opcode = CMDQ_OP_TLBI_NH_ASID, + .opcode = smmu->features & ARM_SMMU_FEAT_E2H ? + CMDQ_OP_TLBI_EL2_ASID : CMDQ_OP_TLBI_NH_ASID, .tlbi.asid = asid, }; @@ -1326,13 +1332,16 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, } if (s1_cfg) { + u64 strw = smmu->features & ARM_SMMU_FEAT_E2H ? + STRTAB_STE_1_STRW_EL2 : STRTAB_STE_1_STRW_NSEL1; + BUG_ON(ste_live); dst[1] = cpu_to_le64( FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | - FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1)); + FIELD_PREP(STRTAB_STE_1_STRW, strw)); if (master->prg_resp_needs_ssid) dst[1] |= cpu_to_le64(STRTAB_STE_1_PPAR); @@ -2003,7 +2012,8 @@ static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, }; if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { - cmd.opcode = CMDQ_OP_TLBI_NH_VA; + cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? + CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; } else { cmd.opcode = CMDQ_OP_TLBI_S2_IPA; @@ -2023,7 +2033,8 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, struct arm_smmu_domain *smmu_domain) { struct arm_smmu_cmdq_ent cmd = { - .opcode = CMDQ_OP_TLBI_NH_VA, + .opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? + CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA, .tlbi = { .asid = asid, .leaf = leaf, @@ -3544,7 +3555,11 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); /* CR2 (random crap) */ - reg = CR2_PTM | CR2_RECINVSID | CR2_E2H; + reg = CR2_PTM | CR2_RECINVSID; + + if (smmu->features & ARM_SMMU_FEAT_E2H) + reg |= CR2_E2H; + writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); /* Stream table */ @@ -3705,8 +3720,11 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) smmu->options |= ARM_SMMU_OPT_MSIPOLL; } - if (reg & IDR0_HYP) + if (reg & IDR0_HYP) { smmu->features |= ARM_SMMU_FEAT_HYP; + if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) + smmu->features |= ARM_SMMU_FEAT_E2H; + } /* * The coherency feature as set by FW is used in preference to the ID