From patchwork Mon Jan 25 14:07:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 12043527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2666BC433E0 for ; Mon, 25 Jan 2021 14:08:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DFD5822C9E for ; Mon, 25 Jan 2021 14:08:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DFD5822C9E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6AC306E15D; Mon, 25 Jan 2021 14:08:51 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id E09316E054 for ; Mon, 25 Jan 2021 14:08:49 +0000 (UTC) IronPort-SDR: g36qQkfMmLvevxHE0F4mCsSiKQHGyOnJT8wBZ4/gA0Z33+mhov9LUZOseC9tpKxWDng3KzTsHZ 95bd2VYwWN+w== X-IronPort-AV: E=McAfee;i="6000,8403,9874"; a="179879100" X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="179879100" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:28 -0800 IronPort-SDR: PrOCqdp9md9j0WwAs0EduA78tXGrh/dE5fOPcfoJBGaEVVXibdvPtyq3GGG2zowRCuN5nlvzNV WsV0lrrIiP2A== X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="472319525" Received: from iduggana-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.81.9]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:27 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jan 2021 06:07:44 -0800 Message-Id: <20210125140753.347998-2-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210125140753.347998-1-aditya.swarup@intel.com> References: <20210125140753.347998-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/10] x86/gpu: Add Alderlake-S stolen memory support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Caz Yokoyama Alderlake-S is a Gen 12 based hybrid processor architeture. As it belongs to Gen 12 family, it uses the same GTT stolen memory settings like its predecessors - ICL(Gen 11) and TGL(Gen 12). This patch inherits the gen11 and gen 9 quirks for determining base and size of stolen memory. Note that this patch depends on commit 0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids") Bspec: 52055 Bspec: 49589 Bspec: 49636 Cc: Lucas De Marchi Signed-off-by: Caz Yokoyama Signed-off-by: Aditya Swarup Reviewed-by: Lucas De Marchi --- arch/x86/kernel/early-quirks.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index a4b5af03dcc1..6edd1e2ee8af 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -551,6 +551,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_EHL_IDS(&gen11_early_ops), INTEL_TGL_12_IDS(&gen11_early_ops), INTEL_RKL_IDS(&gen11_early_ops), + INTEL_ADLS_IDS(&gen11_early_ops), }; struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0); From patchwork Mon Jan 25 14:07:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 12043529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10492C433DB for ; Mon, 25 Jan 2021 14:08:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BEDEF22C9E for ; Mon, 25 Jan 2021 14:08:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BEDEF22C9E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA50B6E0F0; Mon, 25 Jan 2021 14:08:51 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5C3836E054 for ; Mon, 25 Jan 2021 14:08:50 +0000 (UTC) IronPort-SDR: oCKflvVcX8h8ObHHLbwTUOSnFHF7eyw01HrrJqgfK7QVcCPXLr83PpDnANZKSfh7wzZsBawsJb XsEphdlqm+FQ== X-IronPort-AV: E=McAfee;i="6000,8403,9874"; a="179879103" X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="179879103" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:28 -0800 IronPort-SDR: rKqc/Vgbt9xboeI81PCci+6c1qyx0Lgx55TlyMe5VkYHDYh/W5HwhJCavdq2+xu1eJBDhc/IxZ 5K+849gGpsjQ== X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="472319543" Received: from iduggana-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.81.9]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:28 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jan 2021 06:07:45 -0800 Message-Id: <20210125140753.347998-3-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210125140753.347998-1-aditya.swarup@intel.com> References: <20210125140753.347998-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 02/10] drm/i915/adl_s: Add PCH support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Add support for Alderpoint(ADP) PCH used with Alderlake-S. v2: - Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup) Cc: Matt Roper Cc: Lucas De Marchi Cc: Caz Yokoyama Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Signed-off-by: Anusha Srivatsa Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_pch.c | 8 +++++++- drivers/gpu/drm/i915/intel_pch.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index ecaf314d60b6..4813207fc053 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -128,6 +128,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n"); drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv)); return PCH_JSP; + case INTEL_PCH_ADP_DEVICE_ID_TYPE: + drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n"); + drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv)); + return PCH_ADP; default: return PCH_NONE; } @@ -156,7 +160,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv, * make an educated guess as to which PCH is really there. */ - if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) + if (IS_ALDERLAKE_S(dev_priv)) + id = INTEL_PCH_ADP_DEVICE_ID_TYPE; + else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) id = INTEL_PCH_TGP_DEVICE_ID_TYPE; else if (IS_JSL_EHL(dev_priv)) id = INTEL_PCH_MCC_DEVICE_ID_TYPE; diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h index 06d2cd50af0b..7318377503b0 100644 --- a/drivers/gpu/drm/i915/intel_pch.h +++ b/drivers/gpu/drm/i915/intel_pch.h @@ -26,6 +26,7 @@ enum intel_pch { PCH_JSP, /* Jasper Lake PCH */ PCH_MCC, /* Mule Creek Canyon PCH */ PCH_TGP, /* Tiger Lake PCH */ + PCH_ADP, /* Alder Lake PCH */ /* Fake PCHs, functionality handled on the same PCI dev */ PCH_DG1 = 1024, @@ -53,12 +54,14 @@ enum intel_pch { #define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380 #define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80 #define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880 +#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) +#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) #define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP) #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) From patchwork Mon Jan 25 14:07:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 12043531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC6B5C433DB for ; Mon, 25 Jan 2021 14:08:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9318722C9E for ; Mon, 25 Jan 2021 14:08:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9318722C9E Authentication-Results: mail.kernel.org; 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d="scan'208";a="472319554" Received: from iduggana-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.81.9]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:29 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jan 2021 06:07:46 -0800 Message-Id: <20210125140753.347998-4-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210125140753.347998-1-aditya.swarup@intel.com> References: <20210125140753.347998-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/10] drm/i915/adl_s: Add Interrupt Support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa ADLS follows ICP/TGP like interrupts. v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas) Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: José Roberto de Souza Signed-off-by: Anusha Srivatsa Signed-off-by: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_irq.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 33019cf0e630..6568e7e9fe2a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -209,8 +209,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) if (HAS_PCH_DG1(dev_priv)) hpd->pch_hpd = hpd_sde_dg1; - else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) || - HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) hpd->pch_hpd = hpd_icp; else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) hpd->pch_hpd = hpd_spt; From patchwork Mon Jan 25 14:07:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 12043537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15E41C433E0 for ; Mon, 25 Jan 2021 14:09:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CEE6D22C9E for ; Mon, 25 Jan 2021 14:09:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CEE6D22C9E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A62346E165; Mon, 25 Jan 2021 14:08:56 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3C7976E0F0 for ; Mon, 25 Jan 2021 14:08:51 +0000 (UTC) IronPort-SDR: OaQoOJBnsTno3RlqJbnviEpyeKxLj8iRSwdncfxHIbU0feleZdqBNFpreaKLobRlmRtAiwIuh7 xfZU5X8fIYEw== X-IronPort-AV: E=McAfee;i="6000,8403,9874"; a="179879113" X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="179879113" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:31 -0800 IronPort-SDR: wDa8AgS+NAMi9WsRv4LMUAIzoiTKRRahigPsfyJgNQhEG6d2QcDoX9bLbxtsUrSrm6/QFkvjxv DIpwM/vvrJog== X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="472319565" Received: from iduggana-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.81.9]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:31 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jan 2021 06:07:47 -0800 Message-Id: <20210125140753.347998-5-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210125140753.347998-1-aditya.swarup@intel.com> References: <20210125140753.347998-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 04/10] drm/i915/adl_s: Add PHYs for Alderlake S X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Alderlake-S has 5 combo phys, add reg definitions for combo phys and update the port to phy helper for ADL-S. v2: - Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc() and return false for platforms RKL,DG1 and ADLS.(mdroper) Cc: Lucas De Marchi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Signed-off-by: Anusha Srivatsa Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++----- drivers/gpu/drm/i915/i915_reg.h | 5 ++++- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7ec7d94b8cdb..acf06feffd3e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5668,6 +5668,8 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) { if (phy == PHY_NONE) return false; + else if (IS_ALDERLAKE_S(dev_priv)) + return phy <= PHY_E; else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) return phy <= PHY_D; else if (IS_JSL_EHL(dev_priv)) @@ -5680,11 +5682,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) { - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) - return false; - else if (INTEL_GEN(dev_priv) >= 12) + if (IS_TIGERLAKE(dev_priv)) return phy >= PHY_D && phy <= PHY_I; - else if (INTEL_GEN(dev_priv) >= 11 && !IS_JSL_EHL(dev_priv)) + else if (IS_ICELAKE(dev_priv)) return phy >= PHY_C && phy <= PHY_F; else return false; @@ -5692,7 +5692,9 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) { - if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) + if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) + return PHY_B + port - PORT_TC1; + else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) return PHY_C + port - PORT_TC1; else if (IS_JSL_EHL(i915) && port == PORT_D) return PHY_A; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8b9bbc6bacb1..0fe499840b82 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1874,10 +1874,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _ICL_COMBOPHY_B 0x6C000 #define _EHL_COMBOPHY_C 0x160000 #define _RKL_COMBOPHY_D 0x161000 +#define _ADL_COMBOPHY_E 0x16B000 + #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ _ICL_COMBOPHY_B, \ _EHL_COMBOPHY_C, \ - _RKL_COMBOPHY_D) + _RKL_COMBOPHY_D, \ + _ADL_COMBOPHY_E) /* CNL/ICL Port CL_DW registers */ #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ From patchwork Mon Jan 25 14:07:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 12043535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5B07C433DB for ; Mon, 25 Jan 2021 14:08:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7E51722C9E for ; Mon, 25 Jan 2021 14:08:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7E51722C9E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 594EE6E174; Mon, 25 Jan 2021 14:08:56 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3C38B6E054 for ; Mon, 25 Jan 2021 14:08:51 +0000 (UTC) IronPort-SDR: GbfOZFQdbMYZRILWG02npPWJZ1wwt+zofMO147hX9zrr9AqlfOEqiTn3YYs0nWE2ZK9KoiWiFH X1XixtDudTCg== X-IronPort-AV: E=McAfee;i="6000,8403,9874"; a="179879115" X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="179879115" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:32 -0800 IronPort-SDR: CNq76YggjanfSlg7V4YqXfAEugufMwl7yAZHcVU7VrZcB+R1Yhe1lMC5rfm6I9ThkJIObDBZJ0 pL7jxmknLSaQ== X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="472319573" Received: from iduggana-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.81.9]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:32 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jan 2021 06:07:48 -0800 Message-Id: <20210125140753.347998-6-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210125140753.347998-1-aditya.swarup@intel.com> References: <20210125140753.347998-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 05/10] drm/i915/adl_s: Configure DPLL for ADL-S X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add changes for configuring DPLL for ADL-S - Reusing DG1 DPLL 2 & DPLL 3 for ADL-S - Extend CNL macro to choose DPLL_ENABLE for ADL-S. - Select CFGCR0 and CFGCR1 for ADL-S plls. On BSpec: 53720 PLL arrangement dig for adls: DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1) DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1) v2 (Lucas): add missing update_ref_clks Bspec: 50288 Bspec: 50289 Bspec: 49443 v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield for DPLL3_USED.(mdroper) Bspec: 53707 v4: BSpec 53723 has been updated with note - DPLL2 is controlled by DPLL4 CFGCR 0/1.(mdroper) Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup Signed-off-by: Lucas De Marchi Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++- 2 files changed, 54 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index f6ad257a260e..529b1d569af2 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3559,7 +3559,13 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + dpll_mask = + BIT(DPLL_ID_DG1_DPLL3) | + BIT(DPLL_ID_DG1_DPLL2) | + BIT(DPLL_ID_ICL_DPLL1) | + BIT(DPLL_ID_ICL_DPLL0); + } else if (IS_DG1(dev_priv)) { if (port == PORT_D || port == PORT_E) { dpll_mask = BIT(DPLL_ID_DG1_DPLL2) | @@ -3865,7 +3871,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, if (!(val & PLL_ENABLE)) goto out; - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id)); + } else if (IS_DG1(dev_priv)) { hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id)); } else if (IS_ROCKETLAKE(dev_priv)) { @@ -3921,7 +3930,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, const enum intel_dpll_id id = pll->info->id; i915_reg_t cfgcr0_reg, cfgcr1_reg; - if (IS_DG1(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + cfgcr0_reg = ADLS_DPLL_CFGCR0(id); + cfgcr1_reg = ADLS_DPLL_CFGCR1(id); + } else if (IS_DG1(dev_priv)) { cfgcr0_reg = DG1_DPLL_CFGCR0(id); cfgcr1_reg = DG1_DPLL_CFGCR1(id); } else if (IS_ROCKETLAKE(dev_priv)) { @@ -4384,6 +4396,22 @@ static const struct intel_dpll_mgr dg1_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info adls_plls[] = { + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 }, + { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 }, + { }, +}; + +static const struct intel_dpll_mgr adls_pll_mgr = { + .dpll_info = adls_plls, + .get_dplls = icl_get_dplls, + .put_dplls = icl_put_dplls, + .update_ref_clks = icl_update_dpll_ref_clks, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -4397,7 +4425,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (IS_DG1(dev_priv)) + if (IS_ALDERLAKE_S(dev_priv)) + dpll_mgr = &adls_pll_mgr; + else if (IS_DG1(dev_priv)) dpll_mgr = &dg1_pll_mgr; else if (IS_ROCKETLAKE(dev_priv)) dpll_mgr = &rkl_pll_mgr; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0fe499840b82..339532222d7c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2930,7 +2930,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) #define HDPORT_STATE _MMIO(0x45050) -#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) +#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12) #define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1) #define HDPORT_ENABLED REG_BIT(0) @@ -10394,11 +10394,14 @@ enum skl_power_gate { /* CNL PLL */ #define DPLL0_ENABLE 0x46010 #define DPLL1_ENABLE 0x46014 +#define _ADLS_DPLL2_ENABLE 0x46018 +#define _ADLS_DPLL3_ENABLE 0x46030 #define PLL_ENABLE (1 << 31) #define PLL_LOCK (1 << 30) #define PLL_POWER_ENABLE (1 << 27) #define PLL_POWER_STATE (1 << 26) -#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) +#define CNL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ + _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) #define TBT_PLL_ENABLE _MMIO(0x46020) @@ -10644,6 +10647,21 @@ enum skl_power_gate { _DG1_DPLL2_CFGCR1, \ _DG1_DPLL3_CFGCR1) +/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ +#define _ADLS_DPLL3_CFGCR0 0x1642C0 +#define _ADLS_DPLL4_CFGCR0 0x164294 +#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ + _TGL_DPLL1_CFGCR0, \ + _ADLS_DPLL4_CFGCR0, \ + _ADLS_DPLL3_CFGCR0) + +#define _ADLS_DPLL3_CFGCR1 0x1642C4 +#define _ADLS_DPLL4_CFGCR1 0x164298 +#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ + _TGL_DPLL1_CFGCR1, \ + _ADLS_DPLL4_CFGCR1, \ + _ADLS_DPLL3_CFGCR1) + #define _DKL_PHY1_BASE 0x168000 #define _DKL_PHY2_BASE 0x169000 #define _DKL_PHY3_BASE 0x16A000 From patchwork Mon Jan 25 14:07:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 12043533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C389DC433E0 for ; Mon, 25 Jan 2021 14:08:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 84FA122C9E for ; Mon, 25 Jan 2021 14:08:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 84FA122C9E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0018E6E161; Mon, 25 Jan 2021 14:08:55 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id DD24F6E165 for ; Mon, 25 Jan 2021 14:08:51 +0000 (UTC) IronPort-SDR: 3PLmRQyK4Q/9U732EmLckMQSsbG8D1Cru68nt8wiJJIakewNzgrW0Ci3M5D2XuoQNdrag8CakY MwjGOVo0dSlA== X-IronPort-AV: E=McAfee;i="6000,8403,9874"; a="179879119" X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="179879119" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:34 -0800 IronPort-SDR: GKN+JJui/aVjU2mbBtnNdpoGfPZkeqAR/Pc/OmKs2o+SBOSYU3K3R2jrqWef45Qd7lTOy0kCgv 7FVe9xwIdrcg== X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="472319587" Received: from iduggana-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.81.9]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:33 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jan 2021 06:07:49 -0800 Message-Id: <20210125140753.347998-7-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210125140753.347998-1-aditya.swarup@intel.com> References: <20210125140753.347998-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 06/10] drm/i915/adl_s: Configure Port clock registers for ADL-S X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add changes to configure port clock registers for ADL-S. Combo phy port clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers. The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S translates to DDI A -> DDIA DDI B -> USBC1 DDI I -> USBC2 For DPCLKA_CFGCR1 DDI J -> USBC3 DDI K -> USBC4 Bspec: 50287 Bspec: 53812 Bspec: 53723 v2: Replace I915_READ() with intel_de_read().(Jani) v3: - Use reg variable to assign ADLS specific registers inorder to replace branching with intel_de_read/write() calls.(mdroper) - Reuse icl_get_ddi_pll() for ADLS to fix issue with updating active dpll on driver load.(aswarup) Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_ddi.c | 62 +++++++++++++------- drivers/gpu/drm/i915/display/intel_display.c | 11 +++- drivers/gpu/drm/i915/i915_reg.h | 23 +++++++- 3 files changed, 72 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d4c09a1aa06e..91d8e3cc0d9f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3160,25 +3160,30 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - u32 val; + u32 val, mask, sel; + i915_reg_t reg; + + if (IS_ALDERLAKE_S(dev_priv)) { + reg = ADLS_DPCLKA_CFGCR(phy); + mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy); + sel = ((pll->info->id) << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); + } else if (IS_ROCKETLAKE(dev_priv)) { + reg = ICL_DPCLKA_CFGCR0; + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } else { + reg = ICL_DPCLKA_CFGCR0; + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); + val = intel_de_read(dev_priv, reg); drm_WARN_ON(&dev_priv->drm, (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); if (intel_phy_is_combo(dev_priv, phy)) { - u32 mask, sel; - - if (IS_ROCKETLAKE(dev_priv)) { - mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - } else { - mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - } - /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -3191,12 +3196,12 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, */ val &= ~mask; val |= sel; - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); - intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); } val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); + intel_de_write(dev_priv, reg, val); mutex_unlock(&dev_priv->dpll.lock); } @@ -3219,12 +3224,19 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); u32 val; + i915_reg_t reg; mutex_lock(&dev_priv->dpll.lock); - val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); + if (IS_ALDERLAKE_S(dev_priv)) + reg = ADLS_DPCLKA_CFGCR(phy); + else + reg = ICL_DPCLKA_CFGCR0; + + val = intel_de_read(dev_priv, reg); val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); + + intel_de_write(dev_priv, reg, val); mutex_unlock(&dev_priv->dpll.lock); } @@ -3264,13 +3276,21 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, u32 port_mask, bool ddi_clk_needed) { enum port port; + bool ddi_clk_off; u32 val; + i915_reg_t reg; - val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); for_each_port_masked(port, port_mask) { enum phy phy = intel_port_to_phy(dev_priv, port); - bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, - phy); + + if (IS_ALDERLAKE_S(dev_priv)) + reg = ADLS_DPCLKA_CFGCR(phy); + else + reg = ICL_DPCLKA_CFGCR0; + + val = intel_de_read(dev_priv, reg); + ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, + phy); if (ddi_clk_needed == !ddi_clk_off) continue; @@ -3286,7 +3306,7 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", phy_name(phy)); val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); + intel_de_write(dev_priv, reg, val); } } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index acf06feffd3e..83ac0a7a59f0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8592,20 +8592,27 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_shared_dpll *pll; enum intel_dpll_id id; bool pll_active; + i915_reg_t reg; u32 temp; if (intel_phy_is_combo(dev_priv, phy)) { u32 mask, shift; - if (IS_ROCKETLAKE(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + reg = ADLS_DPCLKA_CFGCR(phy); + mask = ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy); + shift = ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy); + } else if (IS_ROCKETLAKE(dev_priv)) { + reg = ICL_DPCLKA_CFGCR0; mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); } else { + reg = ICL_DPCLKA_CFGCR0; mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); } - temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask; + temp = intel_de_read(dev_priv, reg) & mask; id = temp >> shift; port_dpll_id = ICL_PORT_DPLL_DEFAULT; } else if (intel_phy_is_tc(dev_priv, phy)) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 339532222d7c..6be725a9e46f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10356,7 +10356,7 @@ enum skl_power_gate { /* ICL Clocks */ #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) -#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ (tc_port) + 12 : \ @@ -10391,6 +10391,27 @@ enum skl_power_gate { #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_DPLL_MAP(clk_sel, phy) \ (((clk_sel) >> DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) + _DG1_PHY_DPLL_MAP(phy)) +/* ADLS Clocks */ +#define _ADLS_DPCLKA_CFGCR0 0x164280 +#define _ADLS_DPCLKA_CFGCR1 0x1642BC +#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ + _ADLS_DPCLKA_CFGCR0, \ + _ADLS_DPCLKA_CFGCR1) +#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) +/* ADLS DPCLKA_CFGCR0 DDI mask */ +#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) +#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) +#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) +/* ADLS DPCLKA_CFGCR1 DDI mask */ +#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) +#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) +#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ + ADLS_DPCLKA_DDIA_SEL_MASK, \ + ADLS_DPCLKA_DDIB_SEL_MASK, \ + ADLS_DPCLKA_DDII_SEL_MASK, \ + ADLS_DPCLKA_DDIJ_SEL_MASK, \ + ADLS_DPCLKA_DDIK_SEL_MASK) + /* CNL PLL */ #define DPLL0_ENABLE 0x46010 #define DPLL1_ENABLE 0x46014 From patchwork Mon Jan 25 14:07:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 12043539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33BE4C433DB for ; Mon, 25 Jan 2021 14:09:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ECC7122C9E for ; Mon, 25 Jan 2021 14:09:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ECC7122C9E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B4536E18F; Mon, 25 Jan 2021 14:08:57 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id DCB606E161 for ; Mon, 25 Jan 2021 14:08:51 +0000 (UTC) IronPort-SDR: 417JAU773IU5AGB6eZHVLTiyATk3BcKa9/7PTq8NCqo2w6flJuvEqjTCmyPnxulmWWMYD6EabS eeAmC5MpgusQ== X-IronPort-AV: E=McAfee;i="6000,8403,9874"; a="179879126" X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="179879126" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:35 -0800 IronPort-SDR: FavDwQXh0BaKLWRxjBje5mpHZd1/1/9H6YvVXChSM+jGafMvyTVEufxQ3Wfc7mLxG1/Nn98bVk mLtJQ5e7IVBw== X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="472319599" Received: from iduggana-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.81.9]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:34 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jan 2021 06:07:50 -0800 Message-Id: <20210125140753.347998-8-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210125140753.347998-1-aditya.swarup@intel.com> References: <20210125140753.347998-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/10] drm/i915/adl_s: Initialize display for ADL-S X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Initialize display outputs for ADL-S. ADL-S has 5 display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs. v2: - Use PORT_TCx instead of PORT_D,E.. to stay consistent with other platforms.(mdroper) Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 83ac0a7a59f0..eaec5cd1a144 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13897,7 +13897,13 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { + if (IS_ALDERLAKE_S(dev_priv)) { + intel_ddi_init(dev_priv, PORT_A); + intel_ddi_init(dev_priv, PORT_TC1); + intel_ddi_init(dev_priv, PORT_TC2); + intel_ddi_init(dev_priv, PORT_TC3); + intel_ddi_init(dev_priv, PORT_TC4); + } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); intel_ddi_init(dev_priv, PORT_TC1); From patchwork Mon Jan 25 14:07:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 12043541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F7ECC433E6 for ; Mon, 25 Jan 2021 14:09:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EBE2822C9E for ; Mon, 25 Jan 2021 14:09:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EBE2822C9E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B9326E198; Mon, 25 Jan 2021 14:08:57 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F6AE6E054 for ; Mon, 25 Jan 2021 14:08:52 +0000 (UTC) IronPort-SDR: kuRrXH0U9RJ2RWIHoamPgFfQTlynOKkj+59djLSvhCygEzFe+9hYYi+PBORzhuoNxYlxYrAcKe rgy1B+BEJfTA== X-IronPort-AV: E=McAfee;i="6000,8403,9874"; a="179879137" X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="179879137" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:36 -0800 IronPort-SDR: muUAMqlhSLnuXDZVMBp+LkJMQ8KEzsA4Iui5+CwvAfzslCKxvWGPuVOgaQrtOxZt6hD6xcJLc9 GdpNkFpJ255A== X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="472319610" Received: from iduggana-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.81.9]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:35 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jan 2021 06:07:51 -0800 Message-Id: <20210125140753.347998-9-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210125140753.347998-1-aditya.swarup@intel.com> References: <20210125140753.347998-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 08/10] drm/i915/adl_s: Add adl-s ddc pin mapping X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E. Combo PHY A still uses the old ddc pin mapping. From VBT, ddc pin info suggests the following mapping: VBT DRIVER DDI B->ddc_pin=2 should translate to PORT_D->0x9 DDI C->ddc_pin=3 should translate to PORT_E->0xa DDI D->ddc_pin=4 should translate to PORT_F->0xb DDI E->ddc_pin=5 should translate to PORT_G->0xc Adding pin map to facilitate this translation as we cannot use existing icl ddc pin map due to conflict with DDI B and DDI C info. Bspec:20124 v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing depends on the PCH being used rather than the platform.(mdroper) v3: - Modify adls_port_to_ddc_pin() to make PHY_A the special case for check, else return pin mapping based on correct arithmetic with phy offset. Remove redundant platform checks and use HAS_PCH_ADP() instead of IS_ALDERLAKE_S() in intel_hdmi_ddc_pin().(mdroper) Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_bios.c | 13 +++++++++++- drivers/gpu/drm/i915/display/intel_hdmi.c | 20 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 987cf509337f..e575e584e6d5 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1630,12 +1630,23 @@ static const u8 rkl_pch_tgp_ddc_pin_map[] = { [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP, }; +static const u8 adls_ddc_pin_map[] = { + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT, + [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP, + [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP, + [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP, + [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP, +}; + static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) { const u8 *ddc_pin_map; int n_entries; - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) { + if (HAS_PCH_ADP(dev_priv)) { + ddc_pin_map = adls_ddc_pin_map; + n_entries = ARRAY_SIZE(adls_ddc_pin_map); + } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) { return vbt_pin; } else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) { ddc_pin_map = rkl_pch_tgp_ddc_pin_map; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index d5f4b40a8460..66e1ac3887c6 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3138,6 +3138,22 @@ static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return intel_port_to_phy(dev_priv, port) + 1; } +static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +{ + enum phy phy = intel_port_to_phy(dev_priv, port); + + WARN_ON(port == PORT_B || port == PORT_C); + + /* + * Pin mapping for ADL-S requires TC pins for all combo phy outputs + * except first combo output. + */ + if (phy == PHY_A) + return GMBUS_PIN_1_BXT; + + return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; +} + static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { @@ -3175,7 +3191,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) return ddc_pin; } - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + if (HAS_PCH_ADP(dev_priv)) + ddc_pin = adls_port_to_ddc_pin(dev_priv, port); + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); else if (IS_ROCKETLAKE(dev_priv)) ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 187ec573de59..6d10fa037751 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -327,6 +327,10 @@ enum vbt_gmbus_ddi { ICL_DDC_BUS_PORT_4, TGL_DDC_BUS_PORT_5, TGL_DDC_BUS_PORT_6, + ADLS_DDC_BUS_PORT_TC1 = 0x2, + ADLS_DDC_BUS_PORT_TC2, + ADLS_DDC_BUS_PORT_TC3, + ADLS_DDC_BUS_PORT_TC4 }; #define DP_AUX_A 0x40 From patchwork Mon Jan 25 14:07:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 12043543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E2C3C433E0 for ; Mon, 25 Jan 2021 14:09:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E402622C9E for ; Mon, 25 Jan 2021 14:09:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E402622C9E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ADC196E1A4; Mon, 25 Jan 2021 14:08:57 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6FAC16E161 for ; Mon, 25 Jan 2021 14:08:52 +0000 (UTC) IronPort-SDR: oiWnmjGIReCwwLaHdxvnnau03bSb5u3noMH/sbQwdBa/qzyA73BRC4e6vEjRZWnp2qvN9LMO0y 4x8DA4LvvMMw== X-IronPort-AV: E=McAfee;i="6000,8403,9874"; a="179879140" X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="179879140" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:37 -0800 IronPort-SDR: 7XL+hfJSEO+8RFWFOLGlV3ID+0vHmRaZEafxA6fVw2lIDYT8+yD+HG9HTO46y0pPo3xYFEd15S TtoYN6vA7PVQ== X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="472319615" Received: from iduggana-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.81.9]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:37 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jan 2021 06:07:52 -0800 Message-Id: <20210125140753.347998-10-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210125140753.347998-1-aditya.swarup@intel.com> References: <20210125140753.347998-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 09/10] drm/i915/adl_s: Add vbt port and aux channel settings for adls X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" - ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E. - Add ADLS specific port mappings for vbt port dvo settings. - Select appropriate AUX CH specific to ADLS based on port mapping. Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_bios.c | 57 ++++++++++++++++++----- 1 file changed, 46 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index e575e584e6d5..04337ac6f8c4 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1719,8 +1719,26 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv, [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, }; + /* + * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E, + * PORT_F and PORT_G, we need to map that to correct VBT sections. + */ + static const int adls_port_mapping[][3] = { + [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, + [PORT_B] = { -1 }, + [PORT_C] = { -1 }, + [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, + [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, + [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, + [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 }, + }; - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + if (IS_ALDERLAKE_S(dev_priv)) + return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping), + ARRAY_SIZE(adls_port_mapping[0]), + adls_port_mapping, + dvo_port); + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), ARRAY_SIZE(rkl_port_mapping[0]), rkl_port_mapping, @@ -2672,27 +2690,44 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, return aux_ch; } + /* + * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D + * map to DDI A,B,TC1,TC2 respectively. + * + * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E + * map to DDI A,TC1,TC2,TC3,TC4 respectively. + */ switch (info->alternate_aux_channel) { case DP_AUX_A: aux_ch = AUX_CH_A; break; case DP_AUX_B: - aux_ch = AUX_CH_B; + if (IS_ALDERLAKE_S(dev_priv)) + aux_ch = AUX_CH_USBC1; + else + aux_ch = AUX_CH_B; break; case DP_AUX_C: - /* - * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D - * map to DDI A,B,TC1,TC2 respectively. - */ - aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ? - AUX_CH_USBC1 : AUX_CH_C; + if (IS_ALDERLAKE_S(dev_priv)) + aux_ch = AUX_CH_USBC2; + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + aux_ch = AUX_CH_USBC1; + else + aux_ch = AUX_CH_C; break; case DP_AUX_D: - aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ? - AUX_CH_USBC2 : AUX_CH_D; + if (IS_ALDERLAKE_S(dev_priv)) + aux_ch = AUX_CH_USBC3; + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + aux_ch = AUX_CH_USBC2; + else + aux_ch = AUX_CH_D; break; case DP_AUX_E: - aux_ch = AUX_CH_E; + if (IS_ALDERLAKE_S(dev_priv)) + aux_ch = AUX_CH_USBC4; + else + aux_ch = AUX_CH_E; break; case DP_AUX_F: aux_ch = AUX_CH_F; From patchwork Mon Jan 25 14:07:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aditya Swarup X-Patchwork-Id: 12043545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3726C433E6 for ; Mon, 25 Jan 2021 14:09:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC18522C9E for ; Mon, 25 Jan 2021 14:09:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BC18522C9E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CFA46E196; Mon, 25 Jan 2021 14:08:57 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D6B8F6E054 for ; Mon, 25 Jan 2021 14:08:53 +0000 (UTC) IronPort-SDR: u379G1K5vH2K4x2XZRjs8mS+qDtS0/eaOtQe9ZZOo1sZX8iGWpUL7LOLrrEUjiDKiP9aJyzFBW L8E6pMOzfvQA== X-IronPort-AV: E=McAfee;i="6000,8403,9874"; a="179879145" X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="179879145" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:38 -0800 IronPort-SDR: Gg6CdPDc9TJA2lF6NHkcS8aDDoEwV1OqCl3wtwLMEJSXqG+klprk58hNVMhPMrva9Ewbk0JKft tVbNK5R50ezw== X-IronPort-AV: E=Sophos;i="5.79,373,1602572400"; d="scan'208";a="472319620" Received: from iduggana-mobl.amr.corp.intel.com (HELO aswarup-mobl.amr.corp.intel.com) ([10.254.81.9]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2021 06:08:38 -0800 From: Aditya Swarup To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jan 2021 06:07:53 -0800 Message-Id: <20210125140753.347998-11-aditya.swarup@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210125140753.347998-1-aditya.swarup@intel.com> References: <20210125140753.347998-1-aditya.swarup@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 10/10] drm/i915/adl_s: Update combo PHY master/slave relationships X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper ADL-S switches up which PHYs are considered a master to other PHYs; PHY-C is no longer a master, but PHY-D is now. Bspec: 49291 Cc: Jani Nikula Cc: Ville Syrjälä Cc: Imre Deak Cc: Lucas De Marchi Signed-off-by: Matt Roper Signed-off-by: Aditya Swarup Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 996ae0608a62..dd45cbafcf42 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -246,14 +246,21 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) * RKL,DG1: * A(master) -> B(slave) * C(master) -> D(slave) + * ADL-S: + * A(master) -> B(slave), C(slave) + * D(master) -> E(slave) * * We must set the IREFGEN bit for any PHY acting as a master * to another PHY. */ - if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C) + if (phy == PHY_A) return true; + else if (IS_ALDERLAKE_S(dev_priv)) + return phy == PHY_D; + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + return phy == PHY_C; - return phy == PHY_A; + return false; } static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,