From patchwork Wed Jan 27 07:48:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. 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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id k5sm367349ljg.119.2021.01.26.23.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jan 2021 23:48:52 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PULL v1 1/3] target/microblaze: Add use-non-secure property Date: Wed, 27 Jan 2021 08:48:48 +0100 Message-Id: <20210127074850.1886235-2-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210127074850.1886235-1-edgar.iglesias@gmail.com> References: <20210127074850.1886235-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, joe.komlodi@xilinx.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Joe Komlodi This property is used to control the security of the following interfaces on MicroBlaze: M_AXI_DP - data interface M_AXI_IP - instruction interface M_AXI_DC - dcache interface M_AXI_IC - icache interface It works by enabling or disabling the use of the non_secure[3:0] signals. Interfaces and their corresponding values are taken from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-vivado-microblaze-ref.pdf page 153. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-Id: <1611274735-303873-2-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 11 ++++++++++ target/microblaze/cpu.c | 46 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index c1c264199f..199cfb02d6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -233,6 +233,12 @@ typedef struct CPUMBState CPUMBState; #define TARGET_INSN_START_EXTRA_WORDS 1 +/* use-non-secure property masks */ +#define USE_NON_SECURE_M_AXI_DP_MASK 0x1 +#define USE_NON_SECURE_M_AXI_IP_MASK 0x2 +#define USE_NON_SECURE_M_AXI_DC_MASK 0x4 +#define USE_NON_SECURE_M_AXI_IC_MASK 0x8 + struct CPUMBState { uint32_t bvalue; /* TCG temporary, only valid during a TB */ uint32_t btarget; /* Full resolved branch destination */ @@ -316,6 +322,7 @@ typedef struct { bool use_msr_instr; bool use_pcmp_instr; bool use_mmu; + uint8_t use_non_secure; bool dcache_writeback; bool endi; bool dopb_bus_exception; @@ -337,6 +344,10 @@ struct MicroBlazeCPU { CPUState parent_obj; /*< public >*/ + bool ns_axi_dp; + bool ns_axi_ip; + bool ns_axi_dc; + bool ns_axi_ic; CPUNegativeOffsetState neg; CPUMBState env; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c8e754cfb1..accfb23a4f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -98,6 +98,38 @@ static bool mb_cpu_has_work(CPUState *cs) } #ifndef CONFIG_USER_ONLY +static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu = opaque; + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; + + cpu->ns_axi_dp = level & en; +} + +static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu = opaque; + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; + + cpu->ns_axi_ip = level & en; +} + +static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu = opaque; + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; + + cpu->ns_axi_dc = level & en; +} + +static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu = opaque; + bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; + + cpu->ns_axi_ic = level & en; +} + static void microblaze_cpu_set_irq(void *opaque, int irq, int level) { MicroBlazeCPU *cpu = opaque; @@ -248,6 +280,10 @@ static void mb_cpu_initfn(Object *obj) #ifndef CONFIG_USER_ONLY /* Inbound IRQ and FIR lines */ qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); + qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); #endif } @@ -277,6 +313,16 @@ static Property mb_properties[] = { DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), + /* + * use-non-secure enables/disables the use of the non_secure[3:0] signals. + * It is a bitfield where 1 = non-secure for the following bits and their + * corresponding interfaces: + * 0x1 - M_AXI_DP + * 0x2 - M_AXI_IP + * 0x4 - M_AXI_DC + * 0x8 - M_AXI_IC + */ + DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), From patchwork Wed Jan 27 07:48:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 12049179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31CEFC433DB for ; Wed, 27 Jan 2021 07:50:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AC0D820724 for ; Wed, 27 Jan 2021 07:50:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AC0D820724 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:57066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l4fb2-0007g8-II for qemu-devel@archiver.kernel.org; Wed, 27 Jan 2021 02:50:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60246) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l4fZR-0006N9-6O for qemu-devel@nongnu.org; Wed, 27 Jan 2021 02:48:57 -0500 Received: from mail-lj1-x234.google.com ([2a00:1450:4864:20::234]:44409) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l4fZP-0008FN-LK for qemu-devel@nongnu.org; Wed, 27 Jan 2021 02:48:56 -0500 Received: by mail-lj1-x234.google.com with SMTP id f2so948371ljp.11 for ; Tue, 26 Jan 2021 23:48:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4QBhtqx+2zYsT5bsd6WKN1cKWd33wvJhacw+yaeEiU8=; b=MSK/AAgRs6yr8Qb4OxcjZX4T9Av/dg2UDIntCkjaKrZozSxUKemz98uscsq7dPVXp3 QOBTYwu0umabi3Fi62bKYWz+aLMvW15In2sFrRXztOxL8N/Ml4Yw1CO5Hp45uaVsWBW1 WMdFeJt7UG3T9Ba4EyG7vPzTGRFOvevdt0MrfRUOd3XW0u2AwjKBmMYUOpY3eqmiz2Ju FQLfnWaiNRi3VWrrkFBMxdwp7y2QEj/x7vQGh8vMnOw7V8KxickMe8hj7Fd2mznEy8LF IY78WuLaDZrslvPkb144V9pJiT1GpTfCnZys5CozJ+gnTwwJDPpr72bLJvmEuPjZEdxP NdKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4QBhtqx+2zYsT5bsd6WKN1cKWd33wvJhacw+yaeEiU8=; b=euYsQWe8BBlWRFsgT4gzNaw/J6Hkmyworg3dDOu3mH2bA+VUjsWQTCu5Fv2SftzS9l UP6D+PDh2ncg7xWc50jGFy0paSA/YFLX5Q8rT9tTZ5SeehePzgcKAAXJr2m4OnKedZz/ vlWaX8XG5dy5jRiQwItrxI+D/9EECAnT2a7zbf+IWJAMe8M5+f8SElSt73d6/Fc1Rzyb cenXQir5HJQ8QGYpMl5HKo+RWKISr9Rx/nHjm7otEg9MWkfK5o4HkKL5SXaUNHwMfekj s5+NG1mf076Js67RO7cBXwbaTjhrDb2D8mRmTla+WCpwIRZ0jYXDVT1p66WDLnDhzgCZ s7vw== X-Gm-Message-State: AOAM531p9zBf6qVC3UxPVXju9yG9I/7bYkHPf5442QL15+PQ0FfyqgZC vr+aB7neyiQSvYS3/kKUdRLRaRe3YrY= X-Google-Smtp-Source: ABdhPJztFTvxw+I/pD6DahbG2YDST3pZfna+j3O7NJDHVHJjf4ko7CtBiVUNZLHD/h7JQh8vHAArbg== X-Received: by 2002:a2e:9d96:: with SMTP id c22mr5056523ljj.109.1611733733969; Tue, 26 Jan 2021 23:48:53 -0800 (PST) Received: from gmail.com (81-231-232-130-no39.tbcn.telia.com. [81.231.232.130]) by smtp.gmail.com with ESMTPSA id n8sm359789ljj.116.2021.01.26.23.48.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jan 2021 23:48:53 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PULL v1 2/3] target/microblaze: use MMUAccessType instead of int in mmu_translate Date: Wed, 27 Jan 2021 08:48:49 +0100 Message-Id: <20210127074850.1886235-3-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210127074850.1886235-1-edgar.iglesias@gmail.com> References: <20210127074850.1886235-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, joe.komlodi@xilinx.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Joe Komlodi Using MMUAccessType makes it more clear what the variable's use is. No functional change. Signed-off-by: Joe Komlodi Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-Id: <1611274735-303873-3-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/mmu.h | 2 +- target/microblaze/mmu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 09e4075739..b6b4b9ad60 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -84,7 +84,7 @@ typedef struct { } MicroBlazeMMULookup; unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, - target_ulong vaddr, int rw, int mmu_idx); + target_ulong vaddr, MMUAccessType rw, int mmu_idx); uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v); void mmu_init(MicroBlazeMMU *mmu); diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 1e426963ba..cc40f275ea 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -74,7 +74,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid) /* rw - 0 = read, 1 = write, 2 = fetch. */ unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, - target_ulong vaddr, int rw, int mmu_idx) + target_ulong vaddr, MMUAccessType rw, int mmu_idx) { MicroBlazeMMU *mmu = &cpu->env.mmu; unsigned int i, hit = 0; From patchwork Wed Jan 27 07:48:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. 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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id e7sm304252lfs.159.2021.01.26.23.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jan 2021 23:48:54 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PULL v1 3/3] target/microblaze: Add security attributes on memory transactions Date: Wed, 27 Jan 2021 08:48:50 +0100 Message-Id: <20210127074850.1886235-4-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210127074850.1886235-1-edgar.iglesias@gmail.com> References: <20210127074850.1886235-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, joe.komlodi@xilinx.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Joe Komlodi Using the cfg.use_non_secure bitfield and the MMU access type, we can determine if the access should be secure or not. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-Id: <1611274735-303873-4-git-send-email-komlodi@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 3 ++- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 26 +++++++++++++++++++++++--- 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 199cfb02d6..e4bba8a755 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -361,7 +361,8 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index accfb23a4f..d5e8bfe11f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -375,7 +375,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->tlb_fill = mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed = mb_cpu_transaction_failed; - cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; + cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug; dc->vmsd = &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index cda14a14be..20dbd67313 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -46,6 +46,16 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #else /* !CONFIG_USER_ONLY */ +static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, + MMUAccessType access_type) +{ + if (access_type == MMU_INST_FETCH) { + return !cpu->ns_axi_ip; + } else { + return !cpu->ns_axi_dp; + } +} + bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -55,12 +65,16 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MicroBlazeMMULookup lu; unsigned int hit; int prot; + MemTxAttrs attrs = {}; + + attrs.secure = mb_cpu_access_is_secure(cpu, access_type); if (mmu_idx == MMU_NOMMU_IDX) { /* MMU disabled or not available. */ address &= TARGET_PAGE_MASK; prot = PAGE_BITS; - tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, + TARGET_PAGE_SIZE); return true; } @@ -71,7 +85,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, + TARGET_PAGE_SIZE); return true; } @@ -230,7 +245,8 @@ void mb_cpu_do_interrupt(CPUState *cs) } } -hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, + MemTxAttrs *attrs) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; @@ -239,6 +255,10 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int mmu_idx = cpu_mmu_index(env, false); unsigned int hit; + /* Caller doesn't initialize */ + *attrs = (MemTxAttrs) {}; + attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); + if (mmu_idx != MMU_NOMMU_IDX) { hit = mmu_translate(cpu, &lu, addr, 0, 0); if (hit) {