From patchwork Sat Jan 30 01:52:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12056723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4841C433E6 for ; Sat, 30 Jan 2021 01:56:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 82A6464E0C for ; Sat, 30 Jan 2021 01:56:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233110AbhA3BzC (ORCPT ); Fri, 29 Jan 2021 20:55:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232798AbhA3BxV (ORCPT ); Fri, 29 Jan 2021 20:53:21 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C066FC06174A for ; Fri, 29 Jan 2021 17:52:36 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id g10so10624810wrx.1 for ; Fri, 29 Jan 2021 17:52:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TWOO2zfu8P4UM754zwKeQRqNcelSJ+Vi3BwaB87IrgI=; b=EZ4R0A6K45GJEpt3ikVxK/mZ5uOp/qSvLKwjO7LS5PbjeX+3sWdmNlr+4p56lnPtqL CUdY1yW1rTe7NWAKG6FtSRNNZKnZUAI2VEHfT9t/GySrE8ds9BQbysvGJYiW2faVZNpm DGZ+2ZzDYpOjHkDu0jST31KidNc+L9/fohOoZJZMRjKENmO2boj+1Bne8nOdoKsZZOk2 hms4LiJZ9snctfQC29BzW0EhHYsmNCX7dzY+CxfZJyC29i8WBBxcI2hmd0NS7su5sU/F vCixTZjkQ3F8hOmBQQBzuo5d3mfiya1x/ZzCDk9XbkWe7CW7UiXUFmxJzINuRhOtpEh6 vHGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=TWOO2zfu8P4UM754zwKeQRqNcelSJ+Vi3BwaB87IrgI=; b=CbN8iVsVgsaJMV15gM3hgmUA3LHo514arjKMVZctXaQIhp26L69dQH45Vhqkb7BD/X NjiNYn8C6BzUpBzQ+ofZFf25vJS1jycaObQqDauLUBCsdfLK7/ki7SOXOleTdsRmIMrT SzeO5GhDUBeH1M50KViTYOlGdvA3PrmqWLfHdPlB+iMZURAGGQgBp5+ohxPbm5ZO3AkP Uqtr1hY+twv2W2USymj36kz9eIYiu8gGb6VccT74le2D2SO3iyparAYT+bTch1uJlg2u N0s1FgRnZ3KQ0jq6xbhfluLRTacNobKsNtjDEc6rUkzWeOQFqaMIBavvNM3sUIPVnshs RiQw== X-Gm-Message-State: AOAM533MUKJigGXr4rsY3cZ/HyUTqnbgpbee3rdn7x2HYAf+rCoEqLcu GM3kk0Yh4jnYoNOK8FEND7Y= X-Google-Smtp-Source: ABdhPJwm3L7bSc0x4zKW4ljahz5/V9fkUWnJDpwudDy2IcbG2e/6dOTMtKI7Na8SK+4UY4kLg/lEbg== X-Received: by 2002:adf:e4c9:: with SMTP id v9mr7191301wrm.277.1611971555621; Fri, 29 Jan 2021 17:52:35 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id u14sm11707719wml.19.2021.01.29.17.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:35 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 01/11] exec: Restrict TCG specific headers Date: Sat, 30 Jan 2021 02:52:17 +0100 Message-Id: <20210130015227.4071332-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Fixes when building with --disable-tcg: In file included from target/arm/helper.c:16: include/exec/helper-proto.h:42:10: fatal error: tcg-runtime.h: No such file or directory 42 | #include "tcg-runtime.h" | ^~~~~~~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé --- include/exec/helper-proto.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h index 659f9298e8f..740bff3bb4d 100644 --- a/include/exec/helper-proto.h +++ b/include/exec/helper-proto.h @@ -39,8 +39,10 @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ #include "helper.h" #include "trace/generated-helpers.h" +#ifdef CONFIG_TCG #include "tcg-runtime.h" #include "plugin-helpers.h" +#endif /* CONFIG_TCG */ #undef IN_HELPER_PROTO From patchwork Sat Jan 30 01:52:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12056727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A947C433DB for ; Sat, 30 Jan 2021 01:57:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5037D64E0A for ; Sat, 30 Jan 2021 01:57:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233024AbhA3B4i (ORCPT ); Fri, 29 Jan 2021 20:56:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232852AbhA3BxY (ORCPT ); Fri, 29 Jan 2021 20:53:24 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4A7EC061756 for ; Fri, 29 Jan 2021 17:52:41 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id m1so5253344wml.2 for ; Fri, 29 Jan 2021 17:52:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G9dNmRIohMTgXAElzkQ+lpMLRmxhHG61au1rY6dJdIw=; b=PEjpazXUgk6kR6UqDmwU45UySoXQLcz5AUjh6P8ScUgFkBsPisn+Tm/qm9hBMUWlxU bXEcLJ8UugY9aEVPQbo6p4m/Hux6j9xRlGgX4nFBl3CdGdq2BBIrSjLEO86Z4aoFc8pO sOUDNxqSQ0sq11WskYH43JUY8ipQhlYj/w/bYvz/VXaBRpbw+O5FYEX3aiwba24dV37x eXoZz8Ukp5kBBqvvXXbiR7M0vIrCWLxvkVDzdRwwembHyYCl3SSmuG6HSoiE25+STMef fVEoHq1XKPD0QMR5koqBX/Yf7PEsrpn+QnhlP/GxxXqA9IDdom/mYPcwNcgu4Y2ATxaQ whbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=G9dNmRIohMTgXAElzkQ+lpMLRmxhHG61au1rY6dJdIw=; b=t797YXQ8PaLabsOW/Ok8Fn+ASCaaR437TOaUmAYVt9e2LFsQE2+sY4PrRuy/sWu6rU hWWXQUxBD0JNZeK4OtWKcJ2DgPK8z7YpHRvOxssJBmUOhDY7TGaFE/sBvJ3CMUThVQHY XJoCoBVw7murg/+2FU8w1tVb7OeLcfFuQlarJtBIj+5OfpV+o9v4diEI6C/zbKGwN5ZN bdBw/BZg9UPdS5O2jLvF8iWUKXZfDTKgAOLX1iCvCp7ACKGspysh/XJYvPk7DyrRORyv R3ieDQqbE9uBNmjY3Homjo9TfzhiwFkBC33olN2eNC1yahhMIHYYx/E0reNUW0VKAe8p l3+Q== X-Gm-Message-State: AOAM530G1ow1yPO1UEfaGgyHQTqq8WhFQYk3uWaz3UtlXK/gavu/03De ADk3YeAFlOflZWJ0z3cxpys= X-Google-Smtp-Source: ABdhPJwskto+f53o9TCaynYuVK8iQ1uBoTdTN+CKWcrz2acq5nnSN55h/BCj1DXRiUJLZD6Cr+Hp6Q== X-Received: by 2002:a1c:21c6:: with SMTP id h189mr5786718wmh.173.1611971560647; Fri, 29 Jan 2021 17:52:40 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id w126sm12485133wma.43.2021.01.29.17.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:40 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 02/11] default-configs: Remove unnecessary SEMIHOSTING selection Date: Sat, 30 Jan 2021 02:52:18 +0100 Message-Id: <20210130015227.4071332-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Commit 56b5170c87e ("semihosting: Move ARM semihosting code to shared directories") selected ARM_COMPATIBLE_SEMIHOSTING which already selects SEMIHOSTING. No need to select it again. Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 1 - 1 file changed, 1 deletion(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 0500156a0c7..341d439de6f 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -41,6 +41,5 @@ CONFIG_MICROBIT=y CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y -CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y CONFIG_ALLWINNER_H3=y From patchwork Sat Jan 30 01:52:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12057041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC56BC433E0 for ; Sat, 30 Jan 2021 10:13:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 91AAE64DDD for ; Sat, 30 Jan 2021 10:13:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231543AbhA3KMi (ORCPT ); Sat, 30 Jan 2021 05:12:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232863AbhA3Bx2 (ORCPT ); Fri, 29 Jan 2021 20:53:28 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 108CEC0613D6 for ; Fri, 29 Jan 2021 17:52:47 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id m1so5253411wml.2 for ; Fri, 29 Jan 2021 17:52:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vcCVSF3XdYkCqqZi7utKwViQKx4YjOvtKjolDPxsZVA=; b=uuOQE2bVc/AXhQEPhQ6gdsToWOMtR7/LcnPqZ5MlFP7kxA9NkXZRlPLIuIGcDAICaH ssfdEX74NQKHWvbMKF1O0arKgDrgBDsd8FqdoI/5wNZzzclE5eRj9Kpm6bGoGr5+cZdI Jg5zG6cmCMmNVfGLW3zUisi7sd7SUqp60e7Hpum16Q1olADlzRwBFv2K8f8X18j8D47y 58iyx4+nB5prF66v4obJKkL3bwkP1u0ZTkyuBYVj1LfX8505z2oyoDPPp1zNI+EnKisD o5O/sJHYTlK/TxPX7i+7nbbtSy/f7B6U9/cTk8WL2l7kXtk/9VzZhNismcBX99UrM8es TVZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vcCVSF3XdYkCqqZi7utKwViQKx4YjOvtKjolDPxsZVA=; b=QA29OcpEEUKi8Wx4sA8Gzwf6e6L6tjDTXBPNyz8XWqgr6w8OLPuTsbAbf3VNf41lQW 1gCQMR271XXk75dEndR+uiAigsgLJDydRo/4y3C7K1/CyU5WhNuxNVFyhVvSgNu6OUQB ySPKTCngeKVQwSmmEwlZIM9Cajp0QBDCNbm8CBtX5dvo/xUI7dp+6CMSyg8MdDakcg2u OfzDnx4ehw2gE1pCl11cwcxRqVIKgWoPQ7fqFSXUIJX9Rt2HEZZSC32+Z8IDw2cuKpW1 aBdaEc/V5dGZaJSwc7z/99smTysDx8wsVg/L0oyWhPVlmf7iagQtG2K1JDRAHiEuCo1H nS2A== X-Gm-Message-State: AOAM533QSAdJdF4Um27yga41r8az53Xu3lzho4CSbPjCxtO7uZ+94Nm1 nU/bprJqCPDLWB/E/PP8XJ8= X-Google-Smtp-Source: ABdhPJxjjNgvntexhnAMkjHR5dHZDBe4a6Ehpw1OZ8B2xG9qLvuQMF7WDg1InhxkhCshzCAD0AspzA== X-Received: by 2002:a05:600c:154f:: with SMTP id f15mr6167686wmg.46.1611971565884; Fri, 29 Jan 2021 17:52:45 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id b4sm15215041wrn.12.2021.01.29.17.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:45 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 03/11] target/arm: Restrict ARMv4 cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:19 +0100 Message-Id: <20210130015227.4071332-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv4 CPUs when TCG is available: - StrongARM (SA1100/1110) - OMAP1510 (TI925T) The following machines are no more built when TCG is disabled: - cheetah Palm Tungsten|E aka. Cheetah PDA (OMAP310) - sx1 Siemens SX1 (OMAP310) V2 - sx1-v1 Siemens SX1 (OMAP310) V1 Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 2 -- hw/arm/Kconfig | 8 ++++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 341d439de6f..8a53e637d23 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -14,8 +14,6 @@ CONFIG_INTEGRATOR=y CONFIG_FSL_IMX31=y CONFIG_MUSICPAL=y CONFIG_MUSCA=y -CONFIG_CHEETAH=y -CONFIG_SX1=y CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 223016bb4e8..7126d82f6ce 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -1,3 +1,7 @@ +config ARM_V4 + bool + depends on TCG + config ARM_VIRT bool imply PCI_DEVICES @@ -31,6 +35,8 @@ config ARM_VIRT config CHEETAH bool + default y if TCG + select ARM_V4 select OMAP select TSC210X @@ -249,6 +255,8 @@ config COLLIE config SX1 bool + default y if TCG + select ARM_V4 select OMAP config VERSATILE From patchwork Sat Jan 30 01:52:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12057043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BDDDC433E6 for ; Sat, 30 Jan 2021 10:13:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5F92864DE4 for ; Sat, 30 Jan 2021 10:13:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231897AbhA3KM0 (ORCPT ); Sat, 30 Jan 2021 05:12:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232948AbhA3Bxn (ORCPT ); Fri, 29 Jan 2021 20:53:43 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C040C0613ED for ; Fri, 29 Jan 2021 17:52:52 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id c12so10628066wrc.7 for ; Fri, 29 Jan 2021 17:52:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AIZXZm6d3zsn85EInNhmu0X2HUAdFADt4XuIzrFLo50=; b=JK8OynKD3b/XAd5IOwUaUSZL3h4xFiIGScxh9ajv5/hQv6fFGA3IGW1/DMnBKeMEQR V3Z7hOTVfKN2RLjfn4xgBUhXwjsLFgcrhcbIDR6RRYnAQMbIE9Gz5RCA+F1/TMWz9cOZ Bwv00xaAhqk7mModnA5Lr6pCL3wGAAp126InW50Cd6hGDw/HEENn2Ja7C5ZTrj+jcLSI XTaaejU/NLcaGoCMIASY8BEf1xCRMqDHecP5kpRE7Zp17pL/Fqg0glrRaOUtPbIeKTmT NbY3B3Q9Xqy+/KmZdi0fxeVK2x9/V/vK39DNKtK2hKk7ke3Hdy3d+Q/MJ3HipcXuDAG0 Q4zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=AIZXZm6d3zsn85EInNhmu0X2HUAdFADt4XuIzrFLo50=; b=hQLmZxY9s4pRP3aOOun5ofjODYf3zsc2p1p9xy0LDS7/ra1QdbihUgXcpu3eKc9eCp faC6lVPOrxqT3ShuoJR8YHR5zQ/bZZJiiY7sIbGYlD/3eoqkQYwXIgKDmTrLlOqF4Obo pYwr4R0mPSRGbF8FaZdoJo7AKMLdWRCFF6WAWalS2dhcz6C/hkbUtnjNioMbA2jZOlDn PadWbP7nlahCZntjxdxpDNExIGMjexufw4oLvIOtylLwwwr8AXVkmtKymlCrESUfM8Zh 7WqUM8vUJMb8Oi0XeJ/1MN8cbjwTuxyNE20e5A0+IyL9TqQPnyJo0q/wwdkru7ModrlJ m4Rw== X-Gm-Message-State: AOAM531EvbfnAcvaEbzsQo1YhyryZSS3C1s/XvL7lmtU2jmoo18jUkJ2 VD8S0cj05Jmo1hOnXle2n5g= X-Google-Smtp-Source: ABdhPJyG3IfNKn92dIJ/BqxY8b6yA8upkz3X+oX15/dbRXoTtTOXkskldv0xqkOnW90v7URAiwFqRw== X-Received: by 2002:a5d:40c5:: with SMTP id b5mr7441592wrq.121.1611971570862; Fri, 29 Jan 2021 17:52:50 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id u6sm15859725wro.75.2021.01.29.17.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:50 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 04/11] target/arm: Restrict ARMv5 cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:20 +0100 Message-Id: <20210130015227.4071332-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv5 CPUs when TCG is available: - ARM926 - ARM946 - ARM1026 - XScale (PXA250/255/260/261/262/270) The following machines are no more built when TCG is disabled: - akita Sharp SL-C1000 (Akita) PDA (PXA270) - ast2500-evb Aspeed AST2500 EVB (ARM1176) - ast2600-evb Aspeed AST2600 EVB (Cortex A7) - borzoi Sharp SL-C3100 (Borzoi) PDA (PXA270) - canon-a1100 Canon PowerShot A1100 IS - collie Sharp SL-5500 (Collie) PDA (SA-1110) - connex Gumstix Connex (PXA255) - g220a-bmc Bytedance G220A BMC (ARM1176) - imx25-pdk ARM i.MX25 PDK board (ARM926) - integratorcp ARM Integrator/CP (ARM926EJ-S) - mainstone Mainstone II (PXA27x) - musicpal Marvell 88w8618 / MusicPal (ARM926EJ-S) - palmetto-bmc OpenPOWER Palmetto BMC (ARM926EJ-S) - realview-eb ARM RealView Emulation Baseboard (ARM926EJ-S) - romulus-bmc OpenPOWER Romulus BMC (ARM1176) - sonorapass-bmc OCP SonoraPass BMC (ARM1176) - spitz Sharp SL-C3000 (Spitz) PDA (PXA270) - supermicrox11-bmc Supermicro X11 BMC (ARM926EJ-S) - swift-bmc OpenPOWER Swift BMC (ARM1176) - tacoma-bmc OpenPOWER Tacoma BMC (Cortex A7) - terrier Sharp SL-C3200 (Terrier) PDA (PXA270) - tosa Sharp SL-6000 (Tosa) PDA (PXA255) - verdex Gumstix Verdex (PXA270) - versatileab ARM Versatile/AB (ARM926EJ-S) - versatilepb ARM Versatile/PB (ARM926EJ-S) - witherspoon-bmc OpenPOWER Witherspoon BMC (ARM1176) - z2 Zipit Z2 (PXA27x) Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 12 ------------ hw/arm/realview.c | 5 ++++- hw/arm/Kconfig | 23 +++++++++++++++++++++++ 3 files changed, 27 insertions(+), 13 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 8a53e637d23..5b25fafc9ab 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -10,33 +10,21 @@ CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y CONFIG_HIGHBANK=y -CONFIG_INTEGRATOR=y CONFIG_FSL_IMX31=y -CONFIG_MUSICPAL=y CONFIG_MUSCA=y CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y -CONFIG_VERSATILE=y CONFIG_VEXPRESS=y CONFIG_ZYNQ=y -CONFIG_MAINSTONE=y -CONFIG_GUMSTIX=y -CONFIG_SPITZ=y -CONFIG_TOSA=y -CONFIG_Z2=y CONFIG_NPCM7XX=y -CONFIG_COLLIE=y -CONFIG_ASPEED_SOC=y CONFIG_NETDUINO2=y CONFIG_NETDUINOPLUS2=y CONFIG_MPS2=y CONFIG_RASPI=y -CONFIG_DIGIC=y CONFIG_SABRELITE=y CONFIG_EMCRAFT_SF2=y CONFIG_MICROBIT=y -CONFIG_FSL_IMX25=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 0831159d158..cd37b501287 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -18,6 +18,7 @@ #include "hw/pci/pci.h" #include "net/net.h" #include "sysemu/sysemu.h" +#include "sysemu/tcg.h" #include "hw/boards.h" #include "hw/i2c/i2c.h" #include "exec/address-spaces.h" @@ -460,7 +461,9 @@ static const TypeInfo realview_pbx_a9_type = { static void realview_machine_init(void) { - type_register_static(&realview_eb_type); + if (tcg_enabled()) { + type_register_static(&realview_eb_type); + } type_register_static(&realview_eb_mpcore_type); type_register_static(&realview_pb_a8_type); type_register_static(&realview_pbx_a9_type); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7126d82f6ce..bdb8c63af7b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -2,6 +2,10 @@ config ARM_V4 bool depends on TCG +config ARM_V5 + bool + depends on TCG + config ARM_VIRT bool imply PCI_DEVICES @@ -46,6 +50,8 @@ config CUBIEBOARD config DIGIC bool + default y if TCG + select ARM_V5 select PTIMER select PFLASH_CFI02 @@ -76,6 +82,8 @@ config HIGHBANK config INTEGRATOR bool + default y if TCG + select ARM_V5 select ARM_TIMER select INTEGRATOR_DEBUG select PL011 # UART @@ -88,6 +96,7 @@ config INTEGRATOR config MAINSTONE bool + default y if TCG select PXA2XX select PFLASH_CFI01 select SMC91C111 @@ -102,6 +111,8 @@ config MUSCA config MUSICPAL bool + default y if TCG + select ARM_V5 select OR_IRQ select BITBANG_I2C select MARVELL_88W8618 @@ -142,6 +153,7 @@ config OMAP config PXA2XX bool + select ARM_V5 select FRAMEBUFFER select I2C select SERIAL @@ -151,12 +163,14 @@ config PXA2XX config GUMSTIX bool + default y if TCG select PFLASH_CFI01 select SMC91C111 select PXA2XX config TOSA bool + default y if TCG select ZAURUS # scoop select MICRODRIVE select PXA2XX @@ -164,6 +178,7 @@ config TOSA config SPITZ bool + default y if TCG select ADS7846 # touch-screen controller select MAX111X # A/D converter select WM8750 # audio codec @@ -176,6 +191,7 @@ config SPITZ config Z2 bool + default y if TCG select PFLASH_CFI01 select WM8750 select PL011 # UART @@ -249,6 +265,7 @@ config STRONGARM config COLLIE bool + default y if TCG select PFLASH_CFI01 select ZAURUS # scoop select STRONGARM @@ -261,6 +278,8 @@ config SX1 config VERSATILE bool + default y if TCG + select ARM_V5 select ARM_TIMER # sp804 select PFLASH_CFI01 select LSI_SCSI_PCI @@ -382,6 +401,8 @@ config NPCM7XX config FSL_IMX25 bool + default y if TCG + select ARM_V5 select IMX select IMX_FEC select IMX_I2C @@ -408,6 +429,8 @@ config FSL_IMX6 config ASPEED_SOC bool + default y if TCG + select ARM_V5 select DS1338 select FTGMAC100 select I2C From patchwork Sat Jan 30 01:52:21 2021 Content-Type: text/plain; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id g12sm11835695wmh.14.2021.01.29.17.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:52:55 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 05/11] target/arm: Restrict ARMv6 cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:21 +0100 Message-Id: <20210130015227.4071332-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv6 CPUs when TCG is available: - ARM1136 - ARM1176 - ARM11MPCore - Cortex-M0 The following machines are no more built when TCG is disabled: - kzm ARM KZM Emulation Baseboard (ARM1136) - microbit BBC micro:bit (Cortex-M0) - n800 Nokia N800 tablet aka. RX-34 (OMAP2420) - n810 Nokia N810 tablet aka. RX-44 (OMAP2420) - realview-eb-mpcore ARM RealView Emulation Baseboard (ARM11MPCore) Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 2 -- hw/arm/realview.c | 2 +- hw/arm/Kconfig | 11 +++++++++++ 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index 5b25fafc9ab..ee80bf15150 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -10,9 +10,7 @@ CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y CONFIG_HIGHBANK=y -CONFIG_FSL_IMX31=y CONFIG_MUSCA=y -CONFIG_NSERIES=y CONFIG_STELLARIS=y CONFIG_REALVIEW=y CONFIG_VEXPRESS=y diff --git a/hw/arm/realview.c b/hw/arm/realview.c index cd37b501287..57a37608e39 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -463,8 +463,8 @@ static void realview_machine_init(void) { if (tcg_enabled()) { type_register_static(&realview_eb_type); + type_register_static(&realview_eb_mpcore_type); } - type_register_static(&realview_eb_mpcore_type); type_register_static(&realview_pb_a8_type); type_register_static(&realview_pbx_a9_type); } diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index bdb8c63af7b..daab7081994 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -6,6 +6,11 @@ config ARM_V5 bool depends on TCG +config ARM_V6 + bool + depends on TCG + select ARM_COMPATIBLE_SEMIHOSTING + config ARM_VIRT bool imply PCI_DEVICES @@ -131,6 +136,8 @@ config NETDUINOPLUS2 config NSERIES bool + default y if TCG + select ARM_V6 select OMAP select TMP105 # tempature sensor select BLIZZARD # LCD/TV controller @@ -411,6 +418,8 @@ config FSL_IMX25 config FSL_IMX31 bool + default y if TCG + select ARM_V6 select SERIAL select IMX select IMX_I2C @@ -488,11 +497,13 @@ config FSL_IMX6UL config MICROBIT bool + default y if TCG select NRF51_SOC config NRF51_SOC bool select I2C + select ARM_V6 select ARM_V7M select UNIMP From patchwork Sat Jan 30 01:52:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12057031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 398B2C433DB for ; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id w25sm12591514wmc.42.2021.01.29.17.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:00 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 06/11] target/arm: Restrict ARMv7 R-profile cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:22 +0100 Message-Id: <20210130015227.4071332-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org A KVM-only build won't be able to run R-profile cpus. Only enable the following ARMv7 R-Profile CPUs when TCG is available: - Cortex-R5 - Cortex-R5F The following machine is no more built when TCG is disabled: - xlnx-zcu102 Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/aarch64-softmmu.mak | 1 - hw/arm/Kconfig | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/default-configs/devices/aarch64-softmmu.mak b/default-configs/devices/aarch64-softmmu.mak index 958b1e08e40..a4202f56817 100644 --- a/default-configs/devices/aarch64-softmmu.mak +++ b/default-configs/devices/aarch64-softmmu.mak @@ -3,6 +3,5 @@ # We support all the 32 bit boards so need all their config include arm-softmmu.mak -CONFIG_XLNX_ZYNQMP_ARM=y CONFIG_XLNX_VERSAL=y CONFIG_SBSA_REF=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index daab7081994..320428bf97e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -11,6 +11,11 @@ config ARM_V6 depends on TCG select ARM_COMPATIBLE_SEMIHOSTING +config ARM_V7R + bool + depends on TCG + select ARM_COMPATIBLE_SEMIHOSTING + config ARM_VIRT bool imply PCI_DEVICES @@ -377,8 +382,10 @@ config STM32F405_SOC config XLNX_ZYNQMP_ARM bool + default y if TCG select AHCI select ARM_GIC + select ARM_V7R select CADENCE select DDC select DPCD From patchwork Sat Jan 30 01:52:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12057037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0EEBC433E0 for ; Sat, 30 Jan 2021 10:12:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 837D464DE7 for ; Sat, 30 Jan 2021 10:12:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232118AbhA3KMK (ORCPT ); Sat, 30 Jan 2021 05:12:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233080AbhA3Byd (ORCPT ); Fri, 29 Jan 2021 20:54:33 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B679CC061573 for ; Fri, 29 Jan 2021 17:53:07 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id m13so10618265wro.12 for ; Fri, 29 Jan 2021 17:53:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pL3VFUfes4LLPpgaJDy8jU3gYau+sjFrKic4/sFvnNY=; b=QlPx5vk/bo8ydtxxW9jNTxI4BE08Ejo8IlC/WMnhi4Wbme1fYmhJgyU1Upki/92NmF WC2DbHcdeOoGbbqkX3uzvTl8MPRzbcKjiR9DkW3t+gelrCpi6lbR+YljJPOX4B/pNnJR jLROfdsvWr2JLoQ3ukaZTPfmPpHIQ2tX5RT3QafM9bvIGcGYCZ4JbSGyIOolFM9zj2wp 8Lk2wKKiOifSwg1YsFs8CXFAh+ZPmwh7tkYJaYlPsNhSagHtmcD7TetDYtI5mpUQKEuJ UxtEsewFWr9ZiT2uXhIw/Szt607GBXaZ6aLcK0stqf2PdjzbROXSDKfZ0OHCM4ASM64Z ZiGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pL3VFUfes4LLPpgaJDy8jU3gYau+sjFrKic4/sFvnNY=; b=LvjCMycpsE6PFOR/qhH+P3v+/IqyPo4O3e6QRErPsCmXo4cWejyvOifk/zPWHs/77A D9Dw2LUbdeN0Um4W2hWXuDaHbRSBrx1LcMyy18dy9Zg6mS4kEaDkFPrt7xuZYrma3zIK ZNf80A997fomszWJ8MB1BmNufxm66qzJ2k4BfEZwiq0UT5uaWhglYBH4VQIqySF1Eybh cGkt/aGw4g430/UbdXM5J/coH+Le75AXt56Im9DDj4iKTyv9qb14u83A/mP854KCAaGf JkPHAk6k34eIWWaXBWI6WKiSkbshyJucNSoxfzqQ79Hjqw3lY+rZeJ/tpsMoCta9Z53m NnXQ== X-Gm-Message-State: AOAM531OAdkF+GmZpa8m7qazvpDmfdtcrs06FY7dJT0snY/w4rMX4GNm omnV9W/mX3urzHFmZZIltoU= X-Google-Smtp-Source: ABdhPJwbM5w0TDBpvxYm44nUc4AYAH45EnulcrjfYKeG5PWB96HJ5mDacgEs5qWvrmDx0pRxmhlO2w== X-Received: by 2002:adf:a31d:: with SMTP id c29mr7307582wrb.306.1611971586564; Fri, 29 Jan 2021 17:53:06 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id f13sm8277528wmf.1.2021.01.29.17.53.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:05 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 07/11] target/arm: Restrict ARMv7 M-profile cpus to TCG accel Date: Sat, 30 Jan 2021 02:52:23 +0100 Message-Id: <20210130015227.4071332-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org A KVM-only build won't be able to run M-profile cpus. Only enable the following ARMv7 M-Profile CPUs when TCG is available: - Cortex-M0 - Cortex-M3 - Cortex-M4 - Cortex-M33 The following machines are no more built when TCG is disabled: - emcraft-sf2 SmartFusion2 SOM kit from Emcraft (M2S010) - highbank Calxeda Highbank (ECX-1000) - lm3s6965evb Stellaris LM3S6965EVB - lm3s811evb Stellaris LM3S811EVB - midway Calxeda Midway (ECX-2000) - mps2-an385 ARM MPS2 with AN385 FPGA image for Cortex-M3 - mps2-an386 ARM MPS2 with AN386 FPGA image for Cortex-M4 - mps2-an500 ARM MPS2 with AN500 FPGA image for Cortex-M7 - mps2-an505 ARM MPS2 with AN505 FPGA image for Cortex-M33 - mps2-an511 ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3 - mps2-an521 ARM MPS2 with AN521 FPGA image for dual Cortex-M33 - musca-a ARM Musca-A board (dual Cortex-M33) - musca-b1 ARM Musca-B1 board (dual Cortex-M33) - netduino2 Netduino 2 Machine - netduinoplus2 Netduino Plus 2 Machine We don't need to enforce CONFIG_ARM_V7M in default-configs anymore. Signed-off-by: Philippe Mathieu-Daudé --- default-configs/devices/arm-softmmu.mak | 11 ----------- hw/arm/Kconfig | 17 +++++++++++++---- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak index ee80bf15150..b72926b8fce 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -1,28 +1,17 @@ # Default configuration for arm-softmmu -# TODO: ARM_V7M is currently always required - make this more flexible! -CONFIG_ARM_V7M=y - # CONFIG_PCI_DEVICES=n # CONFIG_TEST_DEVICES=n CONFIG_ARM_VIRT=y CONFIG_CUBIEBOARD=y CONFIG_EXYNOS4=y -CONFIG_HIGHBANK=y -CONFIG_MUSCA=y -CONFIG_STELLARIS=y CONFIG_REALVIEW=y CONFIG_VEXPRESS=y CONFIG_ZYNQ=y CONFIG_NPCM7XX=y -CONFIG_NETDUINO2=y -CONFIG_NETDUINOPLUS2=y -CONFIG_MPS2=y CONFIG_RASPI=y CONFIG_SABRELITE=y -CONFIG_EMCRAFT_SF2=y -CONFIG_MICROBIT=y CONFIG_FSL_IMX7=y CONFIG_FSL_IMX6UL=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 320428bf97e..f56c05c00a8 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -16,6 +16,12 @@ config ARM_V7R depends on TCG select ARM_COMPATIBLE_SEMIHOSTING +config ARM_V7M + bool + depends on TCG + select ARM_COMPATIBLE_SEMIHOSTING + select PTIMER + config ARM_VIRT bool imply PCI_DEVICES @@ -78,6 +84,7 @@ config EXYNOS4 config HIGHBANK bool + default y if TCG select A9MPCORE select A15MPCORE select AHCI @@ -113,6 +120,7 @@ config MAINSTONE config MUSCA bool + default y if TCG select ARMSSE select PL011 select PL031 @@ -133,10 +141,12 @@ config MUSICPAL config NETDUINO2 bool + default y if TCG select STM32F205_SOC config NETDUINOPLUS2 bool + default y if TCG select STM32F405_SOC config NSERIES @@ -258,6 +268,7 @@ config SABRELITE config STELLARIS bool + default y if TCG select ARM_V7M select CMSDK_APB_WATCHDOG select I2C @@ -331,10 +342,6 @@ config ZYNQ select XILINX_SPIPS select ZYNQ_DEVCFG -config ARM_V7M - bool - select PTIMER - config ALLWINNER_A10 bool select AHCI @@ -463,6 +470,7 @@ config ASPEED_SOC config MPS2 bool + default y if TCG select ARMSSE select LAN9118 select MPS2_FPGAIO @@ -516,6 +524,7 @@ config NRF51_SOC config EMCRAFT_SF2 bool + default y if TCG select MSF2 select SSI_M25P80 From patchwork Sat Jan 30 01:52:24 2021 Content-Type: text/plain; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id c18sm20017355wmk.0.2021.01.29.17.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:11 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 08/11] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M Date: Sat, 30 Jan 2021 02:52:24 +0100 Message-Id: <20210130015227.4071332-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Thomas Huth We've already got the CONFIG_ARM_V7M switch, but it currently can not be disabled yet. The m_helper.c code should not be compiled into the binary if the switch is not enabled. We also have to provide some stubs in a separate file to make sure that we still can link the other code without CONFIG_ARM_V7M. Signed-off-by: Thomas Huth Message-Id: <20190903154810.27365-4-thuth@redhat.com> [PMD: Keep m_helper-stub.c but extend it, rewrite the rest] Signed-off-by: Philippe Mathieu-Daudé --- Rewrite since v3, therefore removed Richard R-b tag. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 12 ------- target/arm/cpu_tcg.c | 4 ++- target/arm/helper.c | 7 ---- target/arm/m_helper-stub.c | 73 ++++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 4 ++- 5 files changed, 79 insertions(+), 21 deletions(-) create mode 100644 target/arm/m_helper-stub.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d080239863c..0bd0e51e498 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2281,12 +2281,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, /* Interface between CPU and Interrupt controller. */ #ifndef CONFIG_USER_ONLY bool armv7m_nvic_can_take_pending_exception(void *opaque); -#else -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) -{ - return true; -} -#endif /** * armv7m_nvic_set_pending: mark the specified exception as pending * @opaque: the NVIC @@ -2392,13 +2386,7 @@ int armv7m_nvic_raw_execution_priority(void *opaque); * @secure: the security state to test * This corresponds to the pseudocode IsReqExecPriNeg(). */ -#ifndef CONFIG_USER_ONLY bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); -#else -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) -{ - return false; -} #endif /* Interface for defining coprocessor registers. diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 98544db2df3..3e1c9b40353 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -15,6 +15,7 @@ /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) +#ifndef CONFIG_USER_ONLY static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); @@ -38,6 +39,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } return ret; } +#endif /* CONFIG_USER_ONLY */ static void arm926_initfn(Object *obj) { @@ -666,9 +668,9 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) acc->info = data; #ifndef CONFIG_USER_ONLY cc->do_interrupt = arm_v7m_cpu_do_interrupt; + cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; #endif - cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; cc->gdb_core_xml_file = "arm-m-profile.xml"; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 47e266d7e64..fe3d0291f9c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12825,13 +12825,6 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) } } -#ifndef CONFIG_TCG -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) -{ - g_assert_not_reached(); -} -#endif - ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { ARMMMUIdx idx; diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c new file mode 100644 index 00000000000..6d751424e86 --- /dev/null +++ b/target/arm/m_helper-stub.c @@ -0,0 +1,73 @@ +/* + * ARM V7M related stubs. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "internals.h" + +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) +{ + g_assert_not_reached(); +} + +uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) +{ + g_assert_not_reached(); +} + +uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) +{ + g_assert_not_reached(); +} + +void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) +{ + g_assert_not_reached(); +} + +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) +{ + g_assert_not_reached(); +} + +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + g_assert_not_reached(); +} + +#ifndef CONFIG_USER_ONLY + +bool armv7m_nvic_can_take_pending_exception(void *opaque) +{ + g_assert_not_reached(); +} + +void arm_v7m_cpu_do_interrupt(CPUState *cs) +{ + g_assert_not_reached(); +} + +#endif /* CONFIG_USER_ONLY */ diff --git a/target/arm/meson.build b/target/arm/meson.build index 15b936c1010..6c6081966cd 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -21,7 +21,6 @@ 'gdbstub.c', 'helper.c', 'iwmmxt_helper.c', - 'm_helper.c', 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', @@ -32,6 +31,9 @@ )) arm_ss.add(zlib) +arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) +arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c')) + arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( From patchwork Sat Jan 30 01:52:25 2021 Content-Type: text/plain; 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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id p18sm10429022wrx.84.2021.01.29.17.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:16 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org Subject: [PATCH v5 09/11] target/arm: Reorder meson.build rules Date: Sat, 30 Jan 2021 02:52:25 +0100 Message-Id: <20210130015227.4071332-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Philippe Mathieu-Daudé Reorder the rules to make this file easier to modify. No logical change introduced in this commit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/meson.build | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 6c6081966cd..aac9a383a61 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -14,31 +14,36 @@ arm_ss = ss.source_set() arm_ss.add(gen) +arm_ss.add(zlib) arm_ss.add(files( 'cpu.c', - 'crypto_helper.c', - 'debug_helper.c', 'gdbstub.c', 'helper.c', + 'vfp_helper.c', +)) + +arm_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'cpu64.c', + 'gdbstub64.c', +)) + +arm_ss.add(files( + 'crypto_helper.c', + 'debug_helper.c', 'iwmmxt_helper.c', 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', 'translate.c', 'vec_helper.c', - 'vfp_helper.c', 'cpu_tcg.c', )) -arm_ss.add(zlib) - arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( - 'cpu64.c', - 'gdbstub64.c', 'helper-a64.c', 'mte_helper.c', 'pauth_helper.c', From patchwork Sat Jan 30 01:52:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12057029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C24A5C433DB for ; Sat, 30 Jan 2021 10:11:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9A58064DE7 for ; Sat, 30 Jan 2021 10:11:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232128AbhA3KLQ (ORCPT ); Sat, 30 Jan 2021 05:11:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233116AbhA3B4L (ORCPT ); Fri, 29 Jan 2021 20:56:11 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDC38C06178C for ; Fri, 29 Jan 2021 17:53:22 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id u14so8142492wml.4 for ; Fri, 29 Jan 2021 17:53:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rd+PClqm9GCes/hSRY8Vwer9UM1+ZxmgnVmbkhC6bwQ=; b=S8gP7rmCHgjQ7YTM/ADW7lbRknMIzFi/kvGjnDTBiXVwxuHAweAduqVLnoWGJLI2Ik JfdEKMmuSM3Uo8wpGPc7O5efkIfwempgLB5LYyAxcpbOduzxSzOy25mGYctn0157CNuf zV0ZhHXDZP2UT03nYTizMXR4Vs40tQPbvbnOmuxLCvtPCrY0PMsdGMwTdM2ArhKkBchH TWyvRrzcqLAWdaanShYSz+sOqcrd7NvfsPGFpWW+5oIunY8vE5ZXCX2iLvPjoaAaSoPR DrMJQdIPKVgaAINimQlPBxGcMGIfkres1tY3aYap3kkTCgMibqAulTso5blHDtdlfoUu cwiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Rd+PClqm9GCes/hSRY8Vwer9UM1+ZxmgnVmbkhC6bwQ=; b=lJ2hBVXrGDBO6wOT2n4tYxn/Z4rr5wIRrF1HGlDXIbbtSXixiXgDar8F4GdODb7/z3 vnQ40LN/vnwvn5bK3/Uwicc5aB24YGys1jb3imm7s7m1tbsqcWACabstpbeER8Q7o1dx PQHgEH2R8EpVRyv2idG4plGebP+QiqVeWcAI7SozdgVNFeYOlc3cONVUh0zUtCJdtL+s NqcweajiysQzNYRe8klgdzZyhKhhePcdd5JoEcXJPioBabb7HZzIokGVF1jCNDPOtDAB QdD63omDTsATfH2TmckHTf8ToSVrV4QC3ytPb2rpqhfBQvqm6ziAx493YB2t9FBLvPR2 VYAA== X-Gm-Message-State: AOAM530HCKgS6zTu2/BVRK8f/TRnsm1a0Ti2STyq1QuktyS+gWF55Hv3 j3l5+HUnZwEp/PCIvWh2VMg= X-Google-Smtp-Source: ABdhPJyiwfRfgUFvof6J96IEb3nlU6yPh2kst4/42gIlUzuKzVr51L9y/LCynY6WSCm+1mWXoo7usg== X-Received: by 2002:a05:600c:2204:: with SMTP id z4mr5915886wml.138.1611971601791; Fri, 29 Jan 2021 17:53:21 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id g1sm15181177wrq.30.2021.01.29.17.53.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:21 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, Samuel Ortiz , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 10/11] target/arm: Do not build TCG objects when TCG is off Date: Sat, 30 Jan 2021 02:52:26 +0100 Message-Id: <20210130015227.4071332-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Samuel Ortiz We can now safely turn all TCG dependent build off when CONFIG_TCG is off. This allows building ARM binaries with --disable-tcg. Signed-off-by: Samuel Ortiz [PMD: Heavily rebased during more than 2 years then finally rewritten] Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index aac9a383a61..11b7c0e18fe 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -27,7 +27,8 @@ 'gdbstub64.c', )) -arm_ss.add(files( +arm_tcg_ss = ss.source_set() +arm_tcg_ss.add(files( 'crypto_helper.c', 'debug_helper.c', 'iwmmxt_helper.c', @@ -38,12 +39,12 @@ 'vec_helper.c', 'cpu_tcg.c', )) -arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) +arm_tcg_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('m_helper.c'), if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_TCG', if_false: files('m_helper-stub.c')) arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) -arm_ss.add(when: 'TARGET_AARCH64', if_true: files( +arm_tcg_ss.add(when: 'TARGET_AARCH64', if_true: files( 'helper-a64.c', 'mte_helper.c', 'pauth_helper.c', @@ -52,14 +53,16 @@ 'translate-sve.c', )) +arm_ss.add_all(when: 'CONFIG_TCG', if_true: arm_tcg_ss) + arm_softmmu_ss = ss.source_set() arm_softmmu_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', 'machine.c', 'monitor.c', - 'psci.c', )) +arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files('psci.c')) target_arch += {'arm': arm_ss} target_softmmu_arch += {'arm': arm_softmmu_ss} From patchwork Sat Jan 30 01:52:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12057027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1C74C433E6 for ; Sat, 30 Jan 2021 10:11:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9808D64DE7 for ; Sat, 30 Jan 2021 10:11:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230470AbhA3KLL (ORCPT ); Sat, 30 Jan 2021 05:11:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233125AbhA3B4L (ORCPT ); Fri, 29 Jan 2021 20:56:11 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7FA1C061793 for ; Fri, 29 Jan 2021 17:53:27 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id g10so10625792wrx.1 for ; Fri, 29 Jan 2021 17:53:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dDZADzgKI5lXuqqUK6CV2RYB4kAOXUW22/2lumwj8o4=; b=e7psjHWNaDe5BRPalel5z+UrUPQyCYHO0ADPAqwnXvE6/jKDRHnq865wvhM3CvcziS 81EyjqLup5Sso5l2NVZ/0wY2xzImn5JfNEpSNIBoIBengxfy1LzI66lsP+ni/80f/evR U7QLC+B3eBq5pi+hy3v4oWie/DVjl15VvVl+DUC7b4bFZ82n+IBpLOg69cciuSH0bv0o ugmYLJK5GlHsO6ioN/+OP/utD5jbLp9Mf2b2fwCAn07n5bGBKAg2Ljhf/XruZU6V7ADq ieVbF8YOSHcYMgG6rdoDn8FpNs1Ulo8zayvnM2zRRrDOTV3lmjsv5yKhGHhUzizRmIXS CcDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dDZADzgKI5lXuqqUK6CV2RYB4kAOXUW22/2lumwj8o4=; b=roBg+DPdcXwxsi+xqXnO9F6iTwI/6L3rtATVVxC61n4HQ5K9u2WsxLsomu3jWgEkdd PiBlIFrDB0PHjHmf6sOK08Ot30FM13VQyRgFZIBfFLXQvEW76MLbtGC0kOD6BWPPmNXO 9bYAfim3QnwbDgnUTpr6WfB3s3eWFMdFJwWVUStWhVTnrGVbzuE5lSaAcAZCOwBNFh7s 6BdGoGh9kE6kH8EfrNSdOeSI2usUnkF23w4q+KNFRCABikR2WqjjnVM5NZwXcQKhqdZs FGpWoSwl143VomWbYZIuHUZowaKWkuSOSc/mTAQvHE8RIwuNMKNyLcmXRxFa0vAy4aBY bN/w== X-Gm-Message-State: AOAM533lVl6WAXfdW5wJtkaTjY3SrlcJLJWHiBfUmyP5Y7G0bq1FIga7 TyQ1lPEO6+L0QPfhp3n2DGE= X-Google-Smtp-Source: ABdhPJxaH/w2Fme7el93QIXUQzDffvAxEB63h7HSmXGa9jkoVnLMptaWM3d09a23cIwVkku9tHUZXg== X-Received: by 2002:a5d:5049:: with SMTP id h9mr7559886wrt.404.1611971606779; Fri, 29 Jan 2021 17:53:26 -0800 (PST) Received: from localhost.localdomain (13.red-83-57-169.dynamicip.rima-tde.net. [83.57.169.13]) by smtp.gmail.com with ESMTPSA id d13sm14972889wrx.93.2021.01.29.17.53.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Jan 2021 17:53:26 -0800 (PST) Sender: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , kvm@vger.kernel.org, Peter Maydell , Fam Zheng , Thomas Huth , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Claudio Fontana , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org Subject: [PATCH v5 11/11] .travis.yml: Add a KVM-only Aarch64 job Date: Sat, 30 Jan 2021 02:52:27 +0100 Message-Id: <20210130015227.4071332-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210130015227.4071332-1-f4bug@amsat.org> References: <20210130015227.4071332-1-f4bug@amsat.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Philippe Mathieu-Daudé Add a job to build QEMU on Aarch64 with TCG disabled, so this configuration won't bitrot over time. We explicitly modify default-configs/aarch64-softmmu.mak to only select the 'virt' and 'SBSA-REF' machines. Signed-off-by: Philippe Mathieu-Daudé --- Job ran for 7 min 30 sec https://travis-ci.org/github/philmd/qemu/jobs/731428859 --- .travis.yml | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/.travis.yml b/.travis.yml index 5f1dea873ec..4f1d662b5fc 100644 --- a/.travis.yml +++ b/.travis.yml @@ -264,6 +264,38 @@ jobs: - CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS}" - UNRELIABLE=true + - name: "[aarch64] GCC (disable-tcg)" + arch: arm64 + dist: focal + addons: + apt_packages: + - libaio-dev + - libattr1-dev + - libbrlapi-dev + - libcap-ng-dev + - libgcrypt20-dev + - libgnutls28-dev + - libgtk-3-dev + - libiscsi-dev + - liblttng-ust-dev + - libncurses5-dev + - libnfs-dev + - libnss3-dev + - libpixman-1-dev + - libpng-dev + - librados-dev + - libsdl2-dev + - libseccomp-dev + - liburcu-dev + - libusb-1.0-0-dev + - libvdeplug-dev + - libvte-2.91-dev + - ninja-build + env: + - CONFIG="--disable-containers --disable-tcg --enable-kvm --disable-xen --disable-tools --disable-docs" + - TEST_CMD="make check-unit" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-aarch64" + - name: "[ppc64] GCC check-tcg" arch: ppc64le dist: focal