From patchwork Mon Feb 1 18:13:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD11CC433E0 for ; Mon, 1 Feb 2021 18:15:32 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 73E8664DDE for ; Mon, 1 Feb 2021 18:15:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 73E8664DDE Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2U32QEUkEAevfK3uSGZ/5h1mRf6HIYJrGdUMfGX2cig=; b=Qn6S3xZd3xAHYAyeb9HO9hCtm eunk4xssQid6zHkZHNOhkPoRlaN4552c02k1TXFNPAQ7kAWdTLUNwemkd/kJrbjP+vLiM1M2qL26d uUJdb2sXrZV/Zaiu3iEZi/ctbfbNH8O+Sas7zwmBoe8od2qGWrx/1UM8pa7F9R6Jz1GYSABq1pNCH J76yZz/Hc3uRQC9sU4wl9xvhh2yJNAwihxjFiooIOxNJR62bNG0eA7lfokDQV2lywNMHGRjsi3rIK R2LQUags9BS1jlpCLnqkxjL9YHhBz+VFW6uO6a9eJ8rRnzjUUtBTK9j5WLDFox+D44t8m1U4U/iGA af0kUXAkw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di5-0002yS-Ip; Mon, 01 Feb 2021 18:14:01 +0000 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di0-0002te-7h for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:13:57 +0000 Received: by mail-pl1-x62b.google.com with SMTP id x9so4559130plb.5 for ; Mon, 01 Feb 2021 10:13:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b+kKbPCM5QoqG+cAM7BJq0jTSCBBxgPJ++jOnTflRKg=; b=cFsuGWLqZGXtcoWEE6SkenuYrfeXD7dE3JlwBdjuyByI2PGOyWc848IIP2VMjqFNZO iJHxp9A/9twFqd/E2hEpmG1bylTBTz7mSY3IhXfJrIEB5Dg+fEJMcsMGHV8eBtH1gZu9 2ecqEQgbAdSY3fnSaNiYkTSsULft83XwWXV37WTFKaC7w4l8EI/38mLQFebQZw/Vg7BT YqCGhLXZrnP7X/C6eIwJTWX6F821CCQgPvLYRV6pIUJzVI+ZJUB2PTHNYFoxyVdqMS5r EslxIMEarkAqcKrW3W2Y60bT5TGXFB/sdeDExia8Te1w/vPPhWOh7CnRjGfgJgzx+ep8 v98w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b+kKbPCM5QoqG+cAM7BJq0jTSCBBxgPJ++jOnTflRKg=; b=V7WDA7ubwVzA4sXXFWLrsQQRLOpG3dk7SQsWkQK1NtcPJ/JYVucnuv++oAFivMGffW Z+1dtsMFEsoXnSAoYsbNRADNFYdPN0krpErDHO+BCHKFuFW9xohk/ddff1wj6+OAbrbY WNGRu0v4gFMz+pZNTuagWrKGvIL+/5kHYRMaTwQIEzHUsjhSkQnP0/sVuAdyN8PJ3p+X dikwtyn0hvEGeCwT2e6YMD4AwcfXXjeR7EBguBHg+0g2p0prAH0yPbGvQEfM4lb5huIW z6riLRerGrp1FLFHv4lm2pkBBtZQ7jli0yLIxoe17PqPxsaTn8cFnpC/0Ji1OlQoaVZf hyHA== X-Gm-Message-State: AOAM533xfdcj4pFO6gDF9rK+U+5GTD3xu2xi8f7snx0b5KtsVrFYoe8m QYIIcezyNn2uzj+2qi+PsZyaDzNdjhYfsA== X-Google-Smtp-Source: ABdhPJzQ1f1Hgx/4Da5FS+4mKuRxEPGRYlAIhEpnhnpzJ6rV6iLHUQF9XPG3g9NECjecf+Yt7722dg== X-Received: by 2002:a17:902:ba85:b029:de:ba16:818b with SMTP id k5-20020a170902ba85b02900deba16818bmr18585225pls.75.1612203233966; Mon, 01 Feb 2021 10:13:53 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.13.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:13:53 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 01/31] coresight: cti: Reduce scope for the variable 'cs_fwnode' in cti_plat_create_connection() Date: Mon, 1 Feb 2021 11:13:21 -0700 Message-Id: <20210201181351.1475223-2-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131356_309459_5F5F90A4 X-CRM114-Status: GOOD ( 15.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Markus Elfring A local variable was used only within an else branch. Thus move the definition for the variable “cs_fwnode” into the corresponding code block. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring Link: https://lore.kernel.org/r/c1b09b27-9012-324f-28d0-ba820dc468a5@web.de Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-cti-platform.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers/hwtracing/coresight/coresight-cti-platform.c index 98f830c6ed50..ccef04f27f12 100644 --- a/drivers/hwtracing/coresight/coresight-cti-platform.c +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -343,7 +343,6 @@ static int cti_plat_create_connection(struct device *dev, { struct cti_trig_con *tc = NULL; int cpuid = -1, err = 0; - struct fwnode_handle *cs_fwnode = NULL; struct coresight_device *csdev = NULL; const char *assoc_name = "unknown"; char cpu_name_str[16]; @@ -397,8 +396,9 @@ static int cti_plat_create_connection(struct device *dev, assoc_name = cpu_name_str; } else { /* associated device ? */ - cs_fwnode = fwnode_find_reference(fwnode, - CTI_DT_CSDEV_ASSOC, 0); + struct fwnode_handle *cs_fwnode = fwnode_find_reference(fwnode, + CTI_DT_CSDEV_ASSOC, + 0); if (!IS_ERR(cs_fwnode)) { assoc_name = cti_plat_get_csdev_or_node_name(cs_fwnode, &csdev); From patchwork Mon Feb 1 18:13:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F7F3C433DB for ; Mon, 1 Feb 2021 18:15:37 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C90A164EA1 for ; Mon, 1 Feb 2021 18:15:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C90A164EA1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=QcPyd0nRC06gf3S46Cn33nJPbSgGe4NW7doyNWIAGSU=; b=uOZPEgeVseTJrtoO4HIKgTezx ir9es/sWhf0Yq0gwAVcwa6MyujZkdQpIMgWRgPoXJJXS7i9rXImszm0+biSn5j9Tp9s0MbJ/8JKix L2wrS6WwWab6qWcFTfmAWVornllliOu7czMTKo1ykwyC80xyPIIRTHsQJJ0J3c+38nkExc/QYGZHC 84hpNG4L/vz6JnvRCBkFLPoNmwUZ0ODJ0Pb+kQx93YMdpFZz+5+qtCjmFOl4wkAaKViMd754uZXDU CTyJzGQOdEwOxjtqm/sU6rnNZemyAt/4D29E/mlOtUL9DPv0sM+y6c0ebjR2ppcODsCKv3ir70UfF DORtrRXAQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di8-0002zO-1d; Mon, 01 Feb 2021 18:14:04 +0000 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di1-0002tp-BG for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:13:58 +0000 Received: by mail-pl1-x634.google.com with SMTP id y10so6211975plk.7 for ; Mon, 01 Feb 2021 10:13:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dGzmgBv4K1U0QOhwlZji5Uk4apM7BYnCXSr1rOYmcOs=; b=dQDFI+Mu9BvvAMZgG2UflQSsnnjrfgFTRhaVlUtADA/wI4ubZRWs3bIiZburIrVOYk NMFUJz7GX8uK0OoOBGSFfEvOR/ZdNW8g/ZNFfk7oFyfObgr4aO/mv3Ohh3YWxmTOgUsS s5UMJq2Yqv9hFR02dlmtKmN1w6ysMoHtk2q9SEj6N95ibITwGpJerJBwr4E4wahV4USp N1AksKm/2NqkBdnS+jrpzsvYuHJ7KFZqoMhL03UlEAs2KmZUDaErQl43Glnwa6ZC/IH5 xQ2KxR7SeboK2WRldPNu8fJeaczzm9KWIfFdGVJIAtHwJjdeGi15O+R+sELID1v8Hu3D k/Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dGzmgBv4K1U0QOhwlZji5Uk4apM7BYnCXSr1rOYmcOs=; b=ZTeQv+2+t9Rmn3wdYEZkDM8mM2XaF0wKI2mHRkNn7z+NRsePQfdLx/2ifBy8nxfXyA Xaq5KNd2aMrrqiYft21ncIHo3SSp8yvGuVwn7w+JpkE1H3bA/fhaA7Z/oCmpV6d+bfBK zBT5c8mFDQyC1Z0A0WN4peGU5UCaa1bdasOl8LXAZYSl4oHQrg1EM4j0ihRGFa6eRELx yDA/0UoIkNKJmo8qnwR3oCh6/0W5bYzcNTYLCadpwZjmewg8D1GGSjWDaSwszIVcDC6/ e2IFfQA5lIn66e4lPpUyQaI5MsGFtPrqnfjvAAUoEqEc2SNRskFSR7oQKZ73k/by6jx/ +CAQ== X-Gm-Message-State: AOAM531jhmY2FtGFFh9u4FmjULSpjzOiUCFB7gLd49LYJYdJJX8ZdNrs Jdu6I6jfnWFl918ekOza0pLDxGJuajYI7w== X-Google-Smtp-Source: ABdhPJyjnaarUPrvsvjrLcHjhyWaIR5c5QLFS6RSAs6vBEP5vLqKtMhzO1O2Ssa8vdwMxp53u++PNg== X-Received: by 2002:a17:902:b986:b029:df:e5d6:cd71 with SMTP id i6-20020a170902b986b02900dfe5d6cd71mr18646285pls.42.1612203235161; Mon, 01 Feb 2021 10:13:55 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.13.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:13:54 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 02/31] coresight: etm4x: add AMBA id for Cortex-A55 and Cortex-A75 Date: Mon, 1 Feb 2021 11:13:22 -0700 Message-Id: <20210201181351.1475223-3-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131357_416558_835D7BC6 X-CRM114-Status: GOOD ( 12.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Chunyan Zhang Add AMBA UCI id to support Cortex-A55(Ananke) and Cortex-A75(Promethus). Signed-off-by: Bin Ji Signed-off-by: Chunyan Zhang Reviewed by: Mike Leach Link: https://lore.kernel.org/r/20210118065549.197489-1-zhang.lyra@gmail.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index b20b6ff17cf6..8c4b0c46c8f3 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1713,6 +1713,8 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ + CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ + CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ From patchwork Mon Feb 1 18:13:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8752EC433E0 for ; Mon, 1 Feb 2021 18:15:38 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 04FE864EA3 for ; Mon, 1 Feb 2021 18:15:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 04FE864EA3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=sfG1CUnsFCcpxJLyCssFtjRmhOuEnYPBs8AF1jAthVc=; b=aP5Cv5xbPeS+2Up7pLnVivlJC xkrYFHYsXRrZnh5OskoMjYtEtag+8c7aTHpthoweE/9HmghmQ66JzD693tk7Qu5Yrn1oKMvTAoKYg ORs1xcR72oy9Xj0YXJRdUIDeM7a9Fg3HfrB3jgd8XBtwP/C1/8UdxFCqXqT9mWiODFmp/tLPPk6g6 s2/Sfs2YGFOLFj9TV2XKhIVtVcS59BUUfLVeAEYOGY7bCcUT9mpnu9m5d/2KeW1jTan7TV+rXUo5X N/NJ6lGMnAlqxli/NpwQbttpgXPwjHyKbZcGLnmoLnUZnNlwaWof5QTv5h+ujOUSGt2q1qoQKOl9F 5qJYxym9Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diB-00030z-W4; Mon, 01 Feb 2021 18:14:08 +0000 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di2-0002vO-Ea for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:00 +0000 Received: by mail-pj1-x102c.google.com with SMTP id l18so80547pji.3 for ; Mon, 01 Feb 2021 10:13:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ROzSJ+k0Uh2r90d58CiYcoDg2pZWWxblaGujvBNFeHM=; b=i/YienVEz3qdYBF4/nwO9CuFleIBj9s7iADd2yhy+/daqfs2BU7+4zjKP1FZV5GNvo P1R16Ux80wWZqWcQOcGJKIUm8Qq5q7GOfOXXRhsTOElL4JLG19wGMfx87P+IP7dMeOUq SxlJ8KZXCEC7r79V6RMiYsRguCQWchHWHAvihsG+8uq39wZxS30OgputLXrZtMcvoXmD z7033e1g4QSh74kiJAMeepULA6Q895iQ3Jzq0Yysctuq5jLG5ZVTfo3UPUlG0qthaAUe 1ZCzga5/EyRhintg9SwJ2cCUaMXQX552G5tkKahUobQjuRAaSCNiTqJyo8N2nMy0pxN0 Mg4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ROzSJ+k0Uh2r90d58CiYcoDg2pZWWxblaGujvBNFeHM=; b=STXbbrP5i80vyHkJSYfCOnk6g7n5ChCeqBR4L28G9xAGKj3/HKq27vtOQ8ixoh6MTj VDgXblpCKl75Dd/dzuMdXBnnI2rERlQxu0kXVOwBUpqOTAmIib0CORJTUBzqwXXpgC83 zjNuRqforNG/94NhHuRVi1EXnOB05LkK2pOp7sW62sTPzqRyPzs9m62CnXl3R9hlL8zM g5369GR4/MtWhClbFBt3unjWMZohdOTtU4qleI2YFAwLZL4HRBdtWWkDX/JrkZVEfRFd N8+7MYb7q11kOOzox21e6aKWDnftO/nO2/58uX3Og6xPzi3CmCbyTjkbP8xbafB/nciX jFkQ== X-Gm-Message-State: AOAM5330NMCp+VOrNoE2lpP2EXOroz6dDUD355s6xNbGkCJXmhCkco/S xsNRhwo/lZ4UX91zhwwRwPsV2w== X-Google-Smtp-Source: ABdhPJz52cgRFfXtGh3utHNSaJuqXeFHReNAE8Ak2VwKdK2GWTHpyvL9GsV0UOY/whGmI3IGufyilA== X-Received: by 2002:a17:903:2285:b029:e1:58a2:b937 with SMTP id b5-20020a1709032285b02900e158a2b937mr6528736plh.68.1612203236195; Mon, 01 Feb 2021 10:13:56 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.13.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:13:55 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 03/31] coresight: etm4x: Handle access to TRCSSPCICRn Date: Mon, 1 Feb 2021 11:13:23 -0700 Message-Id: <20210201181351.1475223-4-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131358_533872_A05053F8 X-CRM114-Status: GOOD ( 17.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose TRCSSPCICR is present only if all of the following are true: TRCIDR4.NUMSSCC > n. TRCIDR4.NUMPC > 0b0000 . TRCSSCSR.PC == 0b1 Add a helper function to check all the conditions. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-2-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 29 +++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 8c4b0c46c8f3..4b615e9f3d76 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -59,6 +59,22 @@ static u64 etm4_get_access_type(struct etmv4_config *config); static enum cpuhp_state hp_online; +/* + * Check if TRCSSPCICRn(i) is implemented for a given instance. + * + * TRCSSPCICRn is implemented only if : + * TRCSSPCICR is present only if all of the following are true: + * TRCIDR4.NUMSSCC > n. + * TRCIDR4.NUMPC > 0b0000 . + * TRCSSCSR.PC == 0b1 + */ +static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) +{ + return (n < drvdata->nr_ss_cmp) && + drvdata->nr_pe && + (drvdata->config.ss_status[n] & TRCSSCSRn_PC); +} + static void etm4_os_unlock(struct etmv4_drvdata *drvdata) { /* Writing 0 to TRCOSLAR unlocks the trace registers */ @@ -270,8 +286,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) drvdata->base + TRCSSCCRn(i)); writel_relaxed(config->ss_status[i], drvdata->base + TRCSSCSRn(i)); - writel_relaxed(config->ss_pe_cmp[i], - drvdata->base + TRCSSPCICRn(i)); + if (etm4x_sspcicrn_present(drvdata, i)) + writel_relaxed(config->ss_pe_cmp[i], + drvdata->base + TRCSSPCICRn(i)); } for (i = 0; i < drvdata->nr_addr_cmp; i++) { writeq_relaxed(config->addr_val[i], @@ -1324,7 +1341,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nr_ss_cmp; i++) { state->trcssccr[i] = readl(drvdata->base + TRCSSCCRn(i)); state->trcsscsr[i] = readl(drvdata->base + TRCSSCSRn(i)); - state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i)); + if (etm4x_sspcicrn_present(drvdata, i)) + state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i)); } for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { @@ -1440,8 +1458,9 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) drvdata->base + TRCSSCCRn(i)); writel_relaxed(state->trcsscsr[i], drvdata->base + TRCSSCSRn(i)); - writel_relaxed(state->trcsspcicr[i], - drvdata->base + TRCSSPCICRn(i)); + if (etm4x_sspcicrn_present(drvdata, i)) + writel_relaxed(state->trcsspcicr[i], + drvdata->base + TRCSSPCICRn(i)); } for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 3dd3e0633328..80e480c7fe5c 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -179,6 +179,8 @@ #define TRCSTATR_PMSTABLE_BIT 1 #define ETM_DEFAULT_ADDR_COMP 0 +#define TRCSSCSRn_PC BIT(3) + /* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3) From patchwork Mon Feb 1 18:13:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58BECC433E0 for ; Mon, 1 Feb 2021 18:15:42 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 003C164EA0 for ; Mon, 1 Feb 2021 18:15:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 003C164EA0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9GHU8IpB360HkoNuN8C4A4YUiJushfpGJ2JHlH2Xfj8=; b=XLs24rWzJEwaePD5IEr+MDSBf of7CJLG+njpJ93NCZWtoMmub/tiJcWIPBLTVAuNnWtFYZJKTF5EX0AjG6b2Wma34ziEnu1G8qIZXo FZaOc9W1bRR8qdHFfy1zFN63M/M1piim3nErCcfzykttsfl3bQHlMfRGS4346gj8hat6boGKg9479 7I9a3RU/8wmN7RFwNJo1Y0Ua+DjtCobWk1B6bPFWz8D69E7FY4DDr6nZlPMX9bDD2mwb7z0cu/pBc Xq9y0DZuytBGTuujIdbfZ2YL00K/UTWo1t8qQ07Z9N998A2LjpsiHrW/u3lyY1PTXAtM4pO/hmt5b kF6f4fJUQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diK-00035x-Ne; Mon, 01 Feb 2021 18:14:16 +0000 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di3-0002vs-B3 for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:03 +0000 Received: by mail-pl1-x632.google.com with SMTP id b17so10463157plz.6 for ; Mon, 01 Feb 2021 10:13:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O41rJTlMZTVcMIElK5KqNnqfKtFcYHMw/qm7GjAEOtc=; b=SicjLH2B3f1NYan3zMCEi76cHb9l2J3UEvYZ9aVjRskpwK1cLtxtylONvSM+kUdSgr tbafOxWVBf5DdwXdQFI4nDmU4peqLTunvKCeEaU6LOv4dasiv+NzY56WnXBVUv+IKp0T 4Q3uaNYQN+vfEJFYN9Tdp95GqZrZ3pG5tUaXB6pJNYwxr/hNqzlHWNYyUAYe1QRqAXpf LdiW8Fw+DSmIDHIqdo0qNi6IzRTHOfObJ6wx5+52Qsi3BpTkvQj9N29BOVVqv7mmEI4w lj44xGnxqRKOifns++V8Nop0HvCZPl1i+NP5QUcUccF2EgCXKgXVT8FyMtCzZJdDw1wi xZzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O41rJTlMZTVcMIElK5KqNnqfKtFcYHMw/qm7GjAEOtc=; b=tSMWK6KRv+Yhi/F66DEfYLgBgd4Jzten1aC5dSTx1v/Qn1Z7OfCjDQrkbxehCDia2J TpQKffgh3ue5Po9+ZFM4cQ9EnbR/HzCYIxT7lvQm0cXzO1BAsVt4KJtGZSFuTeNd4upT mtaW3aCcmTeD5FwWS3VLvYN1MXOhW9KwYqx2dwHy1FY9sjXhfsutIjwKtzWpCxbqXyZT nBw9anIwcFeGPLc3uQc4lKMeGSX1R69Jb9gCVi6kMpSOlqYp1oKaiW5u7HjkiAaqx2S3 B/1+OGG140i2I6bstsY/H8yylghMdeljoiULf/JlsFVdKtTK+HcK4pfpaQwyIWGlskqH gPTQ== X-Gm-Message-State: AOAM530lNS6kmvxiBm732AvGbvbU93zz17eYwEqC/q8I6tFMIhQV1nHC 6gLYutyUTfGwkANDj6gpfyWlK1ev7shSNQ== X-Google-Smtp-Source: ABdhPJwvsIXJgpAx3CYkvtgGeS+y+LHSVT2dOhln0HvqlMpx4ib1syz0J/T0PMim1vZZ1xcsQuLZCA== X-Received: by 2002:a17:902:bd0a:b029:e0:612:ad38 with SMTP id p10-20020a170902bd0ab02900e00612ad38mr19262845pls.30.1612203237104; Mon, 01 Feb 2021 10:13:57 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.13.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:13:56 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 04/31] coresight: etm4x: Skip accessing TRCPDCR in save/restore Date: Mon, 1 Feb 2021 11:13:24 -0700 Message-Id: <20210201181351.1475223-5-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131359_645883_C7763901 X-CRM114-Status: GOOD ( 14.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose When the ETM is affected by Qualcomm errata, modifying the TRCPDCR could cause the system hang. Even though this is taken care of during enable/disable ETM, the ETM state save/restore could still access the TRCPDCR. Make sure we skip the access during the save/restore. Found by code inspection. Fixes: 02510a5aa78d ("coresight: etm4x: Add support to skip trace unit power up") Cc: Mathieu Poirier Cc: Mike Leach Cc: Sai Prakash Ranjan Cc: Tingwei Zhang Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-3-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 4b615e9f3d76..0924c376e35a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1373,7 +1373,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR); - state->trcpdcr = readl(drvdata->base + TRCPDCR); + if (!drvdata->skip_power_up) + state->trcpdcr = readl(drvdata->base + TRCPDCR); /* wait for TRCSTATR.IDLE to go up */ if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { @@ -1391,9 +1392,9 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) * potentially save power on systems that respect the TRCPDCR_PU * despite requesting software to save/restore state. */ - writel_relaxed((state->trcpdcr & ~TRCPDCR_PU), - drvdata->base + TRCPDCR); - + if (!drvdata->skip_power_up) + writel_relaxed((state->trcpdcr & ~TRCPDCR_PU), + drvdata->base + TRCPDCR); out: CS_LOCK(drvdata->base); return ret; @@ -1488,7 +1489,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET); - writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR); + if (!drvdata->skip_power_up) + writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR); drvdata->state_needs_restore = false; From patchwork Mon Feb 1 18:13:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F14EEC433E6 for ; Mon, 1 Feb 2021 18:16:32 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 80F5E64DE1 for ; Mon, 1 Feb 2021 18:16:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 80F5E64DE1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BmWlZIrtmJx2HlCkC0UjKf1XXGLdiEBLWBYX1hQfaFY=; b=nL0o9PiRBpUCvRLWroHDFTEkV E1XJM5CL8Izg84YOBWADMBxWD3ipZj64HY9KFOAVDNHKYYURDWCU4K/MOtHP9Z2uehVxOd6ZcGGZb emUx9jh50D7Utm1ite43EucwR5lSQXw2/ER0MVfZTCQvXNUMnQC+/2fYC1sjKDffuHkHwm6mS+PFi PI13IPygwO83qr8qe4Ka0SYjQkJJf5kti3QV4T0WBKbtYCWLUsXc9yahH6c7ucsAdCAeubst4yCuh +TZ6fHvJrAcrM2xb7nNGQBEb7gt2wOXCptQr2Q4cwa2q4jtKINEoNcNaULjMQBbkHHkTtvweXhOtW fbfBReNLQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dim-0003HQ-I8; Mon, 01 Feb 2021 18:14:44 +0000 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di4-0002wH-Oc for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:10 +0000 Received: by mail-pj1-x102d.google.com with SMTP id e9so92266pjj.0 for ; Mon, 01 Feb 2021 10:14:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WYDZPY2yO9DfXvSspozeg3qyfs6f5s9qLckqmrZ7Nys=; b=VPeu4/F892Pfo3ZpxEdo+GTz+l43Zi9I6QGG5ovgmYsOUTiH5WHYZ77TDI6l03Wa+4 7iXYYcxC4tsxyH/QEgZKm+Fad6fbN0oCS+tFUvpynTSMsxYjPAILJlSjIMtXuUAs6tx+ 9Y2XoR+IHa+QfDMHEEGWZAYv1YjitGJ4PiL7Ns1kk+OfyEuHN+UObRUFyn4YHTNDp/7J 1Vd64u/QbhjegM9Ma7gAxc5wSKxTveG6Dd0xQ+X7Flfcz7Z8QrtakMV0Z9WArrPABdFB jU0oi/4Ice026vstprGF+37ApDa/8/TqcplVee550zmUie/GGzKGct4TFt+uwSefcdPA 1xhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WYDZPY2yO9DfXvSspozeg3qyfs6f5s9qLckqmrZ7Nys=; b=jfc/UyDbNV8DYEMIgKIMU1++v92Oi+zMbVX3wEINKV7shtaBXrqAzqdOZQb6OSvnv0 Km2DGJenQcAnh2yW1JbljwPdDva64ekgqGjxuXabC3cA3r6EaMPsQyHbhs+MaEfi5NQE DBYO4jUlq9U3r1u5OdYXFL2h7P2TCwsglfQidBDuejVTL3B746RUL+ns6he/PVrdyuvE ouIZQu57oZpUk+EYQ+pffuMihDU/5NXTKNYKldt2riyyO2cQrGGBe0v1KaoEbm2Q4vcF /d7NaxGcQAVUX08RyTgFeirRK2HxcWkBleaa7a2HUy6u7uzfjoWG2J1xj7UkRMwDhqci Eh7A== X-Gm-Message-State: AOAM532AOEE4IMkJTKw0h4WIpeVSN5m4J4G+zMxTeYBPZk28X5GitSFW Vjxjd01K4xiQIJD0KSpuScNaAg== X-Google-Smtp-Source: ABdhPJxYrWiMZNZ0U0yeATNhUnOJ4pMVC3K+QeBtLTCOzMC/TLgaQrTajjpBYPP+ZXg7MMKKMKAmzQ== X-Received: by 2002:a17:902:ea0d:b029:e1:54c:6344 with SMTP id s13-20020a170902ea0db02900e1054c6344mr18429034plg.22.1612203238317; Mon, 01 Feb 2021 10:13:58 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.13.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:13:57 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 05/31] coresight: Introduce device access abstraction Date: Mon, 1 Feb 2021 11:13:25 -0700 Message-Id: <20210201181351.1475223-6-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131400_988005_A38F326F X-CRM114-Status: GOOD ( 21.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose We are about to introduce support for sysreg access to ETMv4.4+ component. Since there are generic routines that access the registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations, timeout) and in order to preserve the logic of these operations at a single place we introduce an abstraction layer for the accesses to a given device. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-4-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-catu.c | 1 + drivers/hwtracing/coresight/coresight-core.c | 43 ++++ .../hwtracing/coresight/coresight-cti-core.c | 1 + drivers/hwtracing/coresight/coresight-etb10.c | 1 + .../coresight/coresight-etm3x-core.c | 1 + .../coresight/coresight-etm4x-core.c | 1 + .../hwtracing/coresight/coresight-funnel.c | 1 + .../coresight/coresight-replicator.c | 1 + drivers/hwtracing/coresight/coresight-stm.c | 1 + .../hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tpiu.c | 1 + include/linux/coresight.h | 191 +++++++++++++++++- 12 files changed, 241 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index a61313f320bd..867c932c7b26 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -551,6 +551,7 @@ static int catu_probe(struct amba_device *adev, const struct amba_id *id) dev->platform_data = pdata; drvdata->base = base; + catu_desc.access = CSDEV_ACCESS_IOMEM(base); catu_desc.pdata = pdata; catu_desc.dev = dev; catu_desc.groups = catu_groups; diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 4ba801dffcb7..a38af8f0831b 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1458,6 +1458,48 @@ int coresight_timeout(void __iomem *addr, u32 offset, int position, int value) } EXPORT_SYMBOL_GPL(coresight_timeout); +u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) +{ + return csdev_access_relaxed_read32(&csdev->access, offset); +} + +u32 coresight_read32(struct coresight_device *csdev, u32 offset) +{ + return csdev_access_read32(&csdev->access, offset); +} + +void coresight_relaxed_write32(struct coresight_device *csdev, + u32 val, u32 offset) +{ + csdev_access_relaxed_write32(&csdev->access, val, offset); +} + +void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) +{ + csdev_access_write32(&csdev->access, val, offset); +} + +u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset) +{ + return csdev_access_relaxed_read64(&csdev->access, offset); +} + +u64 coresight_read64(struct coresight_device *csdev, u32 offset) +{ + return csdev_access_read64(&csdev->access, offset); +} + +void coresight_relaxed_write64(struct coresight_device *csdev, + u64 val, u32 offset) +{ + csdev_access_relaxed_write64(&csdev->access, val, offset); +} + +void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) +{ + csdev_access_write64(&csdev->access, val, offset); +} + /* * coresight_release_platform_data: Release references to the devices connected * to the output port of this device. @@ -1522,6 +1564,7 @@ struct coresight_device *coresight_register(struct coresight_desc *desc) csdev->type = desc->type; csdev->subtype = desc->subtype; csdev->ops = desc->ops; + csdev->access = desc->access; csdev->orphan = false; csdev->dev.type = &coresight_dev_type[desc->type]; diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index 61dbc1afd8da..b38a8db5f252 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -870,6 +870,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base); drvdata->base = base; + cti_desc.access = CSDEV_ACCESS_IOMEM(base); dev_set_drvdata(dev, drvdata); diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 0cf6f0b947b6..cc742561a986 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -757,6 +757,7 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base); drvdata->base = base; + desc.access = CSDEV_ACCESS_IOMEM(base); spin_lock_init(&drvdata->spinlock); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 5bf5a5a4ce6d..3b7837cbe376 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -839,6 +839,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base); drvdata->base = base; + desc.access = CSDEV_ACCESS_IOMEM(base); spin_lock_init(&drvdata->spinlock); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 0924c376e35a..b9e01357ffad 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1626,6 +1626,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base); drvdata->base = base; + desc.access = CSDEV_ACCESS_IOMEM(base); spin_lock_init(&drvdata->spinlock); diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 071c723227db..8f7c40d7d8d6 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -242,6 +242,7 @@ static int funnel_probe(struct device *dev, struct resource *res) } drvdata->base = base; desc.groups = coresight_funnel_groups; + desc.access = CSDEV_ACCESS_IOMEM(base); } dev_set_drvdata(dev, drvdata); diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 7e2a2b7f503f..205756fab729 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -254,6 +254,7 @@ static int replicator_probe(struct device *dev, struct resource *res) } drvdata->base = base; desc.groups = replicator_groups; + desc.access = CSDEV_ACCESS_IOMEM(base); } if (fwnode_property_present(dev_fwnode(dev), diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 99791773f682..41d9a922c2d4 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -884,6 +884,7 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) if (IS_ERR(base)) return PTR_ERR(base); drvdata->base = base; + desc.access = CSDEV_ACCESS_IOMEM(base); ret = stm_get_stimulus_area(dev, &ch_res); if (ret) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 8169dff5a9f6..e61b75be66b6 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -456,6 +456,7 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) } drvdata->base = base; + desc.access = CSDEV_ACCESS_IOMEM(base); spin_lock_init(&drvdata->spinlock); diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index d5dfee9ee556..6ca396799883 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -149,6 +149,7 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base); drvdata->base = base; + desc.access = CSDEV_ACCESS_IOMEM(base); /* Disable tpiu to support older devices */ tpiu_disable_hw(drvdata); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 7d3c87e5b97c..6107cf4021d3 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -7,6 +7,7 @@ #define _LINUX_CORESIGHT_H #include +#include #include #include @@ -114,6 +115,32 @@ struct coresight_platform_data { struct coresight_connection *conns; }; +/** + * struct csdev_access - Abstraction of a CoreSight device access. + * + * @io_mem : True if the device has memory mapped I/O + * @base : When io_mem == true, base address of the component + * @read : Read from the given "offset" of the given instance. + * @write : Write "val" to the given "offset". + */ +struct csdev_access { + bool io_mem; + union { + void __iomem *base; + struct { + u64 (*read)(u32 offset, bool relaxed, bool _64bit); + void (*write)(u64 val, u32 offset, bool relaxed, + bool _64bit); + }; + }; +}; + +#define CSDEV_ACCESS_IOMEM(_addr) \ + ((struct csdev_access) { \ + .io_mem = true, \ + .base = (_addr), \ + }) + /** * struct coresight_desc - description of a component required from drivers * @type: as defined by @coresight_dev_type. @@ -125,6 +152,7 @@ struct coresight_platform_data { * @groups: operations specific to this component. These will end up * in the component's sysfs sub-directory. * @name: name for the coresight device, also shown under sysfs. + * @access: Describe access to the device */ struct coresight_desc { enum coresight_dev_type type; @@ -134,6 +162,7 @@ struct coresight_desc { struct device *dev; const struct attribute_group **groups; const char *name; + struct csdev_access access; }; /** @@ -173,7 +202,8 @@ struct coresight_sysfs_link { * @type: as defined by @coresight_dev_type. * @subtype: as defined by @coresight_dev_subtype. * @ops: generic operations for this component, as defined - by @coresight_ops. + * by @coresight_ops. + * @access: Device i/o access abstraction for this device. * @dev: The device entity associated to this component. * @refcnt: keep track of what is in use. * @orphan: true if the component has connections that haven't been linked. @@ -195,6 +225,7 @@ struct coresight_device { enum coresight_dev_type type; union coresight_dev_subtype subtype; const struct coresight_ops *ops; + struct csdev_access access; struct device dev; atomic_t *refcnt; bool orphan; @@ -326,6 +357,104 @@ struct coresight_ops { }; #if IS_ENABLED(CONFIG_CORESIGHT) + +static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, + u32 offset) +{ + if (likely(csa->io_mem)) + return readl_relaxed(csa->base + offset); + + return csa->read(offset, true, false); +} + +static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) +{ + if (likely(csa->io_mem)) + return readl(csa->base + offset); + + return csa->read(offset, false, false); +} + +static inline void csdev_access_relaxed_write32(struct csdev_access *csa, + u32 val, u32 offset) +{ + if (likely(csa->io_mem)) + writel_relaxed(val, csa->base + offset); + else + csa->write(val, offset, true, false); +} + +static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) +{ + if (likely(csa->io_mem)) + writel(val, csa->base + offset); + else + csa->write(val, offset, false, false); +} + +#ifdef CONFIG_64BIT + +static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, + u32 offset) +{ + if (likely(csa->io_mem)) + return readq_relaxed(csa->base + offset); + + return csa->read(offset, true, true); +} + +static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) +{ + if (likely(csa->io_mem)) + return readq(csa->base + offset); + + return csa->read(offset, false, true); +} + +static inline void csdev_access_relaxed_write64(struct csdev_access *csa, + u64 val, u32 offset) +{ + if (likely(csa->io_mem)) + writeq_relaxed(val, csa->base + offset); + else + csa->write(val, offset, true, true); +} + +static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) +{ + if (likely(csa->io_mem)) + writeq(val, csa->base + offset); + else + csa->write(val, offset, false, true); +} + +#else /* !CONFIG_64BIT */ + +static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, + u32 offset) +{ + WARN_ON(1); + return 0; +} + +static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) +{ + WARN_ON(1); + return 0; +} + +static inline void csdev_access_relaxed_write64(struct csdev_access *csa, + u64 val, u32 offset) +{ + WARN_ON(1); +} + +static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) +{ + WARN_ON(1); +} +#endif /* CONFIG_64BIT */ + extern struct coresight_device * coresight_register(struct coresight_desc *desc); extern void coresight_unregister(struct coresight_device *csdev); @@ -343,6 +472,18 @@ extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, struct device *dev); extern bool coresight_loses_context_with_cpu(struct device *dev); + +u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); +u32 coresight_read32(struct coresight_device *csdev, u32 offset); +void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); +void coresight_relaxed_write32(struct coresight_device *csdev, + u32 val, u32 offset); +u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); +u64 coresight_read64(struct coresight_device *csdev, u32 offset); +void coresight_relaxed_write64(struct coresight_device *csdev, + u64 val, u32 offset); +void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); + #else static inline struct coresight_device * coresight_register(struct coresight_desc *desc) { return NULL; } @@ -369,10 +510,54 @@ static inline bool coresight_loses_context_with_cpu(struct device *dev) { return false; } -#endif + +static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) +{ + WARN_ON_ONCE(1); + return 0; +} + +static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset) +{ + WARN_ON_ONCE(1); + return 0; +} + +static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) +{ +} + +static inline void coresight_relaxed_write32(struct coresight_device *csdev, + u32 val, u32 offset) +{ +} + +static inline u64 coresight_relaxed_read64(struct coresight_device *csdev, + u32 offset) +{ + WARN_ON_ONCE(1); + return 0; +} + +static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset) +{ + WARN_ON_ONCE(1); + return 0; +} + +static inline void coresight_relaxed_write64(struct coresight_device *csdev, + u64 val, u32 offset) +{ +} + +static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) +{ +} + +#endif /* IS_ENABLED(CONFIG_CORESIGHT) */ extern int coresight_get_cpu(struct device *dev); struct coresight_platform_data *coresight_get_platform_data(struct device *dev); -#endif +#endif /* _LINUX_COREISGHT_H */ From patchwork Mon Feb 1 18:13:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85E71C433DB for ; Mon, 1 Feb 2021 18:15:58 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3238364EA0 for ; Mon, 1 Feb 2021 18:15:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3238364EA0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fR9FTHE4qHmINsJjqsOtzZzwND1mbw4zMi0jDuQBbgg=; b=BZnlRMHWFvYNjBhLVaGBQgZ1j Tj6jAVtI4M5NQ3eX8Us3YrtiocPvcNW6FKSh8x+tNMmcbkSSfJha5lVVN/d0pfhqg8Hlndj2G81Av 5yqBJsv0RJcsgDzla2Xox2J5/44EPwdolvbfnOCBpshBqil+sVyESqWWFN1CGOi3zeIPI5rgRcZFG keHQM8EAhFOXfGao4fjIVQ4rukSp65SKuJrVFtCf2wv1jemelHV45lOYBAh654fa9vLv9vTJG16Ud lPKvnEf+/zTUZVkG8f5eT9B6xIgxmXycHXL6aAbfSiye+VpnfWOFuhQpBhUlKfqr98rD1+Ix+PHiJ zDdutw3Tg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diQ-00038k-Me; Mon, 01 Feb 2021 18:14:22 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di5-0002x4-UB for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:05 +0000 Received: by mail-pj1-x1029.google.com with SMTP id s24so73036pjp.5 for ; Mon, 01 Feb 2021 10:14:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vkMHICiY0sjvBDYwRE3nRQtY0zoUuO0WMFpN8g7r2A8=; b=vlqpMcOccLHMKfyFmm0VBfziORVRLmt8yzV7ICOPBJoFkdzNIO89ZyGaqR6J8hhNNO 7ZlPjJYgqQ5Xvxzcqsep6TF2M15aBK7XgBiu3Zj5wTtj29UpvPf4Iw65f4NgrOSbiUAa +2z+x9Uj+mEvqFDjGraGjhnlPUpfpMLFtaMrbzhUENbXpYlloBTlZEEucKDwvBKCCDwm CbYprpqJVEe6Xu+tfGi9O0gln6Glwsi6U3N5VVWQGUzGLYagUh7fingrvtPAYzft+w9K yhki4VKGcLBRGm/WNKttqksUzJkJHhFE0FCiq2kqRiS9YRbR6vWQJGHQ0OvvLN+qHP38 8xdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vkMHICiY0sjvBDYwRE3nRQtY0zoUuO0WMFpN8g7r2A8=; b=iWj5pvtyfjDCfBHkk/Rq3Yq+/Hf0qbsLGcKdZlSGOvYJ98STyk6XJ1IQMFkK9AtmZf 290YhxxgwZ9coBv9BIBPZtuzWzSOTe2dXBadI1gPqdARTH5Y2rYaTL6MQokWy/EVHVP7 JLlDDkJahpbUA7J50dm9qHcYGCziOJ2L1TO4Rc9A50I4IPKF9oMzLdSZu4txQu4nYy1Q jNPbuN3HIdZ/VR3j4hfMISxTrJ0IVuOAeXmNd8/tkYDDO+WE7NCptIEI/vAeEDLMKuvb AvAQ138x4SVXPd6r1IZmaa1A70evFWI7z0mmh74awri4QHXoH4dxdbe4wSqLlWlFZXM5 a86A== X-Gm-Message-State: AOAM531YUuIiEB98I5V/0ytvJxOmS5k4xbyA2cQUdCIpGdTPIQoPZRA9 X3rz8neurvDuLJ6ADMmVder9iEk+XEGR0Q== X-Google-Smtp-Source: ABdhPJyztrTnQycZMCgCHBeSSeVduujWZcTuRldzwD/RBoN4blZFdcuzJgo7+pc9q0RlJZ9/uuBZ2Q== X-Received: by 2002:a17:902:6b45:b029:e0:7a3:a8c with SMTP id g5-20020a1709026b45b02900e007a30a8cmr19048550plt.1.1612203239599; Mon, 01 Feb 2021 10:13:59 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.13.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:13:58 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 06/31] coresight: tpiu: Prepare for using coresight device access abstraction Date: Mon, 1 Feb 2021 11:13:26 -0700 Message-Id: <20210201181351.1475223-7-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131402_092322_E9158515 X-CRM114-Status: GOOD ( 17.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose Prepare the TPIU driver to make use of the CoreSight device access abstraction layer. The driver touches the device even before the coresight device is registered. Thus we could be accessing the devices without a csdev. As we are about to use the abstraction layer for accessing the device, pass in the access directly to avoid having to deal with the un-initialised csdev. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-5-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tpiu.c | 30 +++++++++----------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index 6ca396799883..a12b6ee0a576 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -60,49 +60,45 @@ struct tpiu_drvdata { struct coresight_device *csdev; }; -static void tpiu_enable_hw(struct tpiu_drvdata *drvdata) +static void tpiu_enable_hw(struct csdev_access *csa) { - CS_UNLOCK(drvdata->base); + CS_UNLOCK(csa->base); /* TODO: fill this up */ - CS_LOCK(drvdata->base); + CS_LOCK(csa->base); } static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused) { - struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - tpiu_enable_hw(drvdata); + tpiu_enable_hw(&csdev->access); atomic_inc(csdev->refcnt); dev_dbg(&csdev->dev, "TPIU enabled\n"); return 0; } -static void tpiu_disable_hw(struct tpiu_drvdata *drvdata) +static void tpiu_disable_hw(struct csdev_access *csa) { - CS_UNLOCK(drvdata->base); + CS_UNLOCK(csa->base); /* Clear formatter and stop on flush */ - writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR); + csdev_access_relaxed_write32(csa, FFCR_STOP_FI, TPIU_FFCR); /* Generate manual flush */ - writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR); + csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR); /* Wait for flush to complete */ - coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); + coresight_timeout(csa->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); /* Wait for formatter to stop */ - coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); + coresight_timeout(csa->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); - CS_LOCK(drvdata->base); + CS_LOCK(csa->base); } static int tpiu_disable(struct coresight_device *csdev) { - struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - if (atomic_dec_return(csdev->refcnt)) return -EBUSY; - tpiu_disable_hw(drvdata); + tpiu_disable_hw(&csdev->access); dev_dbg(&csdev->dev, "TPIU disabled\n"); return 0; @@ -152,7 +148,7 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) desc.access = CSDEV_ACCESS_IOMEM(base); /* Disable tpiu to support older devices */ - tpiu_disable_hw(drvdata); + tpiu_disable_hw(&desc.access); pdata = coresight_get_platform_data(dev); if (IS_ERR(pdata)) From patchwork Mon Feb 1 18:13:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 957E9C433E6 for ; Mon, 1 Feb 2021 18:16:39 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 280BC64DE1 for ; Mon, 1 Feb 2021 18:16:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 280BC64DE1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DeLT2BlCX9ei9oqCwS7o36/BewEdCaGG56lwdwNVuJ4=; b=fp3FWbdk7EUaMkJvYbuVMLXZB O1qyD0ZN1UMbwaUwx1PTWZ/6m6cjUy5KKerNNlOSa5y113/5Au4v3ip3HwzBh0lgI8jvbZlYp2E7q RWgfMMp/PqKAWE57XBjDEGgMsnoYIXmlR8GHbD30Niw7qnFAiaaPXXlY/CWE1u+Mkp6LQeoEFw0Vn 8IZPvjT9luErDxhM7g1naoQxfaIV8UXrwG5pwaWCHcuypVjK6aHD9tnF9xJ/8KC0LmIxgyrM7NonG Yn/Alf98i2rqswBtnXFB/bsVFXEt6Lw62mgvBuQA0wLd5WDstRu4pGqZ/JMU1fMBSSJqQVInEqC2H VkHZMQD2g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diq-0003K0-Ku; Mon, 01 Feb 2021 18:14:48 +0000 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di6-0002yd-UL for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:11 +0000 Received: by mail-pj1-x1033.google.com with SMTP id m12so75528pjs.4 for ; Mon, 01 Feb 2021 10:14:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z3osC3oDSziejkHJJ1wP12+ZD9D+IsOQLgnD9w5tLSo=; b=XmI4RpqF3OBMe5HxTc6r7wAz27oljyunE8/sCHbJ73GfbHL5vJG8UndJZBiXj8MDVh FCpuhg2yPTNw/djt0vn1ztSEjKRUxLU98H2+uedyEpTnB5YsBaBYWlDQZx34A01SxKaP BanMBheF4ddgLGCsCYd+MhwJ79crGLTRpsGR+xO99LGaWrHO4AG43EyTrtaRpyGS3CYr g62ayDbrssH/QxX6O7fr+VCBAx/XGqxUvivceNUauJrPBZa9/XigRBtlLAO4zAykZBbd CtPBOUQSqsf5LVgv42ESDEO/w+8kqOd5NTgCS2EcU6U9gXke5YVDTGdsF/4LsQHU04PC Ixag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z3osC3oDSziejkHJJ1wP12+ZD9D+IsOQLgnD9w5tLSo=; b=H2rXs2SqfLYw3J6kma2QDnTcslzgCxDwYNInnBDgfU5+XQEml5a32jTpSY0FWTqBmx qv4GJXAFAp5k9Ux/6tx5Y4MMtlwx52uepk7Y1M434p236Wv/B7uuegYXXvQojMtzQurV u1HcUisVYxVgdsxpODIDt9ijbzIxmfR5RG97sjKkPqNaDea2ghxOMvsyY7ysCk+JkCiC gPYKgJV/wcwLypuE4UrNrFrfw8O9nOorUbrADX/1eft+9s1wva1YKlUlcPgeYgKTvWT/ 3IFUg6zBG2gJncrkDXggOsLRiiiALXRXFSwPRFbceXY2ksFK0RDfxrFsNBlDIUw2kssK BfZA== X-Gm-Message-State: AOAM533ZyyrVRpKW/D3z+21go1CFrHsaDIQVGOpeN1vTUXOKldprUT80 qLpgiZbrNaWxtkkrW3iL22LKkA== X-Google-Smtp-Source: ABdhPJzckXMg+RkuOTjrLPkoK8IRccYAKfq3/26RezkX88p55MmEuaGWs6hehbmle2YB39/oKFfLHA== X-Received: by 2002:a17:90a:cf:: with SMTP id v15mr96207pjd.221.1612203240643; Mon, 01 Feb 2021 10:14:00 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.13.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:00 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 07/31] coresight: Convert coresight_timeout to use access abstraction Date: Mon, 1 Feb 2021 11:13:27 -0700 Message-Id: <20210201181351.1475223-8-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131403_145510_21CF57D9 X-CRM114-Status: GOOD ( 23.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose Convert the generic routines to use the new access abstraction layer gradually, starting with coresigth_timeout. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-6-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-catu.c | 5 ++-- drivers/hwtracing/coresight/coresight-core.c | 13 ++++---- drivers/hwtracing/coresight/coresight-etb10.c | 5 ++-- .../coresight/coresight-etm4x-core.c | 30 ++++++++++++------- drivers/hwtracing/coresight/coresight-stm.c | 3 +- .../hwtracing/coresight/coresight-tmc-core.c | 15 ++++++---- drivers/hwtracing/coresight/coresight-tpiu.c | 4 +-- include/linux/coresight.h | 11 +++++-- 8 files changed, 54 insertions(+), 32 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index 867c932c7b26..d6097454d399 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -401,8 +401,9 @@ static const struct attribute_group *catu_groups[] = { static inline int catu_wait_for_ready(struct catu_drvdata *drvdata) { - return coresight_timeout(drvdata->base, - CATU_STATUS, CATU_STATUS_READY, 1); + struct csdev_access *csa = &drvdata->csdev->access; + + return coresight_timeout(csa, CATU_STATUS, CATU_STATUS_READY, 1); } static int catu_enable_hw(struct catu_drvdata *drvdata, void *data) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index a38af8f0831b..74985068f325 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1418,23 +1418,24 @@ static void coresight_remove_conns(struct coresight_device *csdev) } /** - * coresight_timeout - loop until a bit has changed to a specific state. - * @addr: base address of the area of interest. - * @offset: address of a register, starting from @addr. + * coresight_timeout - loop until a bit has changed to a specific register + * state. + * @csa: coresight device access for the device + * @offset: Offset of the register from the base of the device. * @position: the position of the bit of interest. * @value: the value the bit should have. * * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if * TIMEOUT_US has elapsed, which ever happens first. */ - -int coresight_timeout(void __iomem *addr, u32 offset, int position, int value) +int coresight_timeout(struct csdev_access *csa, u32 offset, + int position, int value) { int i; u32 val; for (i = TIMEOUT_US; i > 0; i--) { - val = __raw_readl(addr + offset); + val = csdev_access_read32(csa, offset); /* waiting on the bit to go from 0 to 1 */ if (value) { if (val & BIT(position)) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index cc742561a986..0f664aeeda93 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -252,6 +252,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) { u32 ffcr; struct device *dev = &drvdata->csdev->dev; + struct csdev_access *csa = &drvdata->csdev->access; CS_UNLOCK(drvdata->base); @@ -263,7 +264,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) ffcr |= ETB_FFCR_FON_MAN; writel_relaxed(ffcr, drvdata->base + ETB_FFCR); - if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) { + if (coresight_timeout(csa, ETB_FFCR, ETB_FFCR_BIT, 0)) { dev_err(dev, "timeout while waiting for completion of Manual Flush\n"); } @@ -271,7 +272,7 @@ static void __etb_disable_hw(struct etb_drvdata *drvdata) /* disable trace capture */ writel_relaxed(0x0, drvdata->base + ETB_CTL_REG); - if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) { + if (coresight_timeout(csa, ETB_FFSR, ETB_FFSR_BIT, 1)) { dev_err(dev, "timeout while waiting for Formatter to Stop\n"); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index b9e01357ffad..180bb6ed9090 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -217,7 +217,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; struct etmv4_config *config = &drvdata->config; - struct device *etm_dev = &drvdata->csdev->dev; + struct coresight_device *csdev = drvdata->csdev; + struct device *etm_dev = &csdev->dev; + struct csdev_access *csa = &csdev->access; CS_UNLOCK(drvdata->base); etm4_enable_arch_specific(drvdata); @@ -232,7 +234,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) writel_relaxed(0, drvdata->base + TRCPRGCTLR); /* wait for TRCSTATR.IDLE to go up */ - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); if (drvdata->nr_pe) @@ -323,7 +325,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) writel_relaxed(1, drvdata->base + TRCPRGCTLR); /* wait for TRCSTATR.IDLE to go back down to '0' */ - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); @@ -587,7 +589,9 @@ static void etm4_disable_hw(void *info) u32 control; struct etmv4_drvdata *drvdata = info; struct etmv4_config *config = &drvdata->config; - struct device *etm_dev = &drvdata->csdev->dev; + struct coresight_device *csdev = drvdata->csdev; + struct device *etm_dev = &csdev->dev; + struct csdev_access *csa = &csdev->access; int i; CS_UNLOCK(drvdata->base); @@ -615,8 +619,7 @@ static void etm4_disable_hw(void *info) writel_relaxed(control, drvdata->base + TRCPRGCTLR); /* wait for TRCSTATR.PMSTABLE to go to '1' */ - if (coresight_timeout(drvdata->base, TRCSTATR, - TRCSTATR_PMSTABLE_BIT, 1)) + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) dev_err(etm_dev, "timeout while waiting for PM stable Trace Status\n"); @@ -1272,7 +1275,15 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) { int i, ret = 0; struct etmv4_save_state *state; - struct device *etm_dev = &drvdata->csdev->dev; + struct coresight_device *csdev = drvdata->csdev; + struct csdev_access *csa; + struct device *etm_dev; + + if (WARN_ON(!csdev)) + return -ENODEV; + + etm_dev = &csdev->dev; + csa = &csdev->access; /* * As recommended by 3.4.1 ("The procedure when powering down the PE") @@ -1287,8 +1298,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) etm4_os_lock(drvdata); /* wait for TRCSTATR.PMSTABLE to go up */ - if (coresight_timeout(drvdata->base, TRCSTATR, - TRCSTATR_PMSTABLE_BIT, 1)) { + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) { dev_err(etm_dev, "timeout while waiting for PM Stable Status\n"); etm4_os_unlock(drvdata); @@ -1377,7 +1387,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcpdcr = readl(drvdata->base + TRCPDCR); /* wait for TRCSTATR.IDLE to go up */ - if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { + if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); etm4_os_unlock(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 41d9a922c2d4..5927316d7a03 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -258,6 +258,7 @@ static void stm_disable(struct coresight_device *csdev, struct perf_event *event) { struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct csdev_access *csa = &csdev->access; /* * For as long as the tracer isn't disabled another entity can't @@ -270,7 +271,7 @@ static void stm_disable(struct coresight_device *csdev, spin_unlock(&drvdata->spinlock); /* Wait until the engine has completely stopped */ - coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0); + coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0); pm_runtime_put(csdev->dev.parent); diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index e61b75be66b6..4dc1ea2c19b5 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -33,16 +33,20 @@ DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) { + struct coresight_device *csdev = drvdata->csdev; + struct csdev_access *csa = &csdev->access; + /* Ensure formatter, unformatter and hardware fifo are empty */ - if (coresight_timeout(drvdata->base, - TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { - dev_err(&drvdata->csdev->dev, + if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { + dev_err(&csdev->dev, "timeout while waiting for TMC to be Ready\n"); } } void tmc_flush_and_stop(struct tmc_drvdata *drvdata) { + struct coresight_device *csdev = drvdata->csdev; + struct csdev_access *csa = &csdev->access; u32 ffcr; ffcr = readl_relaxed(drvdata->base + TMC_FFCR); @@ -51,9 +55,8 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata) ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT); writel_relaxed(ffcr, drvdata->base + TMC_FFCR); /* Ensure flush completes */ - if (coresight_timeout(drvdata->base, - TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { - dev_err(&drvdata->csdev->dev, + if (coresight_timeout(csa, TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) { + dev_err(&csdev->dev, "timeout while waiting for completion of Manual Flush\n"); } diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c index a12b6ee0a576..2ec057892799 100644 --- a/drivers/hwtracing/coresight/coresight-tpiu.c +++ b/drivers/hwtracing/coresight/coresight-tpiu.c @@ -86,9 +86,9 @@ static void tpiu_disable_hw(struct csdev_access *csa) /* Generate manual flush */ csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR); /* Wait for flush to complete */ - coresight_timeout(csa->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); + coresight_timeout(csa, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); /* Wait for formatter to stop */ - coresight_timeout(csa->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); + coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); CS_LOCK(csa->base); } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 6107cf4021d3..18bc7f9fb041 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -460,7 +460,7 @@ coresight_register(struct coresight_desc *desc); extern void coresight_unregister(struct coresight_device *csdev); extern int coresight_enable(struct coresight_device *csdev); extern void coresight_disable(struct coresight_device *csdev); -extern int coresight_timeout(void __iomem *addr, u32 offset, +extern int coresight_timeout(struct csdev_access *csa, u32 offset, int position, int value); extern int coresight_claim_device(void __iomem *base); @@ -491,8 +491,13 @@ static inline void coresight_unregister(struct coresight_device *csdev) {} static inline int coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } static inline void coresight_disable(struct coresight_device *csdev) {} -static inline int coresight_timeout(void __iomem *addr, u32 offset, - int position, int value) { return 1; } + +static inline int coresight_timeout(struct csdev_access *csa, u32 offset, + int position, int value) +{ + return 1; +} + static inline int coresight_claim_device_unlocked(void __iomem *base) { return -EINVAL; From patchwork Mon Feb 1 18:13:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC26BC433E0 for ; Mon, 1 Feb 2021 18:16:58 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 657F964EA0 for ; Mon, 1 Feb 2021 18:16:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 657F964EA0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=CsJC16X7/U7JeIvbbCL5SyZMvSl1vG3I6tDfZd0EyFc=; b=JflZowsJDBesawsMCrpY29IkN 03/5Dai1PX4qvyih+KrkecmGB8CLx0GNBN1oIpHDK92OXOHoGtRzcE1KNapdGh4c5/K5OSX14tB2P OKCPdvlEXYm4sza7hsTsecHAmHZ4C4pWO3mq5/eTpHnZwb3OxeXb+0ABpZLkgEKolfCQ3OaL5TdGo +MOpwHz+edQXxaBxOGJBsBLxdMxdJWlxied9AP9b7kvoGmAgRxvX8WLaBkSjhPGlUemQPkgeC3Bch s9Ng3kzmkRe4eK/FiEXzMyzhV1eWAuWshVS15o1z4DtgiSV98jamL4+Mis/RElSOq5ar3EbMk+aqq PETgth++A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dj3-0003O2-B6; Mon, 01 Feb 2021 18:15:01 +0000 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di8-0002yz-8W for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:16 +0000 Received: by mail-pl1-x62d.google.com with SMTP id p21so735921pld.8 for ; Mon, 01 Feb 2021 10:14:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9RoyrFdDmxBYKNm+NOAzPYhkWrxpasXdG95XWPP1dB8=; b=vbYqWd6IKRuko64yPg3dFeLqvThsqht8YJftaTy3IVQHTkwU68hOyY/s4GIHuH4CPX djId9Yd9VZiZUujH4/oI0fn4zFI4LocbdyFpgAgb/d0rMa5h9gag908tKZRK4LF4UR4K /FN1BwBmTy6TIA3CAS3KeR7vPqZicRaleIexqt5sPuoxU3gMfr/9fxmVgr/n2Wsgtux1 87PmCXnKLUEHLcYRnD/u6csfvQreGSdpGKcUnxPc9TZj7nRksJhlx7zTbrhS5iKMI3gR WC9V9EzTgvwYc3bAMG9x07AKrYiFonLz4rfoz8QsurE4HDhBB9iZXpz8SLOayIGoPxDR l9+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9RoyrFdDmxBYKNm+NOAzPYhkWrxpasXdG95XWPP1dB8=; b=N5vW34aDpS9x70b13UqvNNTTs2vka7YZ1w4RD7BnHirO/Dx1UemOgW42Uvq2BuQsSi 1vLRxMc9RMIDmA6C/fYteePRChJGdOGJxyvBZpEm0kuKgc77sSW6mfQ0YBdsrV66s+yj RaRwfhl/G3J5glzIrW+QuDHHyV7oTBNsCMnr0/ZSFN6B/A2yEN+FodDOkCfFCe9P7IJa YwBbTV4s+qjkAQr+qvWy+3EMbM0TvUT+EuK4PU6nnFrXyopzDAQmGhETqWeGkX8zLN72 Yg30D9FsfjlckURvHR6jsuYxD+TxzhPLeV4+jwTHMMUljKCM4bHWa4oOg10R05NR0qfJ cc+w== X-Gm-Message-State: AOAM5328F7wkPq0SWZyJNo8HMpwiXHjKizyf8WALnWSyJy5hjfPXNSHf AgdJlBjIt1+fLRv4yxB5fQyeXubiEeVPOg== X-Google-Smtp-Source: ABdhPJx775vhWkvgAgHtBmYkPip1Onf+5ZUw8R5616h5PqYyscU6BGOhnxnSaUOUFEdTz6oSxhH/bw== X-Received: by 2002:a17:902:e54e:b029:de:8c70:2ec4 with SMTP id n14-20020a170902e54eb02900de8c702ec4mr18955290plf.56.1612203241871; Mon, 01 Feb 2021 10:14:01 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:01 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 08/31] coresight: Convert claim/disclaim operations to use access wrappers Date: Mon, 1 Feb 2021 11:13:28 -0700 Message-Id: <20210201181351.1475223-9-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131404_414087_F6673C7A X-CRM114-Status: GOOD ( 21.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose Convert the generic CLAIM tag management APIs to use the device access layer abstraction. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-7-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-catu.c | 6 +- drivers/hwtracing/coresight/coresight-core.c | 66 +++++++++++-------- .../hwtracing/coresight/coresight-cti-core.c | 17 +++-- drivers/hwtracing/coresight/coresight-etb10.c | 4 +- .../coresight/coresight-etm3x-core.c | 8 ++- .../coresight/coresight-etm4x-core.c | 4 +- .../hwtracing/coresight/coresight-funnel.c | 6 +- .../coresight/coresight-replicator.c | 12 ++-- .../hwtracing/coresight/coresight-tmc-etf.c | 10 +-- .../hwtracing/coresight/coresight-tmc-etr.c | 4 +- include/linux/coresight.h | 16 ++--- 11 files changed, 91 insertions(+), 62 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index d6097454d399..9a0b9ce4a7da 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -412,6 +412,7 @@ static int catu_enable_hw(struct catu_drvdata *drvdata, void *data) u32 control, mode; struct etr_buf *etr_buf = data; struct device *dev = &drvdata->csdev->dev; + struct coresight_device *csdev = drvdata->csdev; if (catu_wait_for_ready(drvdata)) dev_warn(dev, "Timeout while waiting for READY\n"); @@ -422,7 +423,7 @@ static int catu_enable_hw(struct catu_drvdata *drvdata, void *data) return -EBUSY; } - rc = coresight_claim_device_unlocked(drvdata->base); + rc = coresight_claim_device_unlocked(csdev); if (rc) return rc; @@ -466,9 +467,10 @@ static int catu_disable_hw(struct catu_drvdata *drvdata) { int rc = 0; struct device *dev = &drvdata->csdev->dev; + struct coresight_device *csdev = drvdata->csdev; catu_write_control(drvdata, 0); - coresight_disclaim_device_unlocked(drvdata->base); + coresight_disclaim_device_unlocked(csdev); if (catu_wait_for_ready(drvdata)) { dev_info(dev, "Timeout while waiting for READY\n"); rc = -EAGAIN; diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 74985068f325..0062c8935653 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -145,30 +145,32 @@ static int coresight_find_link_outport(struct coresight_device *csdev, return -ENODEV; } -static inline u32 coresight_read_claim_tags(void __iomem *base) +static inline u32 coresight_read_claim_tags(struct coresight_device *csdev) { - return readl_relaxed(base + CORESIGHT_CLAIMCLR); + return csdev_access_relaxed_read32(&csdev->access, CORESIGHT_CLAIMCLR); } -static inline bool coresight_is_claimed_self_hosted(void __iomem *base) +static inline bool coresight_is_claimed_self_hosted(struct coresight_device *csdev) { - return coresight_read_claim_tags(base) == CORESIGHT_CLAIM_SELF_HOSTED; + return coresight_read_claim_tags(csdev) == CORESIGHT_CLAIM_SELF_HOSTED; } -static inline bool coresight_is_claimed_any(void __iomem *base) +static inline bool coresight_is_claimed_any(struct coresight_device *csdev) { - return coresight_read_claim_tags(base) != 0; + return coresight_read_claim_tags(csdev) != 0; } -static inline void coresight_set_claim_tags(void __iomem *base) +static inline void coresight_set_claim_tags(struct coresight_device *csdev) { - writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMSET); + csdev_access_relaxed_write32(&csdev->access, CORESIGHT_CLAIM_SELF_HOSTED, + CORESIGHT_CLAIMSET); isb(); } -static inline void coresight_clear_claim_tags(void __iomem *base) +static inline void coresight_clear_claim_tags(struct coresight_device *csdev) { - writel_relaxed(CORESIGHT_CLAIM_SELF_HOSTED, base + CORESIGHT_CLAIMCLR); + csdev_access_relaxed_write32(&csdev->access, CORESIGHT_CLAIM_SELF_HOSTED, + CORESIGHT_CLAIMCLR); isb(); } @@ -182,27 +184,33 @@ static inline void coresight_clear_claim_tags(void __iomem *base) * Called with CS_UNLOCKed for the component. * Returns : 0 on success */ -int coresight_claim_device_unlocked(void __iomem *base) +int coresight_claim_device_unlocked(struct coresight_device *csdev) { - if (coresight_is_claimed_any(base)) + if (WARN_ON(!csdev)) + return -EINVAL; + + if (coresight_is_claimed_any(csdev)) return -EBUSY; - coresight_set_claim_tags(base); - if (coresight_is_claimed_self_hosted(base)) + coresight_set_claim_tags(csdev); + if (coresight_is_claimed_self_hosted(csdev)) return 0; /* There was a race setting the tags, clean up and fail */ - coresight_clear_claim_tags(base); + coresight_clear_claim_tags(csdev); return -EBUSY; } EXPORT_SYMBOL_GPL(coresight_claim_device_unlocked); -int coresight_claim_device(void __iomem *base) +int coresight_claim_device(struct coresight_device *csdev) { int rc; - CS_UNLOCK(base); - rc = coresight_claim_device_unlocked(base); - CS_LOCK(base); + if (WARN_ON(!csdev)) + return -EINVAL; + + CS_UNLOCK(csdev->access.base); + rc = coresight_claim_device_unlocked(csdev); + CS_LOCK(csdev->access.base); return rc; } @@ -212,11 +220,14 @@ EXPORT_SYMBOL_GPL(coresight_claim_device); * coresight_disclaim_device_unlocked : Clear the claim tags for the device. * Called with CS_UNLOCKed for the component. */ -void coresight_disclaim_device_unlocked(void __iomem *base) +void coresight_disclaim_device_unlocked(struct coresight_device *csdev) { - if (coresight_is_claimed_self_hosted(base)) - coresight_clear_claim_tags(base); + if (WARN_ON(!csdev)) + return; + + if (coresight_is_claimed_self_hosted(csdev)) + coresight_clear_claim_tags(csdev); else /* * The external agent may have not honoured our claim @@ -227,11 +238,14 @@ void coresight_disclaim_device_unlocked(void __iomem *base) } EXPORT_SYMBOL_GPL(coresight_disclaim_device_unlocked); -void coresight_disclaim_device(void __iomem *base) +void coresight_disclaim_device(struct coresight_device *csdev) { - CS_UNLOCK(base); - coresight_disclaim_device_unlocked(base); - CS_LOCK(base); + if (WARN_ON(!csdev)) + return; + + CS_UNLOCK(csdev->access.base); + coresight_disclaim_device_unlocked(csdev); + CS_LOCK(csdev->access.base); } EXPORT_SYMBOL_GPL(coresight_disclaim_device); diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index b38a8db5f252..0c81eb9603ae 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -102,7 +102,7 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) goto cti_state_unchanged; /* claim the device */ - rc = coresight_claim_device(drvdata->base); + rc = coresight_claim_device(drvdata->csdev); if (rc) goto cti_err_not_enabled; @@ -136,7 +136,7 @@ static void cti_cpuhp_enable_hw(struct cti_drvdata *drvdata) goto cti_hp_not_enabled; /* try to claim the device */ - if (coresight_claim_device(drvdata->base)) + if (coresight_claim_device(drvdata->csdev)) goto cti_hp_not_enabled; cti_write_all_hw_regs(drvdata); @@ -154,6 +154,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) { struct cti_config *config = &drvdata->config; struct device *dev = &drvdata->csdev->dev; + struct coresight_device *csdev = drvdata->csdev; spin_lock(&drvdata->spinlock); @@ -171,7 +172,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) writel_relaxed(0, drvdata->base + CTICONTROL); config->hw_enabled = false; - coresight_disclaim_device_unlocked(drvdata->base); + coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); spin_unlock(&drvdata->spinlock); pm_runtime_put(dev); @@ -655,6 +656,7 @@ static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, void *v) { struct cti_drvdata *drvdata; + struct coresight_device *csdev; unsigned int cpu = smp_processor_id(); int notify_res = NOTIFY_OK; @@ -662,6 +664,7 @@ static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, return NOTIFY_OK; drvdata = cti_cpu_drvdata[cpu]; + csdev = drvdata->csdev; if (WARN_ON_ONCE(drvdata->ctidev.cpu != cpu)) return NOTIFY_BAD; @@ -673,13 +676,13 @@ static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, /* CTI regs all static - we have a copy & nothing to save */ drvdata->config.hw_powered = false; if (drvdata->config.hw_enabled) - coresight_disclaim_device(drvdata->base); + coresight_disclaim_device(csdev); break; case CPU_PM_ENTER_FAILED: drvdata->config.hw_powered = true; if (drvdata->config.hw_enabled) { - if (coresight_claim_device(drvdata->base)) + if (coresight_claim_device(csdev)) drvdata->config.hw_enabled = false; } break; @@ -692,7 +695,7 @@ static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, /* check enable reference count to enable HW */ if (atomic_read(&drvdata->config.enable_req_count)) { /* check we can claim the device as we re-power */ - if (coresight_claim_device(drvdata->base)) + if (coresight_claim_device(csdev)) goto cti_notify_exit; drvdata->config.hw_enabled = true; @@ -736,7 +739,7 @@ static int cti_dying_cpu(unsigned int cpu) spin_lock(&drvdata->spinlock); drvdata->config.hw_powered = false; if (drvdata->config.hw_enabled) - coresight_disclaim_device(drvdata->base); + coresight_disclaim_device(drvdata->csdev); spin_unlock(&drvdata->spinlock); return 0; } diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 0f664aeeda93..74922c94f4b1 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -132,7 +132,7 @@ static void __etb_enable_hw(struct etb_drvdata *drvdata) static int etb_enable_hw(struct etb_drvdata *drvdata) { - int rc = coresight_claim_device(drvdata->base); + int rc = coresight_claim_device(drvdata->csdev); if (rc) return rc; @@ -345,7 +345,7 @@ static void etb_disable_hw(struct etb_drvdata *drvdata) { __etb_disable_hw(drvdata); etb_dump_hw(drvdata); - coresight_disclaim_device(drvdata->base); + coresight_disclaim_device(drvdata->csdev); } static int etb_disable(struct coresight_device *csdev) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 3b7837cbe376..29d4dba4bee9 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -358,10 +358,11 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) int i, rc; u32 etmcr; struct etm_config *config = &drvdata->config; + struct coresight_device *csdev = drvdata->csdev; CS_UNLOCK(drvdata->base); - rc = coresight_claim_device_unlocked(drvdata->base); + rc = coresight_claim_device_unlocked(csdev); if (rc) goto done; @@ -566,6 +567,7 @@ static void etm_disable_hw(void *info) int i; struct etm_drvdata *drvdata = info; struct etm_config *config = &drvdata->config; + struct coresight_device *csdev = drvdata->csdev; CS_UNLOCK(drvdata->base); etm_set_prog(drvdata); @@ -577,7 +579,7 @@ static void etm_disable_hw(void *info) config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i)); etm_set_pwrdwn(drvdata); - coresight_disclaim_device_unlocked(drvdata->base); + coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); @@ -602,7 +604,7 @@ static void etm_disable_perf(struct coresight_device *csdev) * power down the tracer. */ etm_set_pwrdwn(drvdata); - coresight_disclaim_device_unlocked(drvdata->base); + coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 180bb6ed9090..a041ad52737f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -226,7 +226,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4_os_unlock(drvdata); - rc = coresight_claim_device_unlocked(drvdata->base); + rc = coresight_claim_device_unlocked(csdev); if (rc) goto done; @@ -635,7 +635,7 @@ static void etm4_disable_hw(void *info) readl_relaxed(drvdata->base + TRCCNTVRn(i)); } - coresight_disclaim_device_unlocked(drvdata->base); + coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c index 8f7c40d7d8d6..38bebdddcbff 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -52,13 +52,14 @@ static int dynamic_funnel_enable_hw(struct funnel_drvdata *drvdata, int port) { u32 functl; int rc = 0; + struct coresight_device *csdev = drvdata->csdev; CS_UNLOCK(drvdata->base); functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL); /* Claim the device only when we enable the first slave */ if (!(functl & FUNNEL_ENSx_MASK)) { - rc = coresight_claim_device_unlocked(drvdata->base); + rc = coresight_claim_device_unlocked(csdev); if (rc) goto done; } @@ -101,6 +102,7 @@ static void dynamic_funnel_disable_hw(struct funnel_drvdata *drvdata, int inport) { u32 functl; + struct coresight_device *csdev = drvdata->csdev; CS_UNLOCK(drvdata->base); @@ -110,7 +112,7 @@ static void dynamic_funnel_disable_hw(struct funnel_drvdata *drvdata, /* Disclaim the device if none of the slaves are now active */ if (!(functl & FUNNEL_ENSx_MASK)) - coresight_disclaim_device_unlocked(drvdata->base); + coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); } diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c index 205756fab729..a73fea9185b6 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -45,12 +45,14 @@ struct replicator_drvdata { static void dynamic_replicator_reset(struct replicator_drvdata *drvdata) { + struct coresight_device *csdev = drvdata->csdev; + CS_UNLOCK(drvdata->base); - if (!coresight_claim_device_unlocked(drvdata->base)) { + if (!coresight_claim_device_unlocked(csdev)) { writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); - coresight_disclaim_device_unlocked(drvdata->base); + coresight_disclaim_device_unlocked(csdev); } CS_LOCK(drvdata->base); @@ -70,6 +72,7 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, { int rc = 0; u32 id0val, id1val; + struct coresight_device *csdev = drvdata->csdev; CS_UNLOCK(drvdata->base); @@ -84,7 +87,7 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata, id0val = id1val = 0xff; if (id0val == 0xff && id1val == 0xff) - rc = coresight_claim_device_unlocked(drvdata->base); + rc = coresight_claim_device_unlocked(csdev); if (!rc) { switch (outport) { @@ -140,6 +143,7 @@ static void dynamic_replicator_disable(struct replicator_drvdata *drvdata, int inport, int outport) { u32 reg; + struct coresight_device *csdev = drvdata->csdev; switch (outport) { case 0: @@ -160,7 +164,7 @@ static void dynamic_replicator_disable(struct replicator_drvdata *drvdata, if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0xff) && (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0xff)) - coresight_disclaim_device_unlocked(drvdata->base); + coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); } diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 989d965f3d90..45b85edfc690 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -37,7 +37,7 @@ static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) { - int rc = coresight_claim_device(drvdata->base); + int rc = coresight_claim_device(drvdata->csdev); if (rc) return rc; @@ -88,7 +88,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) { __tmc_etb_disable_hw(drvdata); - coresight_disclaim_device(drvdata->base); + coresight_disclaim_device(drvdata->csdev); } static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) @@ -109,7 +109,7 @@ static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) { - int rc = coresight_claim_device(drvdata->base); + int rc = coresight_claim_device(drvdata->csdev); if (rc) return rc; @@ -120,11 +120,13 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) { + struct coresight_device *csdev = drvdata->csdev; + CS_UNLOCK(drvdata->base); tmc_flush_and_stop(drvdata); tmc_disable_hw(drvdata); - coresight_disclaim_device_unlocked(drvdata->base); + coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); } diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index bf5230e39c5b..acdb59e0e661 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1040,7 +1040,7 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, rc = tmc_etr_enable_catu(drvdata, etr_buf); if (rc) return rc; - rc = coresight_claim_device(drvdata->base); + rc = coresight_claim_device(drvdata->csdev); if (!rc) { drvdata->etr_buf = etr_buf; __tmc_etr_enable_hw(drvdata); @@ -1134,7 +1134,7 @@ void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) __tmc_etr_disable_hw(drvdata); /* Disable CATU device if this ETR is connected to one */ tmc_etr_disable_catu(drvdata); - coresight_disclaim_device(drvdata->base); + coresight_disclaim_device(drvdata->csdev); /* Reset the ETR buf used by hardware */ drvdata->etr_buf = NULL; } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 18bc7f9fb041..976ec2697610 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -463,11 +463,11 @@ extern void coresight_disable(struct coresight_device *csdev); extern int coresight_timeout(struct csdev_access *csa, u32 offset, int position, int value); -extern int coresight_claim_device(void __iomem *base); -extern int coresight_claim_device_unlocked(void __iomem *base); +extern int coresight_claim_device(struct coresight_device *csdev); +extern int coresight_claim_device_unlocked(struct coresight_device *csdev); -extern void coresight_disclaim_device(void __iomem *base); -extern void coresight_disclaim_device_unlocked(void __iomem *base); +extern void coresight_disclaim_device(struct coresight_device *csdev); +extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, struct device *dev); @@ -498,18 +498,18 @@ static inline int coresight_timeout(struct csdev_access *csa, u32 offset, return 1; } -static inline int coresight_claim_device_unlocked(void __iomem *base) +static inline int coresight_claim_device_unlocked(struct coresight_device *csdev) { return -EINVAL; } -static inline int coresight_claim_device(void __iomem *base) +static inline int coresight_claim_device(struct coresight_device *csdev) { return -EINVAL; } -static inline void coresight_disclaim_device(void __iomem *base) {} -static inline void coresight_disclaim_device_unlocked(void __iomem *base) {} +static inline void coresight_disclaim_device(struct coresight_device *csdev) {} +static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {} static inline bool coresight_loses_context_with_cpu(struct device *dev) { From patchwork Mon Feb 1 18:13:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E830C433E0 for ; Mon, 1 Feb 2021 18:16:39 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1EE5F6024A for ; Mon, 1 Feb 2021 18:16:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1EE5F6024A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=tHrKFt0DQiSsroMRIdKpjX/gPc5R+14FgTjuXEmO3GQ=; b=Igb+VUtI1jJG4EvqLDXTHTu82 a4Q0qArMKul/BFpEgdTi30zOTBK1llwEaC/Z5nK0/sYWiBjnRq1mVNgDz2y16Rt/VrMgOrj2o8goL hsdYWO/SmgsR958CCYBkkfI5JDPPh0Nukt4iQrLBbrhJ3rPJxESPc/B02J/2SBbIgTn4DkwYLndQ/ IP6EiFWpk5pibrhb+HWbBaLx9YR+dYzjeKxM5oSy+bUEejhnVz7GCnAWDkRC1DcCAIggaA2OqF8Fp Fmhz7MRTahL0s8cvD4+ytCmPAFDE7Uo1om8ePjI8c55oShLZDBLm9WZMSXs1aXMewr7Zvz3XdopVF BWg/W0Iag==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diu-0003MB-QK; Mon, 01 Feb 2021 18:14:52 +0000 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6di9-0002zM-4q for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:11 +0000 Received: by mail-pf1-x435.google.com with SMTP id e19so12129621pfh.6 for ; Mon, 01 Feb 2021 10:14:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CnVnyNqTZ1zzjJCrFT2+4AV5x1r9Ds8A+SATYgEzXLw=; b=jF+yWrdkivTBGi6/W8tX5H5x01E5l6AITQlQa9mM67G3Tjm1rvHZ9jM2Q5NEr56lPi VmpfIGEYyBVhZq7CMGyl3GRXu7mAe09JFS19wgeNWcCghYo0i2RzIwPb0pyNPsuMEZPy 8FAXn/E+LLDYrvB9RZlDpAbwHuiPad1sBxeVLs9k8PhbnRl6gRcQoJIfuxJkLt2Pv1VH 3Fhm2eRAaXpOVYsK/qPyWXslIrjRpZRNFHGAtkndSgNeEup3fT+nr33vBImzVJiK6mnj 10ETO4J5pCEPqnA1rQPhmOk4kh0fEa8D9hYvO0v31nmORsbWlMwrzm4JiEnYKM5BKNZh fXYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CnVnyNqTZ1zzjJCrFT2+4AV5x1r9Ds8A+SATYgEzXLw=; b=iyWaLCTeyaGASF4JcAjPk9mOxB6hkit8SX7cjjKCte1bHmw13DRUWKH+0OTmePHz8r SNT9rcYzvx2FZRfRHgM0hGXAC/+P8p1KULAsVDcBzUuZwkDF/LOgG83+MD6W+8Ttx80S Nzo3AsnhmVD4ewibwk3ux2t/iVg1rA/hhCJJOqhXbSosP0N9YvPctMMJMwg3b9nkLvEK cytN02MIgxJeyQCYz4Jm3PQXyVJH8nD7zu0fmHDNah5nKduw2Z7+snChkBfupCqdfIf8 ThqfRImbnKVt3fj/wcRwJESO4H+7/AuJTPG1gufwX8mqxrnBKSOMXGW/TcHVCzofGzKL EA+w== X-Gm-Message-State: AOAM531BhYSPBJJ2qEGFl2xKHok1SZ7Mtx6zkOviSwyizfOYRO4zcGgl 0Muh4zajcT6fMahO2PKC5kI3rw== X-Google-Smtp-Source: ABdhPJxWANO/umUDUgrviRdL+IMi52eSuWeOHTFEOlYeZYuFSQc4Dzl6GknsGI4twhiiunAirey4iQ== X-Received: by 2002:a65:418b:: with SMTP id a11mr18278641pgq.231.1612203242770; Mon, 01 Feb 2021 10:14:02 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:02 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 09/31] coresight: etm4x: Always read the registers on the host CPU Date: Mon, 1 Feb 2021 11:13:29 -0700 Message-Id: <20210201181351.1475223-10-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131405_295851_5F5A5EB6 X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose As we are about to add support for sysreg access to ETM4.4+ components, make sure that we read the registers only on the host CPU. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-8-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-sysfs.c | 23 ++++++++----------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 989ce7b8ade7..c4781d4e5886 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2344,23 +2344,20 @@ static u32 etmv4_cross_read(const struct device *dev, u32 offset) return reg.data; } -#define coresight_etm4x_reg(name, offset) \ - coresight_simple_reg32(struct etmv4_drvdata, name, offset) - #define coresight_etm4x_cross_read(name, offset) \ coresight_simple_func(struct etmv4_drvdata, etmv4_cross_read, \ name, offset) -coresight_etm4x_reg(trcpdcr, TRCPDCR); -coresight_etm4x_reg(trcpdsr, TRCPDSR); -coresight_etm4x_reg(trclsr, TRCLSR); -coresight_etm4x_reg(trcauthstatus, TRCAUTHSTATUS); -coresight_etm4x_reg(trcdevid, TRCDEVID); -coresight_etm4x_reg(trcdevtype, TRCDEVTYPE); -coresight_etm4x_reg(trcpidr0, TRCPIDR0); -coresight_etm4x_reg(trcpidr1, TRCPIDR1); -coresight_etm4x_reg(trcpidr2, TRCPIDR2); -coresight_etm4x_reg(trcpidr3, TRCPIDR3); +coresight_etm4x_cross_read(trcpdcr, TRCPDCR); +coresight_etm4x_cross_read(trcpdsr, TRCPDSR); +coresight_etm4x_cross_read(trclsr, TRCLSR); +coresight_etm4x_cross_read(trcauthstatus, TRCAUTHSTATUS); +coresight_etm4x_cross_read(trcdevid, TRCDEVID); +coresight_etm4x_cross_read(trcdevtype, TRCDEVTYPE); +coresight_etm4x_cross_read(trcpidr0, TRCPIDR0); +coresight_etm4x_cross_read(trcpidr1, TRCPIDR1); +coresight_etm4x_cross_read(trcpidr2, TRCPIDR2); +coresight_etm4x_cross_read(trcpidr3, TRCPIDR3); coresight_etm4x_cross_read(trcoslsr, TRCOSLSR); coresight_etm4x_cross_read(trcconfig, TRCCONFIGR); coresight_etm4x_cross_read(trctraceid, TRCTRACEIDR); From patchwork Mon Feb 1 18:13:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A67A3C433DB for ; Mon, 1 Feb 2021 18:17:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 10FAD64EA1 for ; Mon, 1 Feb 2021 18:17:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 10FAD64EA1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bPLzi+/saAedDB86Mr0s9XHsF7A/x0ItKSYJvwFS8kw=; b=nKbMibk/hScRNV9czBX5xA5C1 mJPghYD7yvIdyi+ar5aAQ8o9u+m41u2Q+ZXaAuDW9SK8NyaPAaZQ9nq968auRMy1WxTmDzvRoROuc zHUSUEJ6y8MeJvuOC++Xp0O50P8Fiu4bCTuV0BNJ92Ofor/S3Yu5fTcXmc3oWFnS3vthFgJIQxqgD NDJjIP6wYE6USlIMrVF3g1IL0NVjU5y9javyZi9g6l8UD9kuYCaWxdaDGa9cpdl9mt/qoy62BlMCk VsZdRTvgZR9+goXsu/BNCBU2nkfptasmoO1wNcSgoE1DAzSwe2C4aGCNDCFcsA03cZ8snRFQe1tmD gcud1SpsQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6djj-0003nv-Bu; Mon, 01 Feb 2021 18:15:43 +0000 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diB-000309-5e for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:24 +0000 Received: by mail-pj1-x102f.google.com with SMTP id gx20so88492pjb.1 for ; Mon, 01 Feb 2021 10:14:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vCKQXmZNPjxwsyrToEHwpPphFJk+ig89MwClwtthRb4=; b=YLbhjycPXJZwH37/d8nje0wsvqsmgW4b94mkbRyQwceCOCl5Hs5osdUq6Da8e1rLKS jPX4Lqab3T44Z+Mw2SwjEohnd1feHpZzNeUE2Ny+JNmW//QGXtKSoM4BHomBVVF4Hkna GxL5eMS4aJK6tck9Z2lHT74RBcA4IQHu0sOZ78UuXQ8yGVvs3BnBJYuCzlGzcV/Xwf52 Woh5tN2Zx0/J7Zy2CJaAy8IvktvWgXnlFW1YdaGsWShIuvGdfrbcx4avjF7XvDkBrfYT SIkk6gV/8XNvOrP/e8+kxhOKvRknGXqdGl8GbDURPWZmhiwY210Oz41EmrK5epsIOpiF /IsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vCKQXmZNPjxwsyrToEHwpPphFJk+ig89MwClwtthRb4=; b=GrhEO+vG3d5/CivzHM97fulHUUbSeAK6t/W0+Ou/FTGcjSPF7hNbnT++mymdaGqzhL F/vY5/BkOYxMZcMXTBARAmYlWl93xvAevX+QVLiyeJMzOM/9cUlKH8AraqNLkqVnLSGT jJgWMFeloZEkm9YQZz/nodItoN4JT6JHfjP5RAlScvDEjOVo2qfvFIRZ39zg/SM5qIfx 56NEAGSkyN7XWhuwU01jtszsLxqj3Q8yYgv9M8/dLOTNP5QzV16TGiId/m0kYfiLbYxD /gZpNmw/IpTI0/9rxoRcClafTYy76aIcHkNfQE52cq6rmT2QdeM0hhWkaz2SDDq8kSF3 nuUA== X-Gm-Message-State: AOAM531EoZZ3u0t2KFVYJH7GeUyf6Kw65+R26pUIj36F4UEMCZKvoipt W1Tega0mguuvMxAIHUnfSaiDhA== X-Google-Smtp-Source: ABdhPJzsbiJGVCNCpIzhga43SqPxMw8Ov2FbbIHN3bvQGYJ8p5faph1Uwa2321kVqnk07X/ttyzomw== X-Received: by 2002:a17:902:c114:b029:e1:5c6f:4a26 with SMTP id 20-20020a170902c114b02900e15c6f4a26mr6253188pli.85.1612203244476; Mon, 01 Feb 2021 10:14:04 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:03 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 10/31] coresight: etm4x: Convert all register accesses Date: Mon, 1 Feb 2021 11:13:30 -0700 Message-Id: <20210201181351.1475223-11-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131407_425965_B082E02E X-CRM114-Status: GOOD ( 20.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose Convert all register accesses from etm4x driver to use a wrapper to allow switching the access at runtime with little overhead. co-developed by sed tool ;-), mostly equivalent to : s/readl\(_relaxed\)\?(drvdata->base + \(.*\))/etm4x_\1_read32(csdev, \2) s/writel\(_relaxed\)\?(\(.*\), drvdata->base + \(.*\))/etm4x_\1_write32(csdev, \2, \3) We don't want to replace them with the csdev_access_* to avoid a function call for every register access for system register access. This is a prepartory step to add system register access later where the support is available. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-9-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 327 +++++++++--------- .../coresight/coresight-etm4x-sysfs.c | 9 +- drivers/hwtracing/coresight/coresight-etm4x.h | 24 ++ 3 files changed, 188 insertions(+), 172 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index a041ad52737f..9331281b931f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -75,18 +75,28 @@ static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) (drvdata->config.ss_status[n] & TRCSSCSRn_PC); } -static void etm4_os_unlock(struct etmv4_drvdata *drvdata) +static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { /* Writing 0 to TRCOSLAR unlocks the trace registers */ - writel_relaxed(0x0, drvdata->base + TRCOSLAR); + etm4x_relaxed_write32(csa, 0x0, TRCOSLAR); drvdata->os_unlock = true; isb(); } +static void etm4_os_unlock(struct etmv4_drvdata *drvdata) +{ + if (!WARN_ON(!drvdata->csdev)) + etm4_os_unlock_csa(drvdata, &drvdata->csdev->access); + +} + static void etm4_os_lock(struct etmv4_drvdata *drvdata) { + if (WARN_ON(!drvdata->csdev)) + return; + /* Writing 0x1 to TRCOSLAR locks the trace registers */ - writel_relaxed(0x1, drvdata->base + TRCOSLAR); + etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR); drvdata->os_unlock = false; isb(); } @@ -231,45 +241,39 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) goto done; /* Disable the trace unit before programming trace registers */ - writel_relaxed(0, drvdata->base + TRCPRGCTLR); + etm4x_relaxed_write32(csa, 0, TRCPRGCTLR); /* wait for TRCSTATR.IDLE to go up */ if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); if (drvdata->nr_pe) - writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR); - writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR); + etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR); + etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR); /* nothing specific implemented */ - writel_relaxed(0x0, drvdata->base + TRCAUXCTLR); - writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R); - writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R); - writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR); - writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR); - writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR); - writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR); - writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR); - writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR); - writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR); - writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR); - writel_relaxed(config->vissctlr, - drvdata->base + TRCVISSCTLR); + etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR); + etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); + etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R); + etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); + etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR); + etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR); + etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR); + etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR); + etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR); + etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); + etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR); + etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); if (drvdata->nr_pe_cmp) - writel_relaxed(config->vipcssctlr, - drvdata->base + TRCVIPCSSCTLR); + etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); for (i = 0; i < drvdata->nrseqstate - 1; i++) - writel_relaxed(config->seq_ctrl[i], - drvdata->base + TRCSEQEVRn(i)); - writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR); - writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR); - writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR); + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { - writel_relaxed(config->cntrldvr[i], - drvdata->base + TRCCNTRLDVRn(i)); - writel_relaxed(config->cntr_ctrl[i], - drvdata->base + TRCCNTCTLRn(i)); - writel_relaxed(config->cntr_val[i], - drvdata->base + TRCCNTVRn(i)); + etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); + etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); + etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i)); } /* @@ -277,52 +281,45 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) * such start at 2. */ for (i = 2; i < drvdata->nr_resource * 2; i++) - writel_relaxed(config->res_ctrl[i], - drvdata->base + TRCRSCTLRn(i)); + etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); for (i = 0; i < drvdata->nr_ss_cmp; i++) { /* always clear status bit on restart if using single-shot */ if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) config->ss_status[i] &= ~BIT(31); - writel_relaxed(config->ss_ctrl[i], - drvdata->base + TRCSSCCRn(i)); - writel_relaxed(config->ss_status[i], - drvdata->base + TRCSSCSRn(i)); + etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); + etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) - writel_relaxed(config->ss_pe_cmp[i], - drvdata->base + TRCSSPCICRn(i)); + etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); } for (i = 0; i < drvdata->nr_addr_cmp; i++) { - writeq_relaxed(config->addr_val[i], - drvdata->base + TRCACVRn(i)); - writeq_relaxed(config->addr_acc[i], - drvdata->base + TRCACATRn(i)); + etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); + etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); } for (i = 0; i < drvdata->numcidc; i++) - writeq_relaxed(config->ctxid_pid[i], - drvdata->base + TRCCIDCVRn(i)); - writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0); + etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); + etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); if (drvdata->numcidc > 4) - writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1); + etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1); for (i = 0; i < drvdata->numvmidc; i++) - writeq_relaxed(config->vmid_val[i], - drvdata->base + TRCVMIDCVRn(i)); - writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); + etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); + etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); if (drvdata->numvmidc > 4) - writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); + etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1); if (!drvdata->skip_power_up) { + u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR); + /* * Request to keep the trace unit powered and also * emulation of powerdown */ - writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | - TRCPDCR_PU, drvdata->base + TRCPDCR); + etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR); } /* Enable the trace unit */ - writel_relaxed(1, drvdata->base + TRCPRGCTLR); + etm4x_relaxed_write32(csa, 1, TRCPRGCTLR); /* wait for TRCSTATR.IDLE to go back down to '0' */ if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) @@ -599,12 +596,12 @@ static void etm4_disable_hw(void *info) if (!drvdata->skip_power_up) { /* power can be removed from the trace unit now */ - control = readl_relaxed(drvdata->base + TRCPDCR); + control = etm4x_relaxed_read32(csa, TRCPDCR); control &= ~TRCPDCR_PU; - writel_relaxed(control, drvdata->base + TRCPDCR); + etm4x_relaxed_write32(csa, control, TRCPDCR); } - control = readl_relaxed(drvdata->base + TRCPRGCTLR); + control = etm4x_relaxed_read32(csa, TRCPRGCTLR); /* EN, bit[0] Trace unit enable bit */ control &= ~0x1; @@ -616,7 +613,7 @@ static void etm4_disable_hw(void *info) */ dsb(sy); isb(); - writel_relaxed(control, drvdata->base + TRCPRGCTLR); + etm4x_relaxed_write32(csa, control, TRCPRGCTLR); /* wait for TRCSTATR.PMSTABLE to go to '1' */ if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) @@ -626,13 +623,13 @@ static void etm4_disable_hw(void *info) /* read the status of the single shot comparators */ for (i = 0; i < drvdata->nr_ss_cmp; i++) { config->ss_status[i] = - readl_relaxed(drvdata->base + TRCSSCSRn(i)); + etm4x_relaxed_read32(csa, TRCSSCSRn(i)); } /* read back the current counter values */ for (i = 0; i < drvdata->nr_cntr; i++) { config->cntr_val[i] = - readl_relaxed(drvdata->base + TRCCNTVRn(i)); + etm4x_relaxed_read32(csa, TRCCNTVRn(i)); } coresight_disclaim_device_unlocked(csdev); @@ -661,7 +658,7 @@ static int etm4_disable_perf(struct coresight_device *csdev, * scheduled again. Configuration of the start/stop logic happens in * function etm4_set_event_filters(). */ - control = readl_relaxed(drvdata->base + TRCVICTLR); + control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR); /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus = (control & BIT(9)); @@ -741,15 +738,17 @@ static void etm4_init_arch_data(void *info) u32 etmidr4; u32 etmidr5; struct etmv4_drvdata *drvdata = info; + struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); + struct csdev_access *csa = &tmp_csa; int i; /* Make sure all registers are accessible */ - etm4_os_unlock(drvdata); + etm4_os_unlock_csa(drvdata, csa); CS_UNLOCK(drvdata->base); /* find all capabilities of the tracing unit */ - etmidr0 = readl_relaxed(drvdata->base + TRCIDR0); + etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); /* INSTP0, bits[2:1] P0 tracing support field */ if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) @@ -789,7 +788,7 @@ static void etm4_init_arch_data(void *info) drvdata->ts_size = BMVAL(etmidr0, 24, 28); /* base architecture of trace unit */ - etmidr1 = readl_relaxed(drvdata->base + TRCIDR1); + etmidr1 = etm4x_relaxed_read32(csa, TRCIDR1); /* * TRCARCHMIN, bits[7:4] architecture the minor version number * TRCARCHMAJ, bits[11:8] architecture major versin number @@ -798,7 +797,7 @@ static void etm4_init_arch_data(void *info) drvdata->config.arch = drvdata->arch; /* maximum size of resources */ - etmidr2 = readl_relaxed(drvdata->base + TRCIDR2); + etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); /* CIDSIZE, bits[9:5] Indicates the Context ID size */ drvdata->ctxid_size = BMVAL(etmidr2, 5, 9); /* VMIDSIZE, bits[14:10] Indicates the VMID size */ @@ -806,7 +805,7 @@ static void etm4_init_arch_data(void *info) /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ drvdata->ccsize = BMVAL(etmidr2, 25, 28); - etmidr3 = readl_relaxed(drvdata->base + TRCIDR3); + etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ drvdata->ccitmin = BMVAL(etmidr3, 0, 11); /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ @@ -856,7 +855,7 @@ static void etm4_init_arch_data(void *info) drvdata->nooverflow = false; /* number of resources trace unit supports */ - etmidr4 = readl_relaxed(drvdata->base + TRCIDR4); + etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4); /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3); /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ @@ -882,14 +881,14 @@ static void etm4_init_arch_data(void *info) drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23); for (i = 0; i < drvdata->nr_ss_cmp; i++) { drvdata->config.ss_status[i] = - readl_relaxed(drvdata->base + TRCSSCSRn(i)); + etm4x_relaxed_read32(csa, TRCSSCSRn(i)); } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ drvdata->numcidc = BMVAL(etmidr4, 24, 27); /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ drvdata->numvmidc = BMVAL(etmidr4, 28, 31); - etmidr5 = readl_relaxed(drvdata->base + TRCIDR5); + etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); /* NUMEXTIN, bits[8:0] number of external inputs implemented */ drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8); /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ @@ -1308,56 +1307,56 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) state = drvdata->save_state; - state->trcprgctlr = readl(drvdata->base + TRCPRGCTLR); + state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR); if (drvdata->nr_pe) - state->trcprocselr = readl(drvdata->base + TRCPROCSELR); - state->trcconfigr = readl(drvdata->base + TRCCONFIGR); - state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR); - state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R); - state->trceventctl1r = readl(drvdata->base + TRCEVENTCTL1R); - state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR); - state->trctsctlr = readl(drvdata->base + TRCTSCTLR); - state->trcsyncpr = readl(drvdata->base + TRCSYNCPR); - state->trcccctlr = readl(drvdata->base + TRCCCCTLR); - state->trcbbctlr = readl(drvdata->base + TRCBBCTLR); - state->trctraceidr = readl(drvdata->base + TRCTRACEIDR); - state->trcqctlr = readl(drvdata->base + TRCQCTLR); - - state->trcvictlr = readl(drvdata->base + TRCVICTLR); - state->trcviiectlr = readl(drvdata->base + TRCVIIECTLR); - state->trcvissctlr = readl(drvdata->base + TRCVISSCTLR); + state->trcprocselr = etm4x_read32(csa, TRCPROCSELR); + state->trcconfigr = etm4x_read32(csa, TRCCONFIGR); + state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR); + state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); + state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R); + state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR); + state->trctsctlr = etm4x_read32(csa, TRCTSCTLR); + state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR); + state->trcccctlr = etm4x_read32(csa, TRCCCCTLR); + state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR); + state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR); + state->trcqctlr = etm4x_read32(csa, TRCQCTLR); + + state->trcvictlr = etm4x_read32(csa, TRCVICTLR); + state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR); + state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR); if (drvdata->nr_pe_cmp) - state->trcvipcssctlr = readl(drvdata->base + TRCVIPCSSCTLR); - state->trcvdctlr = readl(drvdata->base + TRCVDCTLR); - state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR); - state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR); + state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); + state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR); + state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR); + state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR); for (i = 0; i < drvdata->nrseqstate - 1; i++) - state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i)); + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); - state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR); - state->trcseqstr = readl(drvdata->base + TRCSEQSTR); - state->trcextinselr = readl(drvdata->base + TRCEXTINSELR); + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { - state->trccntrldvr[i] = readl(drvdata->base + TRCCNTRLDVRn(i)); - state->trccntctlr[i] = readl(drvdata->base + TRCCNTCTLRn(i)); - state->trccntvr[i] = readl(drvdata->base + TRCCNTVRn(i)); + state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); + state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i)); + state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i)); } for (i = 0; i < drvdata->nr_resource * 2; i++) - state->trcrsctlr[i] = readl(drvdata->base + TRCRSCTLRn(i)); + state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i)); for (i = 0; i < drvdata->nr_ss_cmp; i++) { - state->trcssccr[i] = readl(drvdata->base + TRCSSCCRn(i)); - state->trcsscsr[i] = readl(drvdata->base + TRCSSCSRn(i)); + state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i)); + state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) - state->trcsspcicr[i] = readl(drvdata->base + TRCSSPCICRn(i)); + state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i)); } for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { - state->trcacvr[i] = readq(drvdata->base + TRCACVRn(i)); - state->trcacatr[i] = readq(drvdata->base + TRCACATRn(i)); + state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); + state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); } /* @@ -1368,23 +1367,23 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) */ for (i = 0; i < drvdata->numcidc; i++) - state->trccidcvr[i] = readq(drvdata->base + TRCCIDCVRn(i)); + state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); for (i = 0; i < drvdata->numvmidc; i++) - state->trcvmidcvr[i] = readq(drvdata->base + TRCVMIDCVRn(i)); + state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); - state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0); + state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0); if (drvdata->numcidc > 4) - state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1); + state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1); - state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0); + state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0); if (drvdata->numvmidc > 4) - state->trcvmidcctlr1 = readl(drvdata->base + TRCVMIDCCTLR1); + state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1); - state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR); + state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR); if (!drvdata->skip_power_up) - state->trcpdcr = readl(drvdata->base + TRCPDCR); + state->trcpdcr = etm4x_read32(csa, TRCPDCR); /* wait for TRCSTATR.IDLE to go up */ if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { @@ -1403,8 +1402,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) * despite requesting software to save/restore state. */ if (!drvdata->skip_power_up) - writel_relaxed((state->trcpdcr & ~TRCPDCR_PU), - drvdata->base + TRCPDCR); + etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), + TRCPDCR); out: CS_LOCK(drvdata->base); return ret; @@ -1414,93 +1413,83 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) { int i; struct etmv4_save_state *state = drvdata->save_state; + struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); + struct csdev_access *csa = &tmp_csa; CS_UNLOCK(drvdata->base); - writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET); + etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); - writel_relaxed(state->trcprgctlr, drvdata->base + TRCPRGCTLR); + etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); if (drvdata->nr_pe) - writel_relaxed(state->trcprocselr, drvdata->base + TRCPROCSELR); - writel_relaxed(state->trcconfigr, drvdata->base + TRCCONFIGR); - writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR); - writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R); - writel_relaxed(state->trceventctl1r, drvdata->base + TRCEVENTCTL1R); - writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR); - writel_relaxed(state->trctsctlr, drvdata->base + TRCTSCTLR); - writel_relaxed(state->trcsyncpr, drvdata->base + TRCSYNCPR); - writel_relaxed(state->trcccctlr, drvdata->base + TRCCCCTLR); - writel_relaxed(state->trcbbctlr, drvdata->base + TRCBBCTLR); - writel_relaxed(state->trctraceidr, drvdata->base + TRCTRACEIDR); - writel_relaxed(state->trcqctlr, drvdata->base + TRCQCTLR); - - writel_relaxed(state->trcvictlr, drvdata->base + TRCVICTLR); - writel_relaxed(state->trcviiectlr, drvdata->base + TRCVIIECTLR); - writel_relaxed(state->trcvissctlr, drvdata->base + TRCVISSCTLR); + etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR); + etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR); + etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR); + etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); + etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R); + etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); + etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR); + etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR); + etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); + etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR); + etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR); + etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR); + + etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); + etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR); + etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR); if (drvdata->nr_pe_cmp) - writel_relaxed(state->trcvipcssctlr, drvdata->base + TRCVIPCSSCTLR); - writel_relaxed(state->trcvdctlr, drvdata->base + TRCVDCTLR); - writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR); - writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR); + etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); + etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR); + etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR); + etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR); for (i = 0; i < drvdata->nrseqstate - 1; i++) - writel_relaxed(state->trcseqevr[i], - drvdata->base + TRCSEQEVRn(i)); + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); - writel_relaxed(state->trcseqrstevr, drvdata->base + TRCSEQRSTEVR); - writel_relaxed(state->trcseqstr, drvdata->base + TRCSEQSTR); - writel_relaxed(state->trcextinselr, drvdata->base + TRCEXTINSELR); + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { - writel_relaxed(state->trccntrldvr[i], - drvdata->base + TRCCNTRLDVRn(i)); - writel_relaxed(state->trccntctlr[i], - drvdata->base + TRCCNTCTLRn(i)); - writel_relaxed(state->trccntvr[i], - drvdata->base + TRCCNTVRn(i)); + etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); + etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i)); + etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i)); } for (i = 0; i < drvdata->nr_resource * 2; i++) - writel_relaxed(state->trcrsctlr[i], - drvdata->base + TRCRSCTLRn(i)); + etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i)); for (i = 0; i < drvdata->nr_ss_cmp; i++) { - writel_relaxed(state->trcssccr[i], - drvdata->base + TRCSSCCRn(i)); - writel_relaxed(state->trcsscsr[i], - drvdata->base + TRCSSCSRn(i)); + etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); + etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) - writel_relaxed(state->trcsspcicr[i], - drvdata->base + TRCSSPCICRn(i)); + etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); } for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { - writeq_relaxed(state->trcacvr[i], - drvdata->base + TRCACVRn(i)); - writeq_relaxed(state->trcacatr[i], - drvdata->base + TRCACATRn(i)); + etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); + etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); } for (i = 0; i < drvdata->numcidc; i++) - writeq_relaxed(state->trccidcvr[i], - drvdata->base + TRCCIDCVRn(i)); + etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); for (i = 0; i < drvdata->numvmidc; i++) - writeq_relaxed(state->trcvmidcvr[i], - drvdata->base + TRCVMIDCVRn(i)); + etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); - writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0); + etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); if (drvdata->numcidc > 4) - writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1); + etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1); - writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0); + etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0); if (drvdata->numvmidc > 4) - writel_relaxed(state->trcvmidcctlr1, drvdata->base + TRCVMIDCCTLR1); + etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1); - writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET); + etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); if (!drvdata->skip_power_up) - writel_relaxed(state->trcpdcr, drvdata->base + TRCPDCR); + etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR); drvdata->state_needs_restore = false; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index c4781d4e5886..fce9df16bfb5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2319,7 +2319,8 @@ static struct attribute *coresight_etmv4_attrs[] = { }; struct etmv4_reg { - void __iomem *addr; + struct coresight_device *csdev; + u32 offset; u32 data; }; @@ -2327,7 +2328,7 @@ static void do_smp_cross_read(void *data) { struct etmv4_reg *reg = data; - reg->data = readl_relaxed(reg->addr); + reg->data = etm4x_relaxed_read32(®->csdev->access, reg->offset); } static u32 etmv4_cross_read(const struct device *dev, u32 offset) @@ -2335,7 +2336,9 @@ static u32 etmv4_cross_read(const struct device *dev, u32 offset) struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); struct etmv4_reg reg; - reg.addr = drvdata->base + offset; + reg.offset = offset; + reg.csdev = drvdata->csdev; + /* * smp cross call ensures the CPU will be powered up before * accessing the ETMv4 trace core registers diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 80e480c7fe5c..b6854f6fd666 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -121,6 +121,30 @@ #define TRCCIDR2 0xFF8 #define TRCCIDR3 0xFFC +#define etm4x_relaxed_read32(csa, offset) \ + readl_relaxed((csa)->base + (offset)) + +#define etm4x_read32(csa, offset) \ + readl((csa)->base + (offset)) + +#define etm4x_relaxed_write32(csa, val, offset) \ + writel_relaxed((val), (csa)->base + (offset)) + +#define etm4x_write32(csa, val, offset) \ + writel((val), (csa)->base + (offset)) + +#define etm4x_relaxed_read64(csa, offset) \ + readq_relaxed((csa)->base + (offset)) + +#define etm4x_read64(csa, offset) \ + readq((csa)->base + (offset)) + +#define etm4x_relaxed_write64(csa, val, offset) \ + writeq_relaxed((val), (csa)->base + (offset)) + +#define etm4x_write64(csa, val, offset) \ + writeq((val), (csa)->base + (offset)) + /* ETMv4 resources */ #define ETM_MAX_NR_PE 8 #define ETMv4_MAX_CNTR 4 From patchwork Mon Feb 1 18:13:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B24AC433DB for ; Mon, 1 Feb 2021 18:17:11 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 946C064E50 for ; Mon, 1 Feb 2021 18:17:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 946C064E50 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=HBzTKFwUU/umDeAWYtlOgRkxytwBuP9IxPibihreycY=; b=raLeJCnSxpFAxw9JltBI8T3eD KUrwXrxk8EDfKJeUwKs7OB2EEn3q7YCTQ4ywS0YQLi4bTR5ke47qGHI5hRZVa4syy/goigwk0AP8G CVbtiJhrEc1EUXu6ZQk5+Ymrj1LPkoIZF1s3PQCLi6HL6b1pFksM6xwRbcwtZNfQLFvXHysvrHhJN L1J/Puby6Jn5pn0EpQrZVowT+z63HRKsXQ7QdCNopb1ulWS1K14/GqFUssGE63qhs6WqrHAAZEolp vBvT67rMWmwEAlXLsQZalEN5UsVY3rvI5UrSM4e/jWdG8Rc3wOXMnFWG5hlicWn+eEx25JGT79u25 UrdNuhoFw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6djD-0003W8-RW; Mon, 01 Feb 2021 18:15:11 +0000 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diB-00030a-D3 for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:17 +0000 Received: by mail-pj1-x1035.google.com with SMTP id l18so80821pji.3 for ; Mon, 01 Feb 2021 10:14:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Gd0PQfLiLT7Acbpyo/XJTh4r8nkghnLD/diEbX5F5ZQ=; b=B59LKz+MwWXqeMaL+5RpXeL576dApBmts5cfHft/pgZF3G6rPGK2NqQEieM7CySch5 E99UnO2+6U5BB6sCasWYqSzOM2T+ED6cuA35DgHYnzQ1RRrmj8E3jHuQ9RcmOjZU3xlq qBCvFXHOQHsuSpiIKeJM+UnT3pvuwmaDP2WwFcXRw24ifFNOxIAWZx172yXGAAQ/5cGk YYuM4Yo0DUqsritpjuj4LpT6hHzNrKYNQmMBn5SLoY7bP3E/EdnaWPupQYtyuvbykxm2 lRq9qXOu38qsSFcKm5FNqxNXqlbOinuMGMN0T2hrI5lFWCHtcG72nWw0P6qoWf8MO03j rUtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gd0PQfLiLT7Acbpyo/XJTh4r8nkghnLD/diEbX5F5ZQ=; b=bqPDGGxy+lkcCFzSx4oz1edLuSCevnoRyO1RVEQS/Ws9fzOCly67Sv7U41SbYGYsyF k/LlrThA43Q0155th6Kv8zSvOeyvLdHCnIYgUKwUxT+CoHxxTsjLUV12+ZRHCk9t9iru 5TBOrXpUSY2iP7WP+PV4AYS/Rn/2eNbeeGIqOchW8xnhbITFFsclGa3gw1biZs/RoKRe ZnaNGKb8uPw4qCRprI+f5qjm8ZbwwMiAYoYXs7hwQSWQEPOWHvss//qSrqdZz/TXSI4b 2z172n0XsmoSWvowIYCVH+PsTDRdJVH9AfbPOS6keKbWMh9BpoNpZTFDfEzICaP4RO9f FjnQ== X-Gm-Message-State: AOAM532qpxBG5+2fclt++vulbR2hXMDt+7JF49qAdEp3j8U+/CK7/vlZ mqFtDm36OpK7QaF45AAgfFgEnQ== X-Google-Smtp-Source: ABdhPJwxLQyX2AF7jmnsqAcCgLAnHPeWdsKBKaRupGzJYOyPlnPuxZVvTC/mN5/PlsIcgdWVbG8SHQ== X-Received: by 2002:a17:90b:e8b:: with SMTP id fv11mr127682pjb.5.1612203245395; Mon, 01 Feb 2021 10:14:05 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:04 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 11/31] coresight: etm4x: Make offset available for sysfs attributes Date: Mon, 1 Feb 2021 11:13:31 -0700 Message-Id: <20210201181351.1475223-12-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131407_612886_5F4EE52B X-CRM114-Status: GOOD ( 16.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose Some of the ETM management registers are not accessible via system instructions. Thus we need to filter accesses to these registers depending on the access mechanism for the ETM at runtime. The driver can cope with this for normal operation, by regular checks. But the driver also exposes them via sysfs, which now needs to be removed. So far, we have used the generic coresight sysfs helper macros to export a given device register, defining a "show" operation per register. This is not helpful to filter the files at runtime, based on the access. In order to do this dynamically, we need to filter the attributes by offsets and hard coded "show" functions doesn't make this easy. Thus, switch to extended attributes, storing the offset in the scratch space. This allows us to implement filtering based on the offset and also saves us some text size. This will be later used for determining a given attribute must be "visible" via sysfs. Cc: Mathieu Poirier Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-10-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-sysfs.c | 115 +++++++++--------- 1 file changed, 57 insertions(+), 58 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index fce9df16bfb5..ddbfeb24fc3f 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2331,9 +2331,8 @@ static void do_smp_cross_read(void *data) reg->data = etm4x_relaxed_read32(®->csdev->access, reg->offset); } -static u32 etmv4_cross_read(const struct device *dev, u32 offset) +static u32 etmv4_cross_read(const struct etmv4_drvdata *drvdata, u32 offset) { - struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); struct etmv4_reg reg; reg.offset = offset; @@ -2347,69 +2346,69 @@ static u32 etmv4_cross_read(const struct device *dev, u32 offset) return reg.data; } -#define coresight_etm4x_cross_read(name, offset) \ - coresight_simple_func(struct etmv4_drvdata, etmv4_cross_read, \ - name, offset) - -coresight_etm4x_cross_read(trcpdcr, TRCPDCR); -coresight_etm4x_cross_read(trcpdsr, TRCPDSR); -coresight_etm4x_cross_read(trclsr, TRCLSR); -coresight_etm4x_cross_read(trcauthstatus, TRCAUTHSTATUS); -coresight_etm4x_cross_read(trcdevid, TRCDEVID); -coresight_etm4x_cross_read(trcdevtype, TRCDEVTYPE); -coresight_etm4x_cross_read(trcpidr0, TRCPIDR0); -coresight_etm4x_cross_read(trcpidr1, TRCPIDR1); -coresight_etm4x_cross_read(trcpidr2, TRCPIDR2); -coresight_etm4x_cross_read(trcpidr3, TRCPIDR3); -coresight_etm4x_cross_read(trcoslsr, TRCOSLSR); -coresight_etm4x_cross_read(trcconfig, TRCCONFIGR); -coresight_etm4x_cross_read(trctraceid, TRCTRACEIDR); +static inline u32 coresight_etm4x_attr_to_offset(struct device_attribute *attr) +{ + struct dev_ext_attribute *eattr; + + eattr = container_of(attr, struct dev_ext_attribute, attr); + return (u32)(unsigned long)eattr->var; +} + +static ssize_t coresight_etm4x_reg_show(struct device *dev, + struct device_attribute *d_attr, + char *buf) +{ + u32 val, offset; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + offset = coresight_etm4x_attr_to_offset(d_attr); + + pm_runtime_get_sync(dev->parent); + val = etmv4_cross_read(drvdata, offset); + pm_runtime_put_sync(dev->parent); + + return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); +} + +#define coresight_etm4x_reg(name, offset) \ + &((struct dev_ext_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_etm4x_reg_show, NULL), \ + (void *)(unsigned long)offset \ + } \ + })[0].attr.attr static struct attribute *coresight_etmv4_mgmt_attrs[] = { - &dev_attr_trcoslsr.attr, - &dev_attr_trcpdcr.attr, - &dev_attr_trcpdsr.attr, - &dev_attr_trclsr.attr, - &dev_attr_trcconfig.attr, - &dev_attr_trctraceid.attr, - &dev_attr_trcauthstatus.attr, - &dev_attr_trcdevid.attr, - &dev_attr_trcdevtype.attr, - &dev_attr_trcpidr0.attr, - &dev_attr_trcpidr1.attr, - &dev_attr_trcpidr2.attr, - &dev_attr_trcpidr3.attr, + coresight_etm4x_reg(trcpdcr, TRCPDCR), + coresight_etm4x_reg(trcpdsr, TRCPDSR), + coresight_etm4x_reg(trclsr, TRCLSR), + coresight_etm4x_reg(trcauthstatus, TRCAUTHSTATUS), + coresight_etm4x_reg(trcdevid, TRCDEVID), + coresight_etm4x_reg(trcdevtype, TRCDEVTYPE), + coresight_etm4x_reg(trcpidr0, TRCPIDR0), + coresight_etm4x_reg(trcpidr1, TRCPIDR1), + coresight_etm4x_reg(trcpidr2, TRCPIDR2), + coresight_etm4x_reg(trcpidr3, TRCPIDR3), + coresight_etm4x_reg(trcoslsr, TRCOSLSR), + coresight_etm4x_reg(trcconfig, TRCCONFIGR), + coresight_etm4x_reg(trctraceid, TRCTRACEIDR), NULL, }; -coresight_etm4x_cross_read(trcidr0, TRCIDR0); -coresight_etm4x_cross_read(trcidr1, TRCIDR1); -coresight_etm4x_cross_read(trcidr2, TRCIDR2); -coresight_etm4x_cross_read(trcidr3, TRCIDR3); -coresight_etm4x_cross_read(trcidr4, TRCIDR4); -coresight_etm4x_cross_read(trcidr5, TRCIDR5); -/* trcidr[6,7] are reserved */ -coresight_etm4x_cross_read(trcidr8, TRCIDR8); -coresight_etm4x_cross_read(trcidr9, TRCIDR9); -coresight_etm4x_cross_read(trcidr10, TRCIDR10); -coresight_etm4x_cross_read(trcidr11, TRCIDR11); -coresight_etm4x_cross_read(trcidr12, TRCIDR12); -coresight_etm4x_cross_read(trcidr13, TRCIDR13); - static struct attribute *coresight_etmv4_trcidr_attrs[] = { - &dev_attr_trcidr0.attr, - &dev_attr_trcidr1.attr, - &dev_attr_trcidr2.attr, - &dev_attr_trcidr3.attr, - &dev_attr_trcidr4.attr, - &dev_attr_trcidr5.attr, + coresight_etm4x_reg(trcidr0, TRCIDR0), + coresight_etm4x_reg(trcidr1, TRCIDR1), + coresight_etm4x_reg(trcidr2, TRCIDR2), + coresight_etm4x_reg(trcidr3, TRCIDR3), + coresight_etm4x_reg(trcidr4, TRCIDR4), + coresight_etm4x_reg(trcidr5, TRCIDR5), /* trcidr[6,7] are reserved */ - &dev_attr_trcidr8.attr, - &dev_attr_trcidr9.attr, - &dev_attr_trcidr10.attr, - &dev_attr_trcidr11.attr, - &dev_attr_trcidr12.attr, - &dev_attr_trcidr13.attr, + coresight_etm4x_reg(trcidr8, TRCIDR8), + coresight_etm4x_reg(trcidr9, TRCIDR9), + coresight_etm4x_reg(trcidr10, TRCIDR10), + coresight_etm4x_reg(trcidr11, TRCIDR11), + coresight_etm4x_reg(trcidr12, TRCIDR12), + coresight_etm4x_reg(trcidr13, TRCIDR13), NULL, }; From patchwork Mon Feb 1 18:13:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D772C433DB for ; Mon, 1 Feb 2021 18:17:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3764764DE1 for ; Mon, 1 Feb 2021 18:17:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3764764DE1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=O9ZFHfio8pd2+OXiuNjhZbl/JjmuQ63m07Ura+l+4BM=; b=o5wPg1wf1fH2ozXH5d58YBLxD qkivdwzsuHZyVQJ9dkXEW8Oh7hFyHKftJ9Xm1fWq1aOVN5HzPtiQCPmqLxAIXg6ya2vSYlQsvQFt7 ONtcoc0QIWHodqGTM7WR537z4rdmSvfBNjZOx96181NbZZ7YrR/nqGAbEbEprjCvu0USCnQd1bC3k QSTWx0uQF+jiMFukS7+rK21DTvrKhtFBeVI83lRi4uMqICwa2EAT0ZIcZ+YFlTJ59iV0O/qsjU16u n59kGwDAqU3A/0eP/P/VSX22S+fDkrdEAXKZV21Nifwuf1w6Arrx6GrN8azN83xoXR7oafzXcXnNz tRbAamxAg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6djH-0003YL-Ro; Mon, 01 Feb 2021 18:15:17 +0000 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diC-00031B-P2 for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:17 +0000 Received: by mail-pj1-x102d.google.com with SMTP id m12so75735pjs.4 for ; Mon, 01 Feb 2021 10:14:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4RRBlCah2JVCFYBxRJ0/Km6eRiEmJrEsdil+05pqvOQ=; b=CWkBaGU1a734N6xxQeXe/aHAKk6b+aehd+zcqVO4EDVYd18IvYky+rCH7IWxqH/uPY +MQoE2QMdy4aWuKUSp0Bq4ZhXdvpj97fGIOw+RYCey3r23Ye3K+O0MblUjaocZA+zi1m nGhpqEt4RFq9eKHfK1DcLmGbexPH6HcRwuTuvW+IUCRVAOe+mrNCcogYIXAvIpKlQN/m t0DAIZRZyul/JjCFROTsQcvVAR63fCttHosuC7L+egNYSiRCiATgiv3yW5/AvMM8A51E uIz5WP46VKzE2k6pPi1QL8a0noh5LXTp1VRw33Dxw8Zt7Iqja4TM7foeIqVQ+blscyZu aj0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4RRBlCah2JVCFYBxRJ0/Km6eRiEmJrEsdil+05pqvOQ=; b=mPApL6udw9WL+V9A/agZzO+A64IShjKbLbwi8mVs0pGaQ1GIZCoVGhpJbjo/DkeZ8J iWEw1eHm6LLQYm72CVg7bZycUaQb02A+VY8j2NOdxSA/3cYj0HSlsjS4GafkT8fE5Wtw hU0oXCkeo3ZbKXbm9EwEvh5JveDtHWiJcAx8lEnxENB7iDs3Q42NZz0A0mWrHXoYI+S8 +iQJFG13BJ9aIBL7BPnkICnFs3XPK3c3SQpqoaVcdWQMzk8aA5gznaLWmTRB7ocEPDgm gSnSJWxvF32DzjCrraJoOSdihksRY7bk9k//r9mfSKVzuzNmXch3x3HFx+s2hdjXFtER xpDQ== X-Gm-Message-State: AOAM533xL8ZdvpkR93N1cfcM2sXjEbBlSygpXkVr9zfcixQ0+/eVbDwy JXuf5HHHB6/ITAnfcUCtnTcw5g== X-Google-Smtp-Source: ABdhPJwhiLmlEKeWZ3or5vPbFtmvgw3cBjMJe7GnknS2fyY+ry+h/ScadxXjs0jezy4BIdQI3EeG1A== X-Received: by 2002:a17:902:778b:b029:df:e7bf:d660 with SMTP id o11-20020a170902778bb02900dfe7bfd660mr19101025pll.43.1612203246698; Mon, 01 Feb 2021 10:14:06 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:05 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 12/31] coresight: etm4x: Add commentary on the registers Date: Mon, 1 Feb 2021 11:13:32 -0700 Message-Id: <20210201181351.1475223-13-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131408_913120_C7285F68 X-CRM114-Status: GOOD ( 13.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose As we are about define a switch..case table for individual register access by offset for implementing the system instruction support, document the possible set of registers for each group to make it easier to correlate. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-11-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index b6854f6fd666..3c2b49ffabc8 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -45,13 +45,13 @@ #define TRCVDSACCTLR 0x0A4 #define TRCVDARCCTLR 0x0A8 /* Derived resources registers */ -#define TRCSEQEVRn(n) (0x100 + (n * 4)) +#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ #define TRCSEQRSTEVR 0x118 #define TRCSEQSTR 0x11C #define TRCEXTINSELR 0x120 -#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) -#define TRCCNTCTLRn(n) (0x150 + (n * 4)) -#define TRCCNTVRn(n) (0x160 + (n * 4)) +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ +#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ /* ID registers */ #define TRCIDR8 0x180 #define TRCIDR9 0x184 @@ -60,7 +60,7 @@ #define TRCIDR12 0x190 #define TRCIDR13 0x194 #define TRCIMSPEC0 0x1C0 -#define TRCIMSPECn(n) (0x1C0 + (n * 4)) +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ #define TRCIDR0 0x1E0 #define TRCIDR1 0x1E4 #define TRCIDR2 0x1E8 @@ -69,9 +69,12 @@ #define TRCIDR5 0x1F4 #define TRCIDR6 0x1F8 #define TRCIDR7 0x1FC -/* Resource selection registers */ +/* + * Resource selection registers, n = 2-31. + * First pair (regs 0, 1) is always present and is reserved. + */ #define TRCRSCTLRn(n) (0x200 + (n * 4)) -/* Single-shot comparator registers */ +/* Single-shot comparator registers, n = 0-7 */ #define TRCSSCCRn(n) (0x280 + (n * 4)) #define TRCSSCSRn(n) (0x2A0 + (n * 4)) #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) @@ -81,11 +84,13 @@ #define TRCPDCR 0x310 #define TRCPDSR 0x314 /* Trace registers (0x318-0xEFC) */ -/* Comparator registers */ +/* Address Comparator registers n = 0-15 */ #define TRCACVRn(n) (0x400 + (n * 8)) #define TRCACATRn(n) (0x480 + (n * 8)) +/* Data Value Comparator Value registers, n = 0-7 */ #define TRCDVCVRn(n) (0x500 + (n * 16)) #define TRCDVCMRn(n) (0x580 + (n * 16)) +/* ContextID/Virtual ContextID comparators, n = 0-7 */ #define TRCCIDCVRn(n) (0x600 + (n * 8)) #define TRCVMIDCVRn(n) (0x640 + (n * 8)) #define TRCCIDCCTLR0 0x680 From patchwork Mon Feb 1 18:13:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44167C433DB for ; Mon, 1 Feb 2021 18:17:42 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BA8DA64DE1 for ; Mon, 1 Feb 2021 18:17:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BA8DA64DE1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Kgipt9q2BXtExdH5TDhCuIzfZALQhs0gs9xNQhTdg2U=; b=IEQARk7Heo6FCkPZgBC7CV3M0 Q73MEdZLApe6THs7K4yzeJ6iI8qyfkqgLLSB6Tv333j+aATwkWHjjSxchWjatvxr7q3amjJGwM0XL Yi0dN/OmhRN2EchPLPKPfVFDcGopjQtR76J5fiENCgs+6NCzc4Aol2MQ1syYTBDwmhGzQ+WNVBvnb bs+T8mkKOWIkRJicnZOw25Y4A2fihjbCc8C0jhLeLMIKcbvToiF0Bwd3aNZ1DPX5yfw22gDV4dMP1 ya5beTX2Eu4MiOMUWd0P9hkSjCzCXCbJPE+36X57Z6SYPbIdoOU5D4vGLuFQM3bVkuaf2tF5g4/Ji gMyU/ZXiQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6djZ-0003ih-VR; Mon, 01 Feb 2021 18:15:34 +0000 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diE-00031i-HJ for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:23 +0000 Received: by mail-pg1-x536.google.com with SMTP id o16so12626497pgg.5 for ; Mon, 01 Feb 2021 10:14:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f+NFDJGlpM5QpztMeS6Hm1Oc/dcOLaVrzObDSDa29bg=; b=vwP8Z6xXnL1m8asUdIB5g/jSNUuoeJo832/cnhJcP+SRHzXWvY6621sRnh3dcErbA5 kZTVk0+87+UkkY4PDmUj44GVoAFd4PNtAaPgrJbmOQ4czK+oDKwiyCSkgSkIqkvVCaB4 CUoC8uyYQT3XJiw5Uarb6pKatffWr4YnfOavLy1tJ1jcfE0blh9SZpa0inviO6rHGzuY HdewBE7+wbXQkO+rSJoevUlxirpQehQg9VI1Q2g3XCpPTWza1c7M4w5hoq+h4a1+FAj0 oWWp3thkIa+5akxDSgsV/hb7FT7dGrS5elIGEY9P1dHIcB+lHb+0OMOhiXnf9+YJ3cuf QlRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f+NFDJGlpM5QpztMeS6Hm1Oc/dcOLaVrzObDSDa29bg=; b=CMhAudI4uPHmNN172Bs3Z5SKDgszLbz1hIYT3zNAfEtuIQBEBuLsxDFQsibACHFvfy /G8+rMBg2gHAvfD3JuB0xFLe8x/JzEHqfcgVdjEFPz3v0SYpxWrOyCIZ9aGTFx3rOpR7 K7Gt3g8KIDaaAMKwqu69RLfgxb49Dn71GuPe3B2xqLSiXZY4KEKbU+dyKRTOTEEx7ItT QTnGewTVgFsuSH2rqub8DkGsRJVa8Qjm5Wg34ASYYyfLBxqTl2J+hdWvqFD7Sf0/S6iO SYtQ5M58RttrEIOg9FdVitob8EU1/zAEmx3ToNud93HfUlaizI4ug2PE/l0PlTxjc/Et 1/fQ== X-Gm-Message-State: AOAM530/Ly1yIO+m7zJ/vHEZwmXQmz8r9Fef/Z06w4P8vb7necEIMuFa vYsZC0VR+AqHHcUR2VMtIv+T1IpOaKPPEw== X-Google-Smtp-Source: ABdhPJyLPgMuvrK3hefT02NxHJD58kX7+rr5r5xo4RABFSohcu2Ss2Jzcy++56LRNZ1jbzsyXxPk1A== X-Received: by 2002:a63:405:: with SMTP id 5mr18182162pge.44.1612203247911; Mon, 01 Feb 2021 10:14:07 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:07 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 13/31] coresight: etm4x: Add sysreg access helpers Date: Mon, 1 Feb 2021 11:13:33 -0700 Message-Id: <20210201181351.1475223-14-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131410_726221_8FBFF5ED X-CRM114-Status: GOOD ( 18.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose ETM architecture defines the system instructions for accessing via register accesses. Add basic support for accessing a given register via system instructions. We split the list of registers as : 1) Accessible only from memory mapped interface 2) Accessible from system register instructions. All registers are accessible via the memory-mapped interface. However, some registers are not accessible via the system instructions. This list is then used to further filter out the files we expose via sysfs. Cc: Mike Leach Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-12-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 32 ++ drivers/hwtracing/coresight/coresight-etm4x.h | 343 ++++++++++++++++-- 2 files changed, 353 insertions(+), 22 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 9331281b931f..37f90d380436 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -75,6 +75,38 @@ static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) (drvdata->config.ss_status[n] & TRCSSCSRn_PC); } +u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) +{ + u64 res = 0; + + switch (offset) { + ETM4x_READ_SYSREG_CASES(res) + default : + pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n", + offset); + } + + if (!_relaxed) + __iormb(res); /* Imitate the !relaxed I/O helpers */ + + return res; +} + +void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) +{ + if (!_relaxed) + __iowmb(); /* Imitate the !relaxed I/O helpers */ + if (!_64bit) + val &= GENMASK(31, 0); + + switch (offset) { + ETM4x_WRITE_SYSREG_CASES(val) + default : + pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n", + offset); + } +} + static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { /* Writing 0 to TRCOSLAR unlocks the trace registers */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 3c2b49ffabc8..24ba0da5b096 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -126,29 +126,325 @@ #define TRCCIDR2 0xFF8 #define TRCCIDR3 0xFFC -#define etm4x_relaxed_read32(csa, offset) \ - readl_relaxed((csa)->base + (offset)) - -#define etm4x_read32(csa, offset) \ - readl((csa)->base + (offset)) - -#define etm4x_relaxed_write32(csa, val, offset) \ - writel_relaxed((val), (csa)->base + (offset)) - -#define etm4x_write32(csa, val, offset) \ - writel((val), (csa)->base + (offset)) - -#define etm4x_relaxed_read64(csa, offset) \ - readq_relaxed((csa)->base + (offset)) - -#define etm4x_read64(csa, offset) \ - readq((csa)->base + (offset)) - -#define etm4x_relaxed_write64(csa, val, offset) \ - writeq_relaxed((val), (csa)->base + (offset)) +/* + * System instructions to access ETM registers. + * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions + */ +#define ETM4x_OFFSET_TO_REG(x) ((x) >> 2) + +#define ETM4x_CRn(n) (((n) >> 7) & 0x7) +#define ETM4x_Op2(n) (((n) >> 4) & 0x7) +#define ETM4x_CRm(n) ((n) & 0xf) + +#include +#define ETM4x_REG_NUM_TO_SYSREG(n) \ + sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n)) + +#define READ_ETM4x_REG(reg) \ + read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg))) +#define WRITE_ETM4x_REG(val, reg) \ + write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg))) + +#define read_etm4x_sysreg_const_offset(offset) \ + READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset)) + +#define write_etm4x_sysreg_const_offset(val, offset) \ + WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset)) + +#define CASE_READ(res, x) \ + case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; } + +#define CASE_WRITE(val, x) \ + case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; } + +/* List of registers accessible via System instructions */ +#define ETM_SYSREG_LIST(op, val) \ + CASE_##op((val), TRCPRGCTLR) \ + CASE_##op((val), TRCPROCSELR) \ + CASE_##op((val), TRCSTATR) \ + CASE_##op((val), TRCCONFIGR) \ + CASE_##op((val), TRCAUXCTLR) \ + CASE_##op((val), TRCEVENTCTL0R) \ + CASE_##op((val), TRCEVENTCTL1R) \ + CASE_##op((val), TRCSTALLCTLR) \ + CASE_##op((val), TRCTSCTLR) \ + CASE_##op((val), TRCSYNCPR) \ + CASE_##op((val), TRCCCCTLR) \ + CASE_##op((val), TRCBBCTLR) \ + CASE_##op((val), TRCTRACEIDR) \ + CASE_##op((val), TRCQCTLR) \ + CASE_##op((val), TRCVICTLR) \ + CASE_##op((val), TRCVIIECTLR) \ + CASE_##op((val), TRCVISSCTLR) \ + CASE_##op((val), TRCVIPCSSCTLR) \ + CASE_##op((val), TRCVDCTLR) \ + CASE_##op((val), TRCVDSACCTLR) \ + CASE_##op((val), TRCVDARCCTLR) \ + CASE_##op((val), TRCSEQEVRn(0)) \ + CASE_##op((val), TRCSEQEVRn(1)) \ + CASE_##op((val), TRCSEQEVRn(2)) \ + CASE_##op((val), TRCSEQRSTEVR) \ + CASE_##op((val), TRCSEQSTR) \ + CASE_##op((val), TRCEXTINSELR) \ + CASE_##op((val), TRCCNTRLDVRn(0)) \ + CASE_##op((val), TRCCNTRLDVRn(1)) \ + CASE_##op((val), TRCCNTRLDVRn(2)) \ + CASE_##op((val), TRCCNTRLDVRn(3)) \ + CASE_##op((val), TRCCNTCTLRn(0)) \ + CASE_##op((val), TRCCNTCTLRn(1)) \ + CASE_##op((val), TRCCNTCTLRn(2)) \ + CASE_##op((val), TRCCNTCTLRn(3)) \ + CASE_##op((val), TRCCNTVRn(0)) \ + CASE_##op((val), TRCCNTVRn(1)) \ + CASE_##op((val), TRCCNTVRn(2)) \ + CASE_##op((val), TRCCNTVRn(3)) \ + CASE_##op((val), TRCIDR8) \ + CASE_##op((val), TRCIDR9) \ + CASE_##op((val), TRCIDR10) \ + CASE_##op((val), TRCIDR11) \ + CASE_##op((val), TRCIDR12) \ + CASE_##op((val), TRCIDR13) \ + CASE_##op((val), TRCIMSPECn(0)) \ + CASE_##op((val), TRCIMSPECn(1)) \ + CASE_##op((val), TRCIMSPECn(2)) \ + CASE_##op((val), TRCIMSPECn(3)) \ + CASE_##op((val), TRCIMSPECn(4)) \ + CASE_##op((val), TRCIMSPECn(5)) \ + CASE_##op((val), TRCIMSPECn(6)) \ + CASE_##op((val), TRCIMSPECn(7)) \ + CASE_##op((val), TRCIDR0) \ + CASE_##op((val), TRCIDR1) \ + CASE_##op((val), TRCIDR2) \ + CASE_##op((val), TRCIDR3) \ + CASE_##op((val), TRCIDR4) \ + CASE_##op((val), TRCIDR5) \ + CASE_##op((val), TRCIDR6) \ + CASE_##op((val), TRCIDR7) \ + CASE_##op((val), TRCRSCTLRn(2)) \ + CASE_##op((val), TRCRSCTLRn(3)) \ + CASE_##op((val), TRCRSCTLRn(4)) \ + CASE_##op((val), TRCRSCTLRn(5)) \ + CASE_##op((val), TRCRSCTLRn(6)) \ + CASE_##op((val), TRCRSCTLRn(7)) \ + CASE_##op((val), TRCRSCTLRn(8)) \ + CASE_##op((val), TRCRSCTLRn(9)) \ + CASE_##op((val), TRCRSCTLRn(10)) \ + CASE_##op((val), TRCRSCTLRn(11)) \ + CASE_##op((val), TRCRSCTLRn(12)) \ + CASE_##op((val), TRCRSCTLRn(13)) \ + CASE_##op((val), TRCRSCTLRn(14)) \ + CASE_##op((val), TRCRSCTLRn(15)) \ + CASE_##op((val), TRCRSCTLRn(16)) \ + CASE_##op((val), TRCRSCTLRn(17)) \ + CASE_##op((val), TRCRSCTLRn(18)) \ + CASE_##op((val), TRCRSCTLRn(19)) \ + CASE_##op((val), TRCRSCTLRn(20)) \ + CASE_##op((val), TRCRSCTLRn(21)) \ + CASE_##op((val), TRCRSCTLRn(22)) \ + CASE_##op((val), TRCRSCTLRn(23)) \ + CASE_##op((val), TRCRSCTLRn(24)) \ + CASE_##op((val), TRCRSCTLRn(25)) \ + CASE_##op((val), TRCRSCTLRn(26)) \ + CASE_##op((val), TRCRSCTLRn(27)) \ + CASE_##op((val), TRCRSCTLRn(28)) \ + CASE_##op((val), TRCRSCTLRn(29)) \ + CASE_##op((val), TRCRSCTLRn(30)) \ + CASE_##op((val), TRCRSCTLRn(31)) \ + CASE_##op((val), TRCSSCCRn(0)) \ + CASE_##op((val), TRCSSCCRn(1)) \ + CASE_##op((val), TRCSSCCRn(2)) \ + CASE_##op((val), TRCSSCCRn(3)) \ + CASE_##op((val), TRCSSCCRn(4)) \ + CASE_##op((val), TRCSSCCRn(5)) \ + CASE_##op((val), TRCSSCCRn(6)) \ + CASE_##op((val), TRCSSCCRn(7)) \ + CASE_##op((val), TRCSSCSRn(0)) \ + CASE_##op((val), TRCSSCSRn(1)) \ + CASE_##op((val), TRCSSCSRn(2)) \ + CASE_##op((val), TRCSSCSRn(3)) \ + CASE_##op((val), TRCSSCSRn(4)) \ + CASE_##op((val), TRCSSCSRn(5)) \ + CASE_##op((val), TRCSSCSRn(6)) \ + CASE_##op((val), TRCSSCSRn(7)) \ + CASE_##op((val), TRCSSPCICRn(0)) \ + CASE_##op((val), TRCSSPCICRn(1)) \ + CASE_##op((val), TRCSSPCICRn(2)) \ + CASE_##op((val), TRCSSPCICRn(3)) \ + CASE_##op((val), TRCSSPCICRn(4)) \ + CASE_##op((val), TRCSSPCICRn(5)) \ + CASE_##op((val), TRCSSPCICRn(6)) \ + CASE_##op((val), TRCSSPCICRn(7)) \ + CASE_##op((val), TRCOSLAR) \ + CASE_##op((val), TRCOSLSR) \ + CASE_##op((val), TRCACVRn(0)) \ + CASE_##op((val), TRCACVRn(1)) \ + CASE_##op((val), TRCACVRn(2)) \ + CASE_##op((val), TRCACVRn(3)) \ + CASE_##op((val), TRCACVRn(4)) \ + CASE_##op((val), TRCACVRn(5)) \ + CASE_##op((val), TRCACVRn(6)) \ + CASE_##op((val), TRCACVRn(7)) \ + CASE_##op((val), TRCACVRn(8)) \ + CASE_##op((val), TRCACVRn(9)) \ + CASE_##op((val), TRCACVRn(10)) \ + CASE_##op((val), TRCACVRn(11)) \ + CASE_##op((val), TRCACVRn(12)) \ + CASE_##op((val), TRCACVRn(13)) \ + CASE_##op((val), TRCACVRn(14)) \ + CASE_##op((val), TRCACVRn(15)) \ + CASE_##op((val), TRCACATRn(0)) \ + CASE_##op((val), TRCACATRn(1)) \ + CASE_##op((val), TRCACATRn(2)) \ + CASE_##op((val), TRCACATRn(3)) \ + CASE_##op((val), TRCACATRn(4)) \ + CASE_##op((val), TRCACATRn(5)) \ + CASE_##op((val), TRCACATRn(6)) \ + CASE_##op((val), TRCACATRn(7)) \ + CASE_##op((val), TRCACATRn(8)) \ + CASE_##op((val), TRCACATRn(9)) \ + CASE_##op((val), TRCACATRn(10)) \ + CASE_##op((val), TRCACATRn(11)) \ + CASE_##op((val), TRCACATRn(12)) \ + CASE_##op((val), TRCACATRn(13)) \ + CASE_##op((val), TRCACATRn(14)) \ + CASE_##op((val), TRCACATRn(15)) \ + CASE_##op((val), TRCDVCVRn(0)) \ + CASE_##op((val), TRCDVCVRn(1)) \ + CASE_##op((val), TRCDVCVRn(2)) \ + CASE_##op((val), TRCDVCVRn(3)) \ + CASE_##op((val), TRCDVCVRn(4)) \ + CASE_##op((val), TRCDVCVRn(5)) \ + CASE_##op((val), TRCDVCVRn(6)) \ + CASE_##op((val), TRCDVCVRn(7)) \ + CASE_##op((val), TRCDVCMRn(0)) \ + CASE_##op((val), TRCDVCMRn(1)) \ + CASE_##op((val), TRCDVCMRn(2)) \ + CASE_##op((val), TRCDVCMRn(3)) \ + CASE_##op((val), TRCDVCMRn(4)) \ + CASE_##op((val), TRCDVCMRn(5)) \ + CASE_##op((val), TRCDVCMRn(6)) \ + CASE_##op((val), TRCDVCMRn(7)) \ + CASE_##op((val), TRCCIDCVRn(0)) \ + CASE_##op((val), TRCCIDCVRn(1)) \ + CASE_##op((val), TRCCIDCVRn(2)) \ + CASE_##op((val), TRCCIDCVRn(3)) \ + CASE_##op((val), TRCCIDCVRn(4)) \ + CASE_##op((val), TRCCIDCVRn(5)) \ + CASE_##op((val), TRCCIDCVRn(6)) \ + CASE_##op((val), TRCCIDCVRn(7)) \ + CASE_##op((val), TRCVMIDCVRn(0)) \ + CASE_##op((val), TRCVMIDCVRn(1)) \ + CASE_##op((val), TRCVMIDCVRn(2)) \ + CASE_##op((val), TRCVMIDCVRn(3)) \ + CASE_##op((val), TRCVMIDCVRn(4)) \ + CASE_##op((val), TRCVMIDCVRn(5)) \ + CASE_##op((val), TRCVMIDCVRn(6)) \ + CASE_##op((val), TRCVMIDCVRn(7)) \ + CASE_##op((val), TRCCIDCCTLR0) \ + CASE_##op((val), TRCCIDCCTLR1) \ + CASE_##op((val), TRCVMIDCCTLR0) \ + CASE_##op((val), TRCVMIDCCTLR1) \ + CASE_##op((val), TRCCLAIMSET) \ + CASE_##op((val), TRCCLAIMCLR) \ + CASE_##op((val), TRCAUTHSTATUS) \ + CASE_##op((val), TRCDEVARCH) \ + CASE_##op((val), TRCDEVID) + +/* List of registers only accessible via memory-mapped interface */ +#define ETM_MMAP_LIST(op, val) \ + CASE_##op((val), TRCDEVTYPE) \ + CASE_##op((val), TRCPDCR) \ + CASE_##op((val), TRCPDSR) \ + CASE_##op((val), TRCDEVAFF0) \ + CASE_##op((val), TRCDEVAFF1) \ + CASE_##op((val), TRCLAR) \ + CASE_##op((val), TRCLSR) \ + CASE_##op((val), TRCITCTRL) \ + CASE_##op((val), TRCPIDR4) \ + CASE_##op((val), TRCPIDR0) \ + CASE_##op((val), TRCPIDR1) \ + CASE_##op((val), TRCPIDR2) \ + CASE_##op((val), TRCPIDR3) + +#define ETM4x_READ_SYSREG_CASES(res) ETM_SYSREG_LIST(READ, (res)) +#define ETM4x_WRITE_SYSREG_CASES(val) ETM_SYSREG_LIST(WRITE, (val)) + +#define read_etm4x_sysreg_offset(offset, _64bit) \ + ({ \ + u64 __val; \ + \ + if (__builtin_constant_p((offset))) \ + __val = read_etm4x_sysreg_const_offset((offset)); \ + else \ + __val = etm4x_sysreg_read((offset), true, (_64bit)); \ + __val; \ + }) + +#define write_etm4x_sysreg_offset(val, offset, _64bit) \ + do { \ + if (__builtin_constant_p((offset))) \ + write_etm4x_sysreg_const_offset((val), \ + (offset)); \ + else \ + etm4x_sysreg_write((val), (offset), true, \ + (_64bit)); \ + } while (0) + + +#define etm4x_relaxed_read32(csa, offset) \ + ((u32)((csa)->io_mem ? \ + readl_relaxed((csa)->base + (offset)) : \ + read_etm4x_sysreg_offset((offset), false))) + +#define etm4x_relaxed_read64(csa, offset) \ + ((u64)((csa)->io_mem ? \ + readq_relaxed((csa)->base + (offset)) : \ + read_etm4x_sysreg_offset((offset), true))) + +#define etm4x_read32(csa, offset) \ + ({ \ + u32 __val = etm4x_relaxed_read32((csa), (offset)); \ + __iormb(__val); \ + __val; \ + }) + +#define etm4x_read64(csa, offset) \ + ({ \ + u64 __val = etm4x_relaxed_read64((csa), (offset)); \ + __iormb(__val); \ + __val; \ + }) + +#define etm4x_relaxed_write32(csa, val, offset) \ + do { \ + if ((csa)->io_mem) \ + writel_relaxed((val), (csa)->base + (offset)); \ + else \ + write_etm4x_sysreg_offset((val), (offset), \ + false); \ + } while (0) + +#define etm4x_relaxed_write64(csa, val, offset) \ + do { \ + if ((csa)->io_mem) \ + writeq_relaxed((val), (csa)->base + (offset)); \ + else \ + write_etm4x_sysreg_offset((val), (offset), \ + true); \ + } while (0) + +#define etm4x_write32(csa, val, offset) \ + do { \ + __iowmb(); \ + etm4x_relaxed_write32((csa), (val), (offset)); \ + } while (0) + +#define etm4x_write64(csa, val, offset) \ + do { \ + __iowmb(); \ + etm4x_relaxed_write64((csa), (val), (offset)); \ + } while (0) -#define etm4x_write64(csa, val, offset) \ - writeq((val), (csa)->base + (offset)) /* ETMv4 resources */ #define ETM_MAX_NR_PE 8 @@ -522,4 +818,7 @@ enum etm_addr_ctxtype { extern const struct attribute_group *coresight_etmv4_groups[]; void etm4_config_trace_mode(struct etmv4_config *config); + +u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); +void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit); #endif From patchwork Mon Feb 1 18:13:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E63DAC43381 for ; Mon, 1 Feb 2021 18:17:27 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5258F64E50 for ; Mon, 1 Feb 2021 18:17:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5258F64E50 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=o091Hia/5GSGozUNe+YOEpFoRCnYF8RmNPsowBr4gtE=; b=ivLA9bH956aiqoWzDDZCg/aV/ QgKwvSSR3vx70XSj62KmUiEal4MNPFhSdFBH0QA4sWF2MowgUmfAjEfBLW1RnIUDfq/m78y88VHDV WbNH8Vvd/S1OSqWCF1Slo2JHueRtzNddVoogX63g05bNpArDnsbZVNF4YjOOliCwKNZnlP7O7zM3G HEuM1HMMIuG3aVh4XQGgMM1FuKircB+CVxLp++yeO6EyCNl3OqDFwpsKAhjgauNinsCeE5hgK0tGs LZU5rvtwFsuVfH51ddiLQxf8wiqxtD9qb8JS6p6cFDgFia+DSFNRuK26XtjF4D0JP4ChivcUz2Vqc zmKl/JQsQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6djV-0003fs-Ko; Mon, 01 Feb 2021 18:15:29 +0000 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diF-000321-6S for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:22 +0000 Received: by mail-pg1-x52c.google.com with SMTP id t25so12642647pga.2 for ; Mon, 01 Feb 2021 10:14:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ex6Az5IYLj6cR6ue6WRS2UBP68zfl2Dt28cPPgU4zxE=; b=n/TPBFoXW/jBQamWy7UtyG/wcdV85ayugtTfFZSaTpR39cXEzsUJpb1UVjoCzF+Mop C2NPOWTr5+ROcBURQz13SBL9iRp6sqG1YNhx0OKliBCUxB11q4+siEivyPAR6NCVIB8D 5H3Ea8zUH0MKYGoVyFQjz/czzrg6qjF42O/50MRDr1bewOKaD3/53N2RIdULNb28w36+ tBOGIKP+BRCG/GHeBI1KMk8/ieQlXgi8Ic2Kq+hZh9ajjCpJre5ChQq8oYXmgYMVDaiw m54Dbh6XH6lslwh4x6ADBFbsE1xb/fZNA71hrYbKwTw8xKphyXEPPwRW9ELAtRiV68nF gu9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ex6Az5IYLj6cR6ue6WRS2UBP68zfl2Dt28cPPgU4zxE=; b=LzoD3FrzK/16G8RtfQfXSM0oGF29hfwK34QKYAwLZwpLvnbzyWgOzhr5lEI9jXKg7E T8cDLYv1YAScpk0vnL5yfz5jZEZsb5rE11qhbtuHw97oOqF/76FEc7mGw/OPuma9dcMk N97ZPiujY+TZyy3WLQi3odJYq2gpxS+XHch1LvZ774r/R/Cl/bA1WWDzxOeEOte201TY LKM4TcaQuJqe4XOQPFFxzCxJaYwqjRBKyY8xYgMGP2iL0zIV0RavsX3PUZOLdulLPzwW 08ONubJVUzTa7OnD7biGRv9RMKMFkch+FnCrzD/SbP7i1x8rrwGcE6oL1n4bjS6uVh3z FxHw== X-Gm-Message-State: AOAM533uFUbtP7RMaGw1hW99KpLeH8yDoYoWyQLTRvYD2GEfFeiahxuR hiDknEF9Si8VvwxrdGqSyZ4F+g== X-Google-Smtp-Source: ABdhPJz4XfjLbEDIofu1JNEkj23kXX3CQ51umXIfXzgj2BSk8EVTG40xfhiYo9nDcayx2gp01Pc8tw== X-Received: by 2002:a63:4e63:: with SMTP id o35mr17700966pgl.291.1612203248787; Mon, 01 Feb 2021 10:14:08 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:08 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 14/31] coresight: etm4x: Hide sysfs attributes for unavailable registers Date: Mon, 1 Feb 2021 11:13:34 -0700 Message-Id: <20210201181351.1475223-15-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131411_350854_13A35EDF X-CRM114-Status: GOOD ( 20.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose Some of the management registers in ETMv4.x are not accessible via system register instructions. Thus we must hide the sysfs files exposing them to the userspace, to prevent system crashes. This patch adds an is_visible() routine to control the visibility at runtime for the registers that may not be accessed. Cc: Mathieu Poirier Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-13-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-sysfs.c | 51 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.h | 6 +++ 2 files changed, 57 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index ddbfeb24fc3f..e8fdda45ffca 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2370,6 +2370,56 @@ static ssize_t coresight_etm4x_reg_show(struct device *dev, return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); } +static inline bool +etm4x_register_implemented(struct etmv4_drvdata *drvdata, u32 offset) +{ + switch (offset) { + ETM4x_SYSREG_LIST_CASES + /* + * Registers accessible via system instructions are always + * implemented. + */ + return true; + ETM4x_MMAP_LIST_CASES + /* + * Registers accessible only via memory-mapped registers + * must not be accessed via system instructions. + * We cannot access the drvdata->csdev here, as this + * function is called during the device creation, via + * coresight_register() and the csdev is not initialized + * until that is done. So rely on the drvdata->base to + * detect if we have a memory mapped access. + */ + return !!drvdata->base; + } + + return false; +} + +/* + * Hide the ETM4x registers that may not be available on the + * hardware. + * There are certain management registers unavailable via system + * instructions. Make those sysfs attributes hidden on such + * systems. + */ +static umode_t +coresight_etm4x_attr_reg_implemented(struct kobject *kobj, + struct attribute *attr, int unused) +{ + struct device *dev = kobj_to_dev(kobj); + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct device_attribute *d_attr; + u32 offset; + + d_attr = container_of(attr, struct device_attribute, attr); + offset = coresight_etm4x_attr_to_offset(d_attr); + + if (etm4x_register_implemented(drvdata, offset)) + return attr->mode; + return 0; +} + #define coresight_etm4x_reg(name, offset) \ &((struct dev_ext_attribute[]) { \ { \ @@ -2417,6 +2467,7 @@ static const struct attribute_group coresight_etmv4_group = { }; static const struct attribute_group coresight_etmv4_mgmt_group = { + .is_visible = coresight_etm4x_attr_reg_implemented, .attrs = coresight_etmv4_mgmt_attrs, .name = "mgmt", }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 24ba0da5b096..193d2819afa7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -157,6 +157,9 @@ #define CASE_WRITE(val, x) \ case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; } +#define CASE_NOP(__unused, x) \ + case (x): /* fall through */ + /* List of registers accessible via System instructions */ #define ETM_SYSREG_LIST(op, val) \ CASE_##op((val), TRCPRGCTLR) \ @@ -369,6 +372,9 @@ #define ETM4x_READ_SYSREG_CASES(res) ETM_SYSREG_LIST(READ, (res)) #define ETM4x_WRITE_SYSREG_CASES(val) ETM_SYSREG_LIST(WRITE, (val)) +#define ETM4x_SYSREG_LIST_CASES ETM_SYSREG_LIST(NOP, __unused) +#define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused) + #define read_etm4x_sysreg_offset(offset, _64bit) \ ({ \ u64 __val; \ From patchwork Mon Feb 1 18:13:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E31DEC43381 for ; Mon, 1 Feb 2021 18:17:58 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49BCE64EA1 for ; Mon, 1 Feb 2021 18:17:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 49BCE64EA1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=jgAH9jGnbdzvWU48k/SvQGu66Q8s2bmCtTOLwVUegzM=; b=T3EE7l93eVxPQeKoKn8VvSR1J gp9dAHrlxDgjRwodkR/nbk0xBXBrVNyQsRB3yUOq5I8Npzi7kYJ+ayMOTAZq+PbJYzTlz/bq3Uu/m Br4D5fkJ8RuY2hLvNt4TQFUH0u7Ak9nRVQ6nYwDKAs0OcrUsu8bZeiuVS7vW9PgBM8sGIcBrZJuBO SZPGSl2iCypjNOBUibCvS21SEN0k5UeWzslvd5Y9H4+6IRC/ngIhgtY65XFePuGNDuONLp1iunwRd nr04CMbcg1qxz8IWo04nh93SUK9wdZKw0fKYHxP/5kmkXbdLA0tqO+6dkHYSh0iaSRIFuUUGLRtoC K+LOrd0ig==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6djz-0003vX-Mf; Mon, 01 Feb 2021 18:16:01 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diF-000325-L1 for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:27 +0000 Received: by mail-pj1-x1029.google.com with SMTP id gx20so88691pjb.1 for ; Mon, 01 Feb 2021 10:14:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gZHHgMd2DF7eOHXrryvC3652lFec+KRo8i3F2jjRyIY=; b=h5/BT7ssV6f/lY/QPEpcBlU+EjYrFM1Ho90LRBm7jkh50+eeK2EaSapsH+ldy2GMFH dbTZZQsLrVZn21yNOsbx9OVcBFWnjfwg1GX9yVr3hYIry/wthOaUh93qn29tPo1Jn2xC mkysB2b0em36SKr8BnkyQ4zxdlavTiiqAnfYAg3EmJdsobHhEvuwWMxTKxDbo02JnuW0 rO3Vuc4KUbtBAXMQzYWtumnxKCVx1yMPhy2UQcW4kYONf61lGxTpv0rK8H3b1RFGoQ4r RiZBoNGwh4WxG8kVhR0LdvF0fqGNNywEM8p+4f0HCzw6ahkhULRS26Y2s7CygXHHgt8q h17Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gZHHgMd2DF7eOHXrryvC3652lFec+KRo8i3F2jjRyIY=; b=XnGQ2NkUgivLfaGSLargyYDypVRe0GUmh4TFxkvL1ENVjGwzho/nJfUto8vY9IoKlX pHv5rPF0ufJy52p5btPSMV2HV6ZBeIqcW9zOCk3iS9+OIWYWAajG4xSfN1pJg4JAIli2 0UGj14UcVPq/o7Iwn0alyGbKi6kZGe2opnwySb70srmx9KH2efSuN9EgDgH59j2uwxQn C49b1IJjS1PdvNI7QNBcOOaVv+Bgi+ucoi+NEfwQUq0mKpMjK9ngrt1MBy+IpRiBlWVI cZqvpa9Vbxr/G9mfi3BwAka8Wt7HY41TCW42nFHBJnZnNHuJscdj3vB0bkiHXVX/waQw zdCw== X-Gm-Message-State: AOAM530b6HVft+LFJtGniDTqcDn5Y7Se5yRJrB0NtMc3SrhV4kB+iYWF cG9Eca1P7nRoThd0xT748ndvK/QIuUAOSA== X-Google-Smtp-Source: ABdhPJy3K3xVS7WDAk9hnk2f/brxYo2shhJg6/nTZ3QySyctXmBChtK08y5vx/Ki1eCJ0Ga6m6O02A== X-Received: by 2002:a17:90b:30d4:: with SMTP id hi20mr123401pjb.41.1612203249684; Mon, 01 Feb 2021 10:14:09 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:09 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 15/31] coresight: etm4x: Define DEVARCH register fields Date: Mon, 1 Feb 2021 11:13:35 -0700 Message-Id: <20210201181351.1475223-16-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131413_693333_91C75694 X-CRM114-Status: GOOD ( 16.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose Define the fields of the DEVARCH register for identifying a component as an ETMv4.x unit. Going forward, we use the DEVARCH register for the component identification, rather than the TRCIDR3. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-14-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 4 +- drivers/hwtracing/coresight/coresight-etm4x.h | 42 +++++++++++++++++++ 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 37f90d380436..04ec13ae22d0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1720,8 +1720,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) static struct amba_cs_uci_id uci_id_etm4[] = { { /* ETMv4 UCI data */ - .devarch = 0x47704a13, - .devarch_mask = 0xfff0ffff, + .devarch = ETM_DEVARCH_ETMv4x_ARCH, + .devarch_mask = ETM_DEVARCH_ID_MASK, .devtype = 0x00000013, } }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 193d2819afa7..fba3c02eea0b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -506,6 +506,48 @@ ETM_MODE_EXCL_KERN | \ ETM_MODE_EXCL_USER) +/* + * TRCDEVARCH Bit field definitions + * Bits[31:21] - ARCHITECT = Always Arm Ltd. + * * Bits[31:28] = 0x4 + * * Bits[27:21] = 0b0111011 + * Bit[20] - PRESENT, Indicates the presence of this register. + * + * Bit[19:16] - REVISION, Revision of the architecture. + * + * Bit[15:0] - ARCHID, Identifies this component as an ETM + * * Bits[15:12] - architecture version of ETM + * * = 4 for ETMv4 + * * Bits[11:0] = 0xA13, architecture part number for ETM. + */ +#define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21) +#define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21)) +#define ETM_DEVARCH_PRESENT BIT(20) +#define ETM_DEVARCH_REVISION_SHIFT 16 +#define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16) +#define ETM_DEVARCH_REVISION(x) \ + (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT) +#define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0) +#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12 +#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12) +#define ETM_DEVARCH_ARCHID_ARCH_VER(x) \ + (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) + +#define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \ + (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) + +#define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL) + +#define ETM_DEVARCH_MAKE_ARCHID(major) \ + ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13)) + +#define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4) + +#define ETM_DEVARCH_ID_MASK \ + (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT) +#define ETM_DEVARCH_ETMv4x_ARCH \ + (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT) + #define TRCSTATR_IDLE_BIT 0 #define TRCSTATR_PMSTABLE_BIT 1 #define ETM_DEFAULT_ADDR_COMP 0 From patchwork Mon Feb 1 18:13:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DB13C433E0 for ; Mon, 1 Feb 2021 18:18:16 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D23AD64EA0 for ; Mon, 1 Feb 2021 18:18:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D23AD64EA0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9VTSfkxtzPEb2NLOa3o6WJPEMFUMV6FM7426OKEZgv0=; b=J9wpbxjPMBKw8VnhzblRdVNb8 8wbzmMrHZYkzrodwxIPyPin32LZB0ELbS/ao4pF0LYDKuqT2X8MeE5o7l2NniA/yPonToO6JAWX3o 7zykQ4J9w3Wxg40RwKZfn2psHWQs3x6lkcvpXoE1qPngPa93WLb3RQLHgUGWFRWWtnE3aR7qHo2cf lZOu36wvk8rNHrSsakWbriSWZX9jDW3Z4eNCGJj9EOR/mmGpALoIR4naiquJAcpNiR3xAjAqKUfMm 05o1RmRIVyM1nx0RmOgQZSKkFKiWQK7VslHTwwl/3UOw6fXZ5dCrTb5SCMhVZrpvpmFu1+aDzgdwm vxVOk3E1Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dkO-000476-79; Mon, 01 Feb 2021 18:16:24 +0000 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diG-00033J-Ld for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:27 +0000 Received: by mail-pl1-x634.google.com with SMTP id s15so10467112plr.9 for ; Mon, 01 Feb 2021 10:14:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z8giPwxj7vPgzjb7g95oKc+3Cw8pXaIxrf1NzUl/Xd0=; b=FHxNMFgRSe9PUUoCEfgUM4HHAEhSwwIeVu9sU4MrST+0e7/N8ozFRXThlnneG+V6c9 oBf/Qc0sep8Rye3yznSRXKcY0oxkyHBZlCwsnex9qLO4O93tHdzDdxs7gYGd3aL2DKIU 2XkO5/iQ0rnGDpSunmhD8ridCUkq1t1+BGDmprZ+EINmi6WxTzWGpFWrC/TNswdrDyZG LTgN7EW25cZDkCgNVgK/oLUgyVZztA/V2YXH9OJSdwyQEnkYqWZpgaARCLhbF8UqWnWZ KLWqUVVatzwU9pwrljXrHDP2vNbSI7uFWy4f0CzhoOOTsALeMehyUjZ5A9Dz45tU6OsW vmPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z8giPwxj7vPgzjb7g95oKc+3Cw8pXaIxrf1NzUl/Xd0=; b=IAwQJkxg1t/p//rv58VCeED28+J08kCPJr+Jgm4yi4wJLCFutgrjE0hkMr6QsIfipQ l14zVWTNZ/+qX49VFlklcD6ayQ1poHZt5/vBlMslX+QL33jvUbZikTPayXdvyqa/tALg 433Hyk2IqcdFGckiKhFlPvuAnKP0SoS240Zhu2JVFyqJdXwSkMOq5BX+S/T5uLusMY6B DvtyBSZTBK1Zv3sKJU8TK5c4TSwM1rX+1zk5nqXwiUfQKhbeEme1VeT4Ch15WgILNjCa Z1xxe1s6iRnGKJwTuMKNp4lo/iTG46KHpUPtxLo8doM/VT7yhWBtkq0VDqRJhR/T7Ydh Qeqw== X-Gm-Message-State: AOAM530fwI7NT2DWGy48+zVtZpVqch3DYRCIAwawvz8CVy3c5KclpJwC rdThsDfrrvsWJSTtQFRbLW7qfw== X-Google-Smtp-Source: ABdhPJw6bU2hecLs+M0YUQANIhUQ4ncMLPSvLGyOG+7FnT1yOvRALlzNWVwfQ7ZEvU4UQ4JwHfzyEg== X-Received: by 2002:a17:902:d4d0:b029:df:d246:ca81 with SMTP id o16-20020a170902d4d0b02900dfd246ca81mr18973848plg.58.1612203250804; Mon, 01 Feb 2021 10:14:10 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:10 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 16/31] coresight: etm4x: Check for Software Lock Date: Mon, 1 Feb 2021 11:13:36 -0700 Message-Id: <20210201181351.1475223-17-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131413_689329_B9E64364 X-CRM114-Status: GOOD ( 16.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose The Software lock is not implemented for system instructions based accesses. So, skip the lock register access in such cases. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-15-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 40 ++++++++++++------- 1 file changed, 26 insertions(+), 14 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 04ec13ae22d0..f095ab9949d9 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -133,6 +133,21 @@ static void etm4_os_lock(struct etmv4_drvdata *drvdata) isb(); } +static void etm4_cs_lock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + /* Software Lock is only accessible via memory mapped interface */ + if (csa->io_mem) + CS_LOCK(csa->base); +} + +static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + if (csa->io_mem) + CS_UNLOCK(csa->base); +} + static bool etm4_arch_supported(u8 arch) { /* Mask out the minor version number */ @@ -263,7 +278,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) struct device *etm_dev = &csdev->dev; struct csdev_access *csa = &csdev->access; - CS_UNLOCK(drvdata->base); + + etm4_cs_unlock(drvdata, csa); etm4_enable_arch_specific(drvdata); etm4_os_unlock(drvdata); @@ -366,7 +382,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) isb(); done: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n", drvdata->cpu, rc); @@ -623,7 +639,7 @@ static void etm4_disable_hw(void *info) struct csdev_access *csa = &csdev->access; int i; - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); etm4_disable_arch_specific(drvdata); if (!drvdata->skip_power_up) { @@ -665,8 +681,7 @@ static void etm4_disable_hw(void *info) } coresight_disclaim_device_unlocked(csdev); - - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); dev_dbg(&drvdata->csdev->dev, "cpu: %d disable smp call done\n", drvdata->cpu); @@ -776,8 +791,7 @@ static void etm4_init_arch_data(void *info) /* Make sure all registers are accessible */ etm4_os_unlock_csa(drvdata, csa); - - CS_UNLOCK(drvdata->base); + etm4_cs_unlock(drvdata, csa); /* find all capabilities of the tracing unit */ etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); @@ -942,7 +956,7 @@ static void etm4_init_arch_data(void *info) drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); /* NUMCNTR, bits[30:28] number of counters available for tracing */ drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } /* Set ELx trace filter access in the TRCVICTLR register */ @@ -1323,8 +1337,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) dsb(sy); isb(); - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); /* Lock the OS lock to disable trace and external debugger access */ etm4_os_lock(drvdata); @@ -1437,7 +1450,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR); out: - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); return ret; } @@ -1448,8 +1461,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); struct csdev_access *csa = &tmp_csa; - CS_UNLOCK(drvdata->base); - + etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); @@ -1534,7 +1546,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) /* Unlock the OS lock to re-enable trace and external debug access */ etm4_os_unlock(drvdata); - CS_LOCK(drvdata->base); + etm4_cs_lock(drvdata, csa); } static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, From patchwork Mon Feb 1 18:13:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F161C433E0 for ; Mon, 1 Feb 2021 18:19:11 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B947464EA8 for ; Mon, 1 Feb 2021 18:19:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B947464EA8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=d2EDUXpVduabrIMSzRMu2ItHr/EeSkwPB5Gtb1pug9M=; b=P+AAV3QeHYLlCJKgTkfdWor1k bt+pHkRi01nMhBShUgGDIMXM242yl0vlWat8zAn0HOL5mQHqf2TlPcq4OnocDxMmZP5a+YqMeLo6s 6dMzubL6YCnvXiLs2ohvUAOBwDqZ2w2EfAWwsYV3f7H1J9Y4qxXjmOB6hF0DoOdPHk46ayTsUqp8M tGlTC5+FzUW0vJqclBr5xwpZTQ/pmzG6JCj2FcRG98Sotb3sf1DJ+N0UcvkcNkSMNXLonqgzYVp0K LcUVjUCBo6ux1UaTfl5832+ueDI8XH07n66bQfSEfa1zml6/U4yjbyqjUrwGdR2me+hKjt6ME7l+1 VjqGIdHeA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dky-0004Zy-Mv; Mon, 01 Feb 2021 18:17:00 +0000 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diI-00033Z-0G for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:31 +0000 Received: by mail-pl1-x62d.google.com with SMTP id b8so10456105plh.12 for ; Mon, 01 Feb 2021 10:14:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Nkl7K2vw3TX4frhQPmfegkQUMEyqX+IThipL7KY2uDo=; b=iIgmVpOKir7028W23vrGXUNsAxqqcr87Dah8tG6OvnNYIf24c+MTPaS8nMFxSxLlqW v6nXnmm1Gom//iRpRbv8tXFt4hNGfMuFOoeUHNLn/p8Qt48PBym3QJsVk8u1o+nXNQSo oQu/JtFFOMWLV9XEwqVIlPxd9orDLyTXN5LFOs4W39L9SjFHV9mfPXjdECylXiVnUk4s NdgLABs71iWl2y9wFn2KEWLU5S0P6a9DBQNVgfV6pN5A+Goh+3wxTNufMsWM8wpSVfpz /sbOlIa0QvqueF4iIuvieYMI2uvMs3hLhdHVoRN2kNozOw8AKJoqohXsC+iTu5ATu1Nx Ie+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Nkl7K2vw3TX4frhQPmfegkQUMEyqX+IThipL7KY2uDo=; b=Kbov8OYOTqshaOtBI5d97k7hpJgmus5Bx74jW8e33bVEKUNXLyO8cmP2hKQ9RyhLAM NH0UGVehaeaZ+y+hXIAXncxcXkqT6wkDQyRm8CLW8u5dhPexLnbW9yz4kSaB+iW711hk fFJp2tpn/WcJwjOdBOKTPDOWrUPIbWdv4nz7oFvq4S0DzarCxUle75zHzGq4hTrG0tNA +0MKqzsxMrTO+Gg+gcXF1AIm4UHvinNK+2jpet7Dsh4bEYISwR6MKJ+QjU12ZyXNpJNz ivst3H/gmphCdD1nLBEnprOISvf51meirXCPWputBLercSvbkjR7Z0o279wHYmQY7AQw 6tFg== X-Gm-Message-State: AOAM533v+j5Wo31t+dKTIvMaVUtDW0Vdd03fJhZmqZ4bk79mIXdCmDEY XrlXj2tLTb7yJAYBlJMTpQsLMg== X-Google-Smtp-Source: ABdhPJzuIgvytfBVtpkA2FJ9wHNHdDAGigkR/PxPydd4F18Pek1Eo61VNMxbJwmCpy5rOUXZGyoTLA== X-Received: by 2002:a17:902:c40b:b029:de:2f1e:825c with SMTP id k11-20020a170902c40bb02900de2f1e825cmr18945101plk.64.1612203251771; Mon, 01 Feb 2021 10:14:11 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:11 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 17/31] coresight: etm4x: Cleanup secure exception level masks Date: Mon, 1 Feb 2021 11:13:37 -0700 Message-Id: <20210201181351.1475223-18-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131414_986412_FCA29956 X-CRM114-Status: GOOD ( 15.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose We rely on the ETM architecture version to decide whether Secure EL2 is available on the CPU for excluding the level for address comparators and viewinst main control register. We must instead use the TRCDIDR3.EXLEVEL_S field to detect the supported levels. Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-16-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 6 ++++-- 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index f095ab9949d9..d91b259a4334 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -840,7 +840,6 @@ static void etm4_init_arch_data(void *info) * TRCARCHMAJ, bits[11:8] architecture major versin number */ drvdata->arch = BMVAL(etmidr1, 4, 11); - drvdata->config.arch = drvdata->arch; /* maximum size of resources */ etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); @@ -856,6 +855,7 @@ static void etm4_init_arch_data(void *info) drvdata->ccitmin = BMVAL(etmidr3, 0, 11); /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ drvdata->s_ex_level = BMVAL(etmidr3, 16, 19); + drvdata->config.s_ex_level = drvdata->s_ex_level; /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23); @@ -1027,16 +1027,9 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) static u64 etm4_get_access_type(struct etmv4_config *config) { u64 access_type = etm4_get_ns_access_type(config); - u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0; - /* - * EXLEVEL_S, bits[11:8], don't trace anything happening - * in secure state. - */ - access_type |= (ETM_EXLEVEL_S_APP | - ETM_EXLEVEL_S_OS | - s_hyp | - ETM_EXLEVEL_S_MON); + /* All supported secure ELs are excluded */ + access_type |= (u64)config->s_ex_level << TRCACATR_EXLEVEL_SHIFT; return access_type; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index fba3c02eea0b..29cd27f53e72 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -557,6 +557,8 @@ /* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3) +#define TRCACATR_EXLEVEL_SHIFT 8 + /* secure state access levels - TRCACATRn */ #define ETM_EXLEVEL_S_APP BIT(8) #define ETM_EXLEVEL_S_OS BIT(9) @@ -631,7 +633,7 @@ enum etm_impdef_type { * @vmid_mask0: VM ID comparator mask for comparator 0-3. * @vmid_mask1: VM ID comparator mask for comparator 4-7. * @ext_inp: External input selection. - * @arch: ETM architecture version (for arch dependent config). + * @s_ex_level: Secure ELs where tracing is supported. */ struct etmv4_config { u32 mode; @@ -675,7 +677,7 @@ struct etmv4_config { u32 vmid_mask0; u32 vmid_mask1; u32 ext_inp; - u8 arch; + u8 s_ex_level; }; /** From patchwork Mon Feb 1 18:13:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C9A3C433DB for ; Mon, 1 Feb 2021 18:20:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 88E2864E50 for ; Mon, 1 Feb 2021 18:20:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 88E2864E50 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GTf+D0+7r41WiLYjPKXb2b5qTxTGc+Q6npBHfJJnjSE=; b=0DGlA2EyhDAfJVGUIYQCOUQFf mub/aFIZGH8k54WLOliEhTIlbSECb0iAcmLGFJaYuXxNe7IMTqPyEYuCy0n03Mh5TYQtJR3+/yHzT U484NWkYr49kdJZS8L3wNiJgkAthPA/6IhcGT5NGdmlUv1TmoirjM2Iee7uG3vRovjcDjT6zUy0Wx 6+ZEhM4qeFSgbw0aqEzZMKC3QqkhZfyTMwkNgA2Yh0Ln49zObt/1SAFj8xL/jgmjer0pwir0jYpRE NePbNqeBrf/yQ+Oh1yOY7AHuzcZuAKdYMLJY3Pd81kURZcU2nBzF263VX7tS7dwTc/XJNVjuO6kZH c5mnBSeFw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dm8-0005Db-95; Mon, 01 Feb 2021 18:18:12 +0000 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diJ-000347-5B for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:32 +0000 Received: by mail-pl1-x634.google.com with SMTP id p21so736203pld.8 for ; Mon, 01 Feb 2021 10:14:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cry816/nSGJZaakAE5oUCDuh5GR8b59TtsUrvCCp4xM=; b=MEvx6jXdM8va8vSZnJhFkcQgtBPM0HbCoiQnPaLm2SvZgrMCg26IdQEM6jcA9jO+NF aSvrDFmHTRYIYIFht6kA1KdHktDn60vo1l1tnWHAPZ8RMdOHDIZOtgxHSxmUWq19QDDR gy7DB2sBjKpaCFvrz/D1LqZFxKrAC0bt7A+8PjZXJC1UwUukK04JGK+mLug7ZlShncTc k/KppVrz/BTAQ3l5FbpwYgPo7CepiODvBWgPlphEogi1Jc0NcR+SpmZ9d8LTIdm4uWBQ 18r4ZckVhceZGAzvBdLwyYmy7qslldy2RM4kpp/viZTBsdbCR5PV7wq3WthCTrs9ubEa fyQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cry816/nSGJZaakAE5oUCDuh5GR8b59TtsUrvCCp4xM=; b=MaXpYSSKvcCjZxMFLja24tVWmnON3iXs9mZ+H5W6u+2aXWxJGBrwjA6tUMVKX1grWB Awo3X8YXvA0BjSR7Ppq3oVjYz0rWQUfmmEyo3tPZOtUUa7L5sFHfkD+/zODP40fKpWox lAOFKBLoh33a9fg+0WnLm3Jyv/sgESyu2SYDOQIFmLiqxGLIiJf6aLeDGe91GGFSktLU qDLsjz4/922vPdWVdFn/Rj3FrA+coHBlX8vml7LRiOMRxXRAlcG/TfQdS7EPOLAfFyrb bxjPqHNzX2s910iZXsN9NMYS4DdE39RL0r+e/cpli86masGIW0Dp9Sowxq83RuFWf7mV xp/w== X-Gm-Message-State: AOAM531xW/+rLlgoZV0jv44vExFGo/fR7El4BTA43D93SXAim3ZSXq78 1UP/88d1Cn36Inq0kaE/dFw99p/8errtkA== X-Google-Smtp-Source: ABdhPJzU1zYTOVaXWXqw4dMF6ou0XXtlAyHt0WeOq2zwKSe/eWlmQaAdrVBUYBpRjQBKXTT/C/lM1Q== X-Received: by 2002:a17:902:ea0f:b029:de:5fd5:abb9 with SMTP id s15-20020a170902ea0fb02900de5fd5abb9mr18746751plg.46.1612203252860; Mon, 01 Feb 2021 10:14:12 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:12 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 18/31] coresight: etm4x: Clean up exception level masks Date: Mon, 1 Feb 2021 11:13:38 -0700 Message-Id: <20210201181351.1475223-19-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131415_330351_1FFB77C7 X-CRM114-Status: GOOD ( 19.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose etm4_get_access_type() calculates the exception level bits for use in address comparator registers. This is also used by the TRCVICTLR register by shifting to the required position. This patch cleans up the logic to make etm4_get_access_type() calculate a generic mask which can be used by all users by shifting to their field. No functional changes intended. Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-17-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 47 +++++++++---------- .../coresight/coresight-etm4x-sysfs.c | 12 ++--- drivers/hwtracing/coresight/coresight-etm4x.h | 47 ++++++++++++------- 3 files changed, 60 insertions(+), 46 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index d91b259a4334..c9fcb17968a0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -959,20 +959,16 @@ static void etm4_init_arch_data(void *info) etm4_cs_lock(drvdata, csa); } +static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config) +{ + return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT; +} + /* Set ELx trace filter access in the TRCVICTLR register */ static void etm4_set_victlr_access(struct etmv4_config *config) { - u64 access_type; - - config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK | ETM_EXLEVEL_NS_VICTLR_MASK); - - /* - * TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering - * bits in vinst_ctrl, same bit pattern as TRCACATRn values returned by - * etm4_get_access_type() but with a relative shift in this register. - */ - access_type = etm4_get_access_type(config) << ETM_EXLEVEL_LSHIFT_TRCVICTLR; - config->vinst_ctrl |= (u32)access_type; + config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK; + config->vinst_ctrl |= etm4_get_victlr_access_type(config); } static void etm4_set_default_config(struct etmv4_config *config) @@ -1002,12 +998,9 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) u64 access_type = 0; /* - * EXLEVEL_NS, bits[15:12] - * The Exception levels are: - * Bit[12] Exception level 0 - Application - * Bit[13] Exception level 1 - OS - * Bit[14] Exception level 2 - Hypervisor - * Bit[15] Never implemented + * EXLEVEL_NS, for NonSecure Exception levels. + * The mask here is a generic value and must be + * shifted to the corresponding field for the registers */ if (!is_kernel_in_hyp_mode()) { /* Stay away from hypervisor mode for non-VHE */ @@ -1024,20 +1017,26 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) return access_type; } +/* + * Construct the exception level masks for a given config. + * This must be shifted to the corresponding register field + * for usage. + */ static u64 etm4_get_access_type(struct etmv4_config *config) { - u64 access_type = etm4_get_ns_access_type(config); - - /* All supported secure ELs are excluded */ - access_type |= (u64)config->s_ex_level << TRCACATR_EXLEVEL_SHIFT; + /* All Secure exception levels are excluded from the trace */ + return etm4_get_ns_access_type(config) | (u64)config->s_ex_level; +} - return access_type; +static u64 etm4_get_comparator_access_type(struct etmv4_config *config) +{ + return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT; } static void etm4_set_comparator_filter(struct etmv4_config *config, u64 start, u64 stop, int comparator) { - u64 access_type = etm4_get_access_type(config); + u64 access_type = etm4_get_comparator_access_type(config); /* First half of default address comparator */ config->addr_val[comparator] = start; @@ -1072,7 +1071,7 @@ static void etm4_set_start_stop_filter(struct etmv4_config *config, enum etm_addr_type type) { int shift; - u64 access_type = etm4_get_access_type(config); + u64 access_type = etm4_get_comparator_access_type(config); /* Configure the comparator */ config->addr_val[comparator] = address; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index e8fdda45ffca..45aeeac2f50e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -743,7 +743,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev, struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; - val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16; + val = (config->vinst_ctrl & TRCVICTLR_EXLEVEL_S_MASK) >> TRCVICTLR_EXLEVEL_S_SHIFT; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -760,10 +760,10 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, spin_lock(&drvdata->spinlock); /* clear all EXLEVEL_S bits */ - config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK); + config->vinst_ctrl &= ~(TRCVICTLR_EXLEVEL_S_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->s_ex_level; - config->vinst_ctrl |= (val << 16); + config->vinst_ctrl |= (val << TRCVICTLR_EXLEVEL_S_SHIFT); spin_unlock(&drvdata->spinlock); return size; } @@ -778,7 +778,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev, struct etmv4_config *config = &drvdata->config; /* EXLEVEL_NS, bits[23:20] */ - val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20; + val = (config->vinst_ctrl & TRCVICTLR_EXLEVEL_NS_MASK) >> TRCVICTLR_EXLEVEL_NS_SHIFT; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -795,10 +795,10 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, spin_lock(&drvdata->spinlock); /* clear EXLEVEL_NS bits */ - config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK); + config->vinst_ctrl &= ~(TRCVICTLR_EXLEVEL_NS_MASK); /* enable instruction tracing for corresponding exception level */ val &= drvdata->ns_ex_level; - config->vinst_ctrl |= (val << 20); + config->vinst_ctrl |= (val << TRCVICTLR_EXLEVEL_NS_SHIFT); spin_unlock(&drvdata->spinlock); return size; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 29cd27f53e72..91b82002e260 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -559,24 +559,39 @@ #define TRCACATR_EXLEVEL_SHIFT 8 -/* secure state access levels - TRCACATRn */ -#define ETM_EXLEVEL_S_APP BIT(8) -#define ETM_EXLEVEL_S_OS BIT(9) -#define ETM_EXLEVEL_S_HYP BIT(10) -#define ETM_EXLEVEL_S_MON BIT(11) -/* non-secure state access levels - TRCACATRn */ -#define ETM_EXLEVEL_NS_APP BIT(12) -#define ETM_EXLEVEL_NS_OS BIT(13) -#define ETM_EXLEVEL_NS_HYP BIT(14) -#define ETM_EXLEVEL_NS_NA BIT(15) - -/* access level control in TRCVICTLR - same bits as TRCACATRn but shifted */ -#define ETM_EXLEVEL_LSHIFT_TRCVICTLR 8 +/* + * Exception level mask for Secure and Non-Secure ELs. + * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn). + * The Secure and Non-Secure ELs are always to gether. + * Non-secure EL3 is never implemented. + * We use the following generic mask as they appear in different + * registers and this can be shifted for the appropriate + * fields. + */ +#define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */ +#define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */ +#define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */ +#define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Monitor */ +#define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */ +#define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */ +#define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */ + +#define ETM_EXLEVEL_MASK (GENMASK(6, 0)) +#define ETM_EXLEVEL_S_MASK (GENMASK(3, 0)) +#define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4)) + +/* access level controls in TRCACATRn */ +#define TRCACATR_EXLEVEL_SHIFT 8 + +/* access level control in TRCVICTLR */ +#define TRCVICTLR_EXLEVEL_SHIFT 16 +#define TRCVICTLR_EXLEVEL_S_SHIFT 16 +#define TRCVICTLR_EXLEVEL_NS_SHIFT 20 /* secure / non secure masks - TRCVICTLR, IDR3 */ -#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16) -/* NS MON (EL3) mode never implemented */ -#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20) +#define TRCVICTLR_EXLEVEL_MASK (ETM_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHIFT) +#define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT) +#define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT) /* Interpretation of resource numbers change at ETM v4.3 architecture */ #define ETM4X_ARCH_4V3 0x43 From patchwork Mon Feb 1 18:13:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F33BC433E0 for ; Mon, 1 Feb 2021 18:21:05 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B21B664EA0 for ; Mon, 1 Feb 2021 18:21:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B21B664EA0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FLedvosBeegj2xBA53K8djEN49celYcvkim9H5ENwmg=; b=B0c83GsljEUNMOJtb7VnZ32Jb wM7nH4E6SvyBHNe2kON3N1Z3sdu+RWjEhaxmx2OTM7ti/oDZahtT56vMNCL+PtlJE5luBjK7jmjyZ P2SivB8M1n5susqLdxgBBn1QRekDLBxqFQCfFP3NxjPsCjDCnzZf9uFfO678Wdc0Kd9RIY2kCnPe3 RqFEE0MT2XCRF/0l4T3hAgAUoId+w9kY00LOzKuCfAdN+h3mQY7GFf303r2hvxCoapZKTLtLET5Mw jzh09CV2woFBpIrFkewc3AESCHtnddRAqRXeBdIoUXJ84un/Zr+UwE/K7cOe0C4vpkwgeXxKc96cF wi71AdM1A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dmY-0005T5-Jc; Mon, 01 Feb 2021 18:18:38 +0000 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diK-00035M-EW for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:32 +0000 Received: by mail-pf1-x42f.google.com with SMTP id b145so5349079pfb.4 for ; Mon, 01 Feb 2021 10:14:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rMKTiBBzzA6qqd/h2MGcj7qPjB9ZbPsUF9hLa2otpO8=; b=mr3uuV5hq02GXn/RPIeayLViAvbTjtyxGnZZ/uAvii+zw7bOaztYkzXjVLHUAp2JmA queFWoAtMlomRlZdDFh1RMeYdgSgf/iv7fY2tZx7Pmb9GYW16+ErcAkk3JklVKKlYXsM tcJtp+YGuxPYtwYHgU8IlmtrAo5hSGZ2puppL43mtLUKI6VbM4Sf5InRyuJWqB76rWR2 EZvlTMuFrPgSrvn+hux3V13Heug9PG9U6Xl4pmf+MFm7qp3T8PMUYjBZVhJfX2yQPlPz rWvDDQyxo4U5MvxbpBREmEwVSonuiNKapJVByaPZ8BkdqDpOcoB8gGw7fDyq3V+L4Z3C 8frQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rMKTiBBzzA6qqd/h2MGcj7qPjB9ZbPsUF9hLa2otpO8=; b=jN1C+6kcMo5wvKKSyronCKfcP8s63zegvMoODV5S0PR/M6GMejC9jLgdvlSEeS2gB8 N6Y9RDcXna2gWEnZ5TAYNDefXC0W0hsEXMJQlCplNKiVMVJKzkvFm5Rr6P3R7DgF6XYz oEYyZCacY22VfaUfxOaoeDYzTs2yunKIKFFfWanyL6/pcDsaBOImxewcEvrZmtEvpCiU IFkP8jgUAJj5v1v/bP9c1WZjLFuihDx+9m5RCnAcRvRhKwMoL2msiW59oKRl5iCD8xRn Gyemt8Hs+MY3x6IJUtueb0y5RKF77dcyz1bpw0aWwKXhL01ghAiRsiTkhUeAOmKh9eJz a+vg== X-Gm-Message-State: AOAM530nDVauklwdNVTteB/J3GM/v7Mg04yC26x7ZUzdTIjJYgMmUUHA D2g7jJ4oww79G3r7S2iTb8tJ9w== X-Google-Smtp-Source: ABdhPJwOPo5tfyma8mXYuGivv4WlttJYWqemAQYnXdNmqQkNL/cR6iuq+N+XVj6NW833ivuaSD6rCA== X-Received: by 2002:a62:75c1:0:b029:1b6:b71a:a369 with SMTP id q184-20020a6275c10000b02901b6b71aa369mr17568835pfc.27.1612203254038; Mon, 01 Feb 2021 10:14:14 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:13 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 19/31] coresight: etm4x: Handle ETM architecture version Date: Mon, 1 Feb 2021 11:13:39 -0700 Message-Id: <20210201181351.1475223-20-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131416_555741_F699C585 X-CRM114-Status: GOOD ( 18.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose We are about to rely on TRCDEVARCH for detecting the ETM and its architecture version, falling back to TRCIDR1 if the former is not implemented (in older broken implementations). Also, we use the architecture version information to make some decisions. Streamline the architecture version handling by adding helpers. Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-18-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x.h | 60 ++++++++++++++++++- 2 files changed, 58 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index c9fcb17968a0..59da9efae9c2 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -917,7 +917,7 @@ static void etm4_init_arch_data(void *info) * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. */ drvdata->nr_resource = BMVAL(etmidr4, 16, 19); - if ((drvdata->arch < ETM4X_ARCH_4V3) || (drvdata->nr_resource > 0)) + if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0)) drvdata->nr_resource += 1; /* * NUMSSCC, bits[23:20] the number of single-shot diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 91b82002e260..0af60571aa23 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -468,7 +468,6 @@ #define ETM_MAX_RES_SEL 32 #define ETM_MAX_SS_CMP 8 -#define ETM_ARCH_V4 0x40 #define ETMv4_SYNC_MASK 0x1F #define ETM_CYC_THRESHOLD_MASK 0xFFF #define ETM_CYC_THRESHOLD_DEFAULT 0x100 @@ -593,8 +592,63 @@ #define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT) #define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT) +#define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8 +#define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT) +#define ETM_TRCIDR1_ARCH_MAJOR(x) \ + (((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT) +#define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4 +#define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT) +#define ETM_TRCIDR1_ARCH_MINOR(x) \ + (((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT) +#define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT +#define ETM_TRCIDR1_ARCH_MASK \ + (ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK) + +#define ETM_TRCIDR1_ARCH_ETMv4 0x4 + +/* + * Driver representation of the ETM architecture. + * The version of an ETM component can be detected from + * + * TRCDEVARCH - CoreSight architected register + * - Bits[15:12] - Major version + * - Bits[19:16] - Minor version + * TRCIDR1 - ETM architected register + * - Bits[11:8] - Major version + * - Bits[7:4] - Minor version + * We must rely on TRCDEVARCH for the version information, + * however we don't want to break the support for potential + * old implementations which might not implement it. Thus + * we fall back to TRCIDR1 if TRCDEVARCH is not implemented + * for memory mapped components. + * Now to make certain decisions easier based on the version + * we use an internal representation of the version in the + * driver, as follows : + * + * ETM_ARCH_VERSION[7:0], where : + * Bits[7:4] - Major version + * Bits[3:0] - Minro version + */ +#define ETM_ARCH_VERSION(major, minor) \ + ((((major) & 0xfU) << 4) | (((minor) & 0xfU))) +#define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU) +#define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU) + +#define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0) /* Interpretation of resource numbers change at ETM v4.3 architecture */ -#define ETM4X_ARCH_4V3 0x43 +#define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3) + +static inline u8 etm_devarch_to_arch(u32 devarch) +{ + return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch), + ETM_DEVARCH_REVISION(devarch)); +} + +static inline u8 etm_trcidr_to_arch(u32 trcidr1) +{ + return ETM_ARCH_VERSION(ETM_TRCIDR1_ARCH_MAJOR(trcidr1), + ETM_TRCIDR1_ARCH_MINOR(trcidr1)); +} enum etm_impdef_type { ETM4_IMPDEF_HISI_CORE_COMMIT, @@ -761,7 +815,7 @@ struct etmv4_save_state { * @spinlock: Only one at a time pls. * @mode: This tracer's mode, i.e sysFS, Perf or disabled. * @cpu: The cpu this component is affined to. - * @arch: ETM version number. + * @arch: ETM architecture version. * @nr_pe: The number of processing entity available for tracing. * @nr_pe_cmp: The number of processing entity comparator inputs that are * available for tracing. From patchwork Mon Feb 1 18:13:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72CF4C433E0 for ; Mon, 1 Feb 2021 18:20:48 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C702E64DE1 for ; Mon, 1 Feb 2021 18:20:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C702E64DE1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=hGbNZjOcIY6+gpawv8LE84uvakXTZI8iDPGuYVn5PQE=; b=XYesS3vwzwyMgTD2DbKBOKB0b jACKcUdXclMpEaOslmQCIo7lMKBnc9dG9uwkFzPWw0l/4/7NedrP0sYP4wMvU1QeRRomNdcNpPu4L bTCwTceg31eqCTbchhl57WYuzhhC8+W08oXmEPGHE9pY/kyNQABDYrzblCoTUBd5GlNHxm3M9/o1p gmBHsucT7ypWQpIWVOQ4RyoMzgJcKSuFzcCMNhlQLIFo+eWafuKnMEbBovtnOC0Bs9OiHcNg2figg /JzK0NgLqDS9WPkU5J2XdddQeaUBDSdzsySzEq/C8uqUpCBKdUm0B1A6y5NA4PtoSwY2Y0pQM2pGj PnVS4JUYQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dmM-0005KF-91; Mon, 01 Feb 2021 18:18:27 +0000 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diL-00036I-4X for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:32 +0000 Received: by mail-pj1-x1035.google.com with SMTP id z9so72660pjl.5 for ; Mon, 01 Feb 2021 10:14:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MZ0qc4FQm15rLxsjsyvmy33IGQ5QIQNw22305IvB1H4=; b=OF9Ql11LG+gDLcy/2U6/rozE5uggjn0RcpCYJSBEDxPryxGcJJEYj5JifZQb530/dv tzlLLR8ZXbU5vcJDK9k+o4XwJjsbq+5orcGSH/CbeXB0lb9MNY/q2ashSbGlC0RjvT8N 5PeFWqDHabeMVfPiZjeWDNB8rBaWJSzulFMIxwVOkOuEQqOv9Wa20EOE7nJNW06nWcN1 dCcoSCGh7sfbG8Yo53wUBf82d3PCJli0743wnekcgdiJLqas3uXARkoRGiX/9UfJMK+Z cHY9rgdYFcw32iyrjXHce5HpxS3MlMSi+97MVpj4X+85gFgRlrfquTiTsoW0LxYtF95W CxFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MZ0qc4FQm15rLxsjsyvmy33IGQ5QIQNw22305IvB1H4=; b=EPQLk9wMgwHdvDtxt4YZZSkErWUWvhzVOyH88wOdba50r0KN33GYa7FfeONoBBd2o5 SmGDCOFZefMN5EuXP1XH8zabcyMIRrHrrcQIe+J2Tu51Hyz+ysSRdygL0bwxqHQH4yJl WhZZgO0vvfD9uJvM370iyLiOfIXal9LMkM5j0me2m/Wed/34UhfYOiw7V5OnUuoL1LNn j6v0426Hoieo69DG07X6Rb+n0V6MAC9RKO6KmbWMvqa5AJAaAS9RsVt9gnFMlHUpJ3/n 0xAo0lOswIszWHXqEmo9a1w/Swk9NBjJun8sfWE/OxwgHHVp6w74d8IKfh84XT+D7IS5 BxjA== X-Gm-Message-State: AOAM532jntEwYm2WpjQZs+FT9RiIzpAqX6ln7sVQ3l0VaXMQAjNawr+z ISzp47sXHr1fhXjevSWDUxxcNw== X-Google-Smtp-Source: ABdhPJydriz8XQSVP4xtpVuwejzTBocd5o9fD1om/EzM/gOK3gKA30RbAcaNlT4sdox1xT/COCfh8w== X-Received: by 2002:a17:90a:d912:: with SMTP id c18mr151485pjv.102.1612203255251; Mon, 01 Feb 2021 10:14:15 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:14 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 20/31] coresight: etm4x: Detect access early on the target CPU Date: Mon, 1 Feb 2021 11:13:40 -0700 Message-Id: <20210201181351.1475223-21-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131418_081528_909F8E72 X-CRM114-Status: GOOD ( 18.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose In preparation to detect the support for system instruction support, move the detection of the device access to the target CPU. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-19-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 45 ++++++++++++++++--- 1 file changed, 40 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 59da9efae9c2..bfe3b8224d9a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -59,6 +59,11 @@ static u64 etm4_get_access_type(struct etmv4_config *config); static enum cpuhp_state hp_online; +struct etm4_init_arg { + struct etmv4_drvdata *drvdata; + struct csdev_access *csa; +}; + /* * Check if TRCSSPCICRn(i) is implemented for a given instance. * @@ -776,6 +781,22 @@ static const struct coresight_ops etm4_cs_ops = { .source_ops = &etm4_source_ops, }; +static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + *csa = CSDEV_ACCESS_IOMEM(drvdata->base); + return true; +} + +static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + if (drvdata->base) + return etm4_init_iomem_access(drvdata, csa); + + return false; +} + static void etm4_init_arch_data(void *info) { u32 etmidr0; @@ -784,11 +805,22 @@ static void etm4_init_arch_data(void *info) u32 etmidr3; u32 etmidr4; u32 etmidr5; - struct etmv4_drvdata *drvdata = info; - struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); - struct csdev_access *csa = &tmp_csa; + struct etm4_init_arg *init_arg = info; + struct etmv4_drvdata *drvdata; + struct csdev_access *csa; int i; + drvdata = init_arg->drvdata; + csa = init_arg->csa; + + /* + * If we are unable to detect the access mechanism, + * or unable to detect the trace unit type, fail + * early. + */ + if (!etm4_init_csdev_access(drvdata, csa)) + return; + /* Make sure all registers are accessible */ etm4_os_unlock_csa(drvdata, csa); etm4_cs_unlock(drvdata, csa); @@ -1634,6 +1666,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) struct etmv4_drvdata *drvdata; struct resource *res = &adev->res; struct coresight_desc desc = { 0 }; + struct etm4_init_arg init_arg = { 0 }; drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) @@ -1661,7 +1694,6 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) return PTR_ERR(base); drvdata->base = base; - desc.access = CSDEV_ACCESS_IOMEM(base); spin_lock_init(&drvdata->spinlock); @@ -1673,8 +1705,11 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) if (!desc.name) return -ENOMEM; + init_arg.drvdata = drvdata; + init_arg.csa = &desc.access; + if (smp_call_function_single(drvdata->cpu, - etm4_init_arch_data, drvdata, 1)) + etm4_init_arch_data, &init_arg, 1)) dev_err(dev, "ETM arch init failed\n"); if (etm4_arch_supported(drvdata->arch) == false) From patchwork Mon Feb 1 18:13:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A52F8C433DB for ; Mon, 1 Feb 2021 18:21:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6614260295 for ; Mon, 1 Feb 2021 18:21:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6614260295 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=L4mCjDsjHj9sR6GoE5ud2U6GQk2YMcLMZ8Yrvfx38tM=; b=SZbLerj0ZzmRCN7N7X3FbfAYe m3aKU0p+Je3Cv/Msvmb+DHu3zwdl5CJroP3/8I4ccqwiiG8MnarQVf6RIKj2nnwupaHOe5VMftE/I yD7h+LRMj/0fyp6jF+WgZAGhDqFdEydUxR3D8AgBRdZfyiLCibBIOBX0piF0+5hYf5LRoCa2CtBRh QAcNZzxpxDBJIwG+9lxABIKIC6z/dd5+ormOpsFEi8Wxq7j7n1MvZ9DFi50s6ZNtnAB//rW2W/7ue S7FZOkcXZF9WhJPTfBn6pnVZDmpI393sYJc73LibH3Jz1OdZVi0v+WzwAqRsLE/OgKD+SgoMXArXz 3+8a1lwkg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dnG-0005l8-KB; Mon, 01 Feb 2021 18:19:22 +0000 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diM-00036g-6G for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:34 +0000 Received: by mail-pg1-x529.google.com with SMTP id o63so12602060pgo.6 for ; Mon, 01 Feb 2021 10:14:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mulIk3ZrpE5FmYY+nWkpdZpOoqpgj1FNbaDnu2ujq+w=; b=nOI4G0Uy3JaK29ToCTHfujgSB2s+miEtNlNmpocpfe9bDEGt2+a/IRxBywLrEaPC1i rF/9zR5q2Uzc4xePqi/DmL+2M3xHnljczSmCG2PvBMJ7BzASHmgfh1fDCq1NFLwyYrwk 0OeZpYeaeVbWXp6rRjdjJcucQ5AzMyPNDrF8y2dLXveAzUyNYlkVAVyljgP8cCzYMz7k Ovt3FEHCTGz341HpzUTNyeQ6jt61tQ5mbl8qZ53k9A4e6rp2KhKKJnFQxkThzFqKnttR oW4CnVfagGotdPZx6VWpJJgHdvDMTqrOtipi3C2rM/Ua11DAuP8xhY3ordmfFpaQZJna IqYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mulIk3ZrpE5FmYY+nWkpdZpOoqpgj1FNbaDnu2ujq+w=; b=GkWZjL0YYl90pCSZ5plMHmpV2lNl8TLY07w/o7VHSBNGfadUqcUb0v5yosgoSbcuU2 o0nli0dNruqs81et9So9IshdBZMi9Dh6dR2nN0b0qCyKwyoh3NtP2Vfts22NrMSF8ZLP 15t2lSPokeGr+eLjgnDjCB1ILS3U0/tUw2UyUqNe2NJ8m9c3fOacl1EN+NzG88Qr6umq fiamxtgNXbYp38wGAstFCsmd9fg0C2SjTNFZDUdpva42yLV82rFkacIwh53VzhS1gNlq KXNJfEPv8Zty0s/6D7IeS2FmTyLM58uzjALrfT71Vp4+Knw6yACFp5iTBS/nwYxiGrHA j3HA== X-Gm-Message-State: AOAM532Mep8p75Q5BPualbojQdXruR8nnte/lJRwdlCRw0RifgbKIrgv PlU76mDksDqqxLKwFpevOKSNCg== X-Google-Smtp-Source: ABdhPJwMheySL7CbzlylXy2ujduMFE//Br4b0BODTt1GBMR8Gc4EROdsCa9qBvKyFP8PPUd9UFmnTA== X-Received: by 2002:a63:220b:: with SMTP id i11mr18245078pgi.2.1612203256188; Mon, 01 Feb 2021 10:14:16 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:15 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 21/31] coresight: etm4x: Use TRCDEVARCH for component discovery Date: Mon, 1 Feb 2021 11:13:41 -0700 Message-Id: <20210201181351.1475223-22-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131418_344265_0BAD20FD X-CRM114-Status: GOOD ( 17.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose We have been using TRCIDR1 for detecting the ETM version. This is in preparation for the future IP support. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-20-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 46 +++++++++---------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index bfe3b8224d9a..a09a653fc5b0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -153,18 +153,6 @@ static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, CS_UNLOCK(csa->base); } -static bool etm4_arch_supported(u8 arch) -{ - /* Mask out the minor version number */ - switch (arch & 0xf0) { - case ETM_ARCH_V4: - break; - default: - return false; - } - return true; -} - static int etm4_cpu_id(struct coresight_device *csdev) { struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -784,6 +772,26 @@ static const struct coresight_ops etm4_cs_ops = { static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { + u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH); + u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1); + + /* + * All ETMs must implement TRCDEVARCH to indicate that + * the component is an ETMv4. To support any broken + * implementations we fall back to TRCIDR1 check, which + * is not really reliable. + */ + if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) { + drvdata->arch = etm_devarch_to_arch(devarch); + } else { + pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n", + smp_processor_id(), devarch); + + if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4) + return false; + drvdata->arch = etm_trcidr_to_arch(idr1); + } + *csa = CSDEV_ACCESS_IOMEM(drvdata->base); return true; } @@ -800,7 +808,6 @@ static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata, static void etm4_init_arch_data(void *info) { u32 etmidr0; - u32 etmidr1; u32 etmidr2; u32 etmidr3; u32 etmidr4; @@ -865,14 +872,6 @@ static void etm4_init_arch_data(void *info) /* TSSIZE, bits[28:24] Global timestamp size field */ drvdata->ts_size = BMVAL(etmidr0, 24, 28); - /* base architecture of trace unit */ - etmidr1 = etm4x_relaxed_read32(csa, TRCIDR1); - /* - * TRCARCHMIN, bits[7:4] architecture the minor version number - * TRCARCHMAJ, bits[11:8] architecture major versin number - */ - drvdata->arch = BMVAL(etmidr1, 4, 11); - /* maximum size of resources */ etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); /* CIDSIZE, bits[9:5] Indicates the Context ID size */ @@ -1712,7 +1711,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) etm4_init_arch_data, &init_arg, 1)) dev_err(dev, "ETM arch init failed\n"); - if (etm4_arch_supported(drvdata->arch) == false) + if (!drvdata->arch) return -EINVAL; etm4_init_trace_id(drvdata); @@ -1744,7 +1743,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n", - drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf); + drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch), + ETM_ARCH_MINOR_VERSION(drvdata->arch)); if (boot_enable) { coresight_enable(drvdata->csdev); From patchwork Mon Feb 1 18:13:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42A01C433E0 for ; Mon, 1 Feb 2021 18:22:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CCEA860295 for ; Mon, 1 Feb 2021 18:22:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CCEA860295 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=WovmWqt4D3WR6z1rWCukx8ndjXFdSHm2dMjFAuGBAIo=; b=EMrHhytfD6ZrSxeryJYvHyJOW EzeLtQ8UqeDbi5qvrePFmz2eogjWCqCIuzCxAP+96VxeC7XeihTxFPVU+YhoMWyQSTMl6B25V69CZ KLZcVViSe+RICDP3rFyBIJkFS2UKbJCd66vu8nxAL9c6bKhsjX1pRDL6gshxIr096QwvEEFVaEjB/ v2obLUCLefS/7VxLBQPh+sRwyi9Dz8XLGF4djb60ZC/FFQJIo8WuVId16nWg/4Sg9aCAWPS+gpmcP /LUkkNtS//wpVTyjzCqIuQcRrQMLz7bdwMAmkYoFmPUouDieaM0CbtN7pZssrY3WWtKCzNqmm36Qt fZiHmxfIQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dnq-00061x-0Y; Mon, 01 Feb 2021 18:19:59 +0000 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diN-00036n-Kb for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:35 +0000 Received: by mail-pf1-x430.google.com with SMTP id w18so12133034pfu.9 for ; Mon, 01 Feb 2021 10:14:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oFuVLB0cXXkCbZq5RshAnDWx0pBkz/WKfxxkwoPXbjk=; b=nMPWMiXPJizdFscCnDFFH3UbjG1xkfRaIs1iiscPr/JRkNG6JChOvOXWD1SOqSlHW1 dHt/xwPCKLz0c8W4MuSx4e4dEpfFXdmpsLYcpk89MaTSH5uU6nFhhrBRWW4g9qSv9sXk URHVEteOG+Go5TWYNdctYs2kAbomqYXvidrJXeo4ac7EuKAVv61+/pg/GItv8ekuxw1E mM7mYu+x0NcQUxmOoD//zkrdYTDBysQTC4YPBrqVvXEjLcu0TLVSix6esovUcIMYWPd4 cRRJVZroTJqNjdbAQml9nayDLXEdE2AEZjhnFx13ZSfUu/qE1omsq3gv/FgMBAw8ZUAa G/Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oFuVLB0cXXkCbZq5RshAnDWx0pBkz/WKfxxkwoPXbjk=; b=ejV0DNwj1IKEQ+7oFVfc97RVXE7+wCw4UTDtu7QBX4T+mkICu/ADeufgcjDWMu0i4F R4u9upHw3TcM+1odk3PCJ31PkzufmZzQKTDN8EMyEivDVSnnvAC6lxQ3UlfryILKBBY2 0Y30JG6HBTyeoU49I4vB+AJwzJDZ0Pn+O5uda0XH04gdtgMqAkxDoNFxL3vLxGvu+ZLK TrR/oqNM1n95OpTU0ktwGRq0/IGzWke0OdqaX0J6P+GGnV/vNxxmuOepZ7dw0U6HB2If EHgokCpymFvnScPtBHVj7nKZFu3zHpVju7ElrcVkXYJEAgmWPMawXMnFitFHCXOy085Z e80A== X-Gm-Message-State: AOAM5303YVHBcUd5Jf5nPCyNycqG3tzkt1mWZDpN8u+tP0Bfw6Fr8BPc /ORuc6EiHR3DpduzJ41J8nMPAQ== X-Google-Smtp-Source: ABdhPJxWbngpziKVIIg6rRKNSMKpa4KZhltNrUD8MuKX12sY9N8c5ytWprHm2L/1B0AIlAZfnTrSpA== X-Received: by 2002:a63:5014:: with SMTP id e20mr18068896pgb.152.1612203257247; Mon, 01 Feb 2021 10:14:17 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:16 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 22/31] coresight: etm4x: Expose trcdevarch via sysfs Date: Mon, 1 Feb 2021 11:13:42 -0700 Message-Id: <20210201181351.1475223-23-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131419_863777_6A794759 X-CRM114-Status: GOOD ( 13.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose Expose the TRCDEVARCH register via the sysfs for component detection. Given that the TRCIDR1 may not completely identify the ETM component and instead need to use TRCDEVARCH, expose this via sysfs for tools to use it for identification. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-21-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 8 ++++++++ drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 1 + 2 files changed, 9 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 881f0cd99ce4..8e53a32f8150 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -371,6 +371,14 @@ Contact: Mathieu Poirier Description: (Read) Print the content of the Device ID Register (0xFC8). The value is taken directly from the HW. +What: /sys/bus/coresight/devices/etm/mgmt/trcdevarch +Date: January 2021 +KernelVersion: 5.12 +Contact: Mathieu Poirier +Description: (Read) Print the content of the Device Architecture Register + (offset 0xFBC). The value is taken directly read + from the HW. + What: /sys/bus/coresight/devices/etm/mgmt/trcdevtype Date: April 2015 KernelVersion: 4.01 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 45aeeac2f50e..b646d53a3133 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2442,6 +2442,7 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = { coresight_etm4x_reg(trcoslsr, TRCOSLSR), coresight_etm4x_reg(trcconfig, TRCCONFIGR), coresight_etm4x_reg(trctraceid, TRCTRACEIDR), + coresight_etm4x_reg(trcdevarch, TRCDEVARCH), NULL, }; From patchwork Mon Feb 1 18:13:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E3DAC433DB for ; Mon, 1 Feb 2021 18:24:28 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9F4CA60295 for ; Mon, 1 Feb 2021 18:24:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9F4CA60295 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=C286xUHkT6M3cawKJnmInOfzIfEZXmAC2mP+mn3OSeU=; b=KC2D5ZNZeZHUXJtkuG/OR3t8J ybuPLSRuM/WRAlclxaw/ax/NxrvknybC48odFStUfEtWUHy/odWPjwYe4mcefYlTo9dvRmrzUJdWB vAg5Qu8tIKgAv8T91+NTD0uXK9bZyjhTMNXNXE2LuakcRMp/NhVaTymeeB1hhHUWmPiMuA/l0GUUH MFw6vG8lJHtTtw/jUiHfoxJdBmIxjh6CYo5r5tPu0vsi8zVTxuld63RPa86vkImyVHLwZ74AsNuHw zh66xLduLJw7rZIfVgfB2uAkYYcgrPE/tMBNabUUUeO2IkZoifEki5bUmHz2GJhSliufhKCG63tAI EYinCJVFA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dpu-0006xp-GL; Mon, 01 Feb 2021 18:22:06 +0000 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diO-00037l-76 for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:36 +0000 Received: by mail-pj1-x1029.google.com with SMTP id z9so72751pjl.5 for ; Mon, 01 Feb 2021 10:14:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PjnieVeYjaiReOFmA2WdsBKbhVRjBxoMWJClMRBvNZk=; b=tzoyyo4fGQkr6c887iXZVOMnx+ryZvntzpwBoxoqDh8tatuq8RXyaV7wzrd4d2WY5R bY5mKC7WQvtS1LoCBUACkgDweBuGdyMvF3s4J1+OwPIuIvqIHKGd4/hJ2x8V/7eyltC6 qv2U+9cvs9L6r15jZjf5SmHK2o4yopin6LG+UdzX7Fk1vd7SqU+IUxsuxhBNJOer6Avh 7svfdF9bYqzlXOqAnbZdrePB9CX83/YTejPKi8a76CGixhVJRmugx5VaZ9efHCMa60qi PwgkQIVBtAiowjBOV9WFUxQoPwCe6CKXmEmHhmKexPMqxBpBP1gMlbwtwKA9uL6k3nd8 6I4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PjnieVeYjaiReOFmA2WdsBKbhVRjBxoMWJClMRBvNZk=; b=EV0xt4OaZcUBqs+zxGa9fdig4iHlZAkfteSJc4gw2KzeHeQ/vtU/N9Z4msQbmYVOCQ lHi5xvyE65dw9mAysjXGXdtQEgEBRPMZHeZQqkFaFR6Jx7uYLIjIzSkSkJOlcKiPFAtE ePwM9V/Bl9AzfkV7Xifg7tSVoHuCNuQfjf1O+Qh37QwaSlXpnLRFeTlFwd+zL7H7JgNY LbKq1Ik1k454k7zY+nLnchQfLDDO6SHD+AYP6QbolO+6381L2ATsnp0jOgasP9NzzYSh SqdAUThvkik0B6STe/xXdmVu87X5tXZ177ZoeU9qTp8jBUYcJ1go2pxVP6pZQAXRkTvn Xssw== X-Gm-Message-State: AOAM532LR6rqZSTEMDrJxM8E+ZbEGMrGrnIBAz5lucWo221Y1oO9d+US GLSFZOKVbInmcWYvHvu0svf5X+RsMjykMw== X-Google-Smtp-Source: ABdhPJx2K97OVJujZKHd1ou0m9ucAagyon1tPZtXb0yQuTNbNg1B2WTMRCdpSHs6WdMhECVA/ARwXQ== X-Received: by 2002:a17:90a:ba08:: with SMTP id s8mr143205pjr.112.1612203258318; Mon, 01 Feb 2021 10:14:18 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:17 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 23/31] coresight: etm4x: Add necessary synchronization for sysreg access Date: Mon, 1 Feb 2021 11:13:43 -0700 Message-Id: <20210201181351.1475223-24-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131420_457347_C6C8B3B1 X-CRM114-Status: GOOD ( 14.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose As per the specification any update to the TRCPRGCTLR must be synchronized by a context synchronization event (in our case an explicist ISB) before the TRCSTATR is checked. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-22-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index a09a653fc5b0..8d644e93de51 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -284,6 +284,15 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) /* Disable the trace unit before programming trace registers */ etm4x_relaxed_write32(csa, 0, TRCPRGCTLR); + /* + * If we use system instructions, we need to synchronize the + * write to the TRCPRGCTLR, before accessing the TRCSTATR. + * See ARM IHI0064F, section + * "4.3.7 Synchronization of register updates" + */ + if (!csa->io_mem) + isb(); + /* wait for TRCSTATR.IDLE to go up */ if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) dev_err(etm_dev, @@ -362,6 +371,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) /* Enable the trace unit */ etm4x_relaxed_write32(csa, 1, TRCPRGCTLR); + /* Synchronize the register updates for sysreg access */ + if (!csa->io_mem) + isb(); + /* wait for TRCSTATR.IDLE to go back down to '0' */ if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) dev_err(etm_dev, From patchwork Mon Feb 1 18:13:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04236C433E6 for ; Mon, 1 Feb 2021 18:23:47 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8EC6860295 for ; Mon, 1 Feb 2021 18:23:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8EC6860295 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=m2nh8m0KopxZZpickdUVHWLQxngU9PYYejwAjRlgA4Y=; b=b8g25gLFzgEnYUoJGZVvyI8+0 cr4rgPx+qB79be+X49o9aSIHGMWeNuZ3qKTywfIqGjoLsqoEF0Amx4Rn81vXgFHJBKI9jUhgfnL/r HgO5YVLpg2FC3TpyJpQCAGavROCwE96p6/4A0ZEBdNZqPiYOQbjIkZ6WmLM9rlTxbkcvBS9z4UrOA umja4z9AU70sTJb0TbHUkQ9TrLZwbM1pgkalbHPPSxslktKrXc0LmNx6l3OO+SFZPjOjV2FxkGSo+ R0BRowPyBSnm4Joye9pk4vWYBc4SUAm8kLNX0mSHmYfagnAI20lrZzfec4d+TQF5sz4BgzDxpgVIs P2+M8j81Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dos-0006TP-R0; Mon, 01 Feb 2021 18:21:03 +0000 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diP-00038B-Np for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:36 +0000 Received: by mail-pg1-x52d.google.com with SMTP id t25so12642981pga.2 for ; Mon, 01 Feb 2021 10:14:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wj97ynLU4juHaZmg3FI2nAyQleSP0VKWb4lYRditvLs=; b=lQwcqLvw8KMiYbtmguszA1QIr306Nxkib7LQWBdGOMDj7eWlz14SqyV1pUT1Ya1RzB VX7b0+KFRA7EXWdn1vvS58zfyXA05FFs85NFkrXR5GY1+mGrzA14T55PUOR8rdySSTM/ JO78TY+BsLxNuEiZMtBHTMyumeLv9r5T8KCvENFc2XryGPSjs9zdlfdw/bqhpcFtyJvu ewaRYbE+wBhA1iQs5lWYgHRhrZxZRfXKr7iEdbotiPQVLQ8SOat0dKBOfnRNzKxVCnjy XY+atthpVGUYXbubwSZg0y+v33KcFtztygvTTfsMZwqdkzXfGzWAekIcpGxcCCGfY5hn r+2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wj97ynLU4juHaZmg3FI2nAyQleSP0VKWb4lYRditvLs=; b=mgxcf5bjnb39fb1CAr3OxjEb8wPUTJSCL8p9Nd7wfUFT4kgCchS2tjJHwM6gHgRkCY 976xaISt3RLYoUFMDrs6agCmBdOC4FHcEDKMdDwJlstApoigi3GAAujMeozdFX+a+bWE JJ230aPkBLkpEckHL+96H6BsVkyErqnEGGXN1qrBC2PYerx7IS8j0aY5m+uN8+peCFGj CTSK8sXo5+P4qDQ/BhU9MB9fpAf908bEkqGkDHkjNu+lIl9kH1CDV++Jh2N0eyieSIFm lnrB+0rjtBLAHg2qTGx0vN2sxI3lw0WtnXWlNsGsVQTIKG7KYnnDs9xLt+v9EG7bOxXI m6OA== X-Gm-Message-State: AOAM533Fam4QBuPcQqu97fgHxSKMioGPdvs0YptObXiOBRlFDGhY5XPM k15SBGfHmzGpb8+B7z/Dn1jVng== X-Google-Smtp-Source: ABdhPJx4wBfHeCAFCUmp0yatV/dNTxTk13j+TKULV+UoEXjSRE2imXzytwXf0obfYEDeYMKHwPEX9A== X-Received: by 2002:a63:4764:: with SMTP id w36mr17732583pgk.127.1612203259415; Mon, 01 Feb 2021 10:14:19 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:18 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 24/31] coresight: etm4x: Detect system instructions support Date: Mon, 1 Feb 2021 11:13:44 -0700 Message-Id: <20210201181351.1475223-25-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131421_874567_BACD4812 X-CRM114-Status: GOOD ( 16.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose ETM v4.4 onwards adds support for system instruction access to the ETM. Detect the support on an ETM and switch to using the mode when available. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-23-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 8d644e93de51..48d8e99e31eb 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -782,6 +782,37 @@ static const struct coresight_ops etm4_cs_ops = { .source_ops = &etm4_source_ops, }; +static inline bool cpu_supports_sysreg_trace(void) +{ + u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); + + return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0; +} + +static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata, + struct csdev_access *csa) +{ + u32 devarch; + + if (!cpu_supports_sysreg_trace()) + return false; + + /* + * ETMs implementing sysreg access must implement TRCDEVARCH. + */ + devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH); + if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) + return false; + *csa = (struct csdev_access) { + .io_mem = false, + .read = etm4x_sysreg_read, + .write = etm4x_sysreg_write, + }; + + drvdata->arch = etm_devarch_to_arch(devarch); + return true; +} + static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { @@ -812,9 +843,17 @@ static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { + /* + * Always choose the memory mapped io, if there is + * a memory map to prevent sysreg access on broken + * systems. + */ if (drvdata->base) return etm4_init_iomem_access(drvdata, csa); + if (etm4_init_sysreg_access(drvdata, csa)) + return true; + return false; } From patchwork Mon Feb 1 18:13:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B781FC433E6 for ; Mon, 1 Feb 2021 18:18:38 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5420A64E50 for ; Mon, 1 Feb 2021 18:18:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5420A64E50 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=kLn7Frnb3KXBIVI15eI1F4oY4Cfd8CLAhQLuyIpXh2w=; b=UytIvmO2voaTT5jKokJbi1i9n 6cgONezr+vd/grrk7ImKqCR3Bwiz1XiOHo47vr//zY/6z83+D5yoPq2JWB6lW4maMubgDETjtqWTh IlYheyIlLHR9nX8gW75zoGsQp+Fe4jP/H63afRNI+4pQ0fE7pmviTpqGCJKlmi/u/RSXaU0ILDJhy 5vG7nJ0fDtwxVYgUUQLknJjsHvaTvjZ7GJCcTDYOSOiVbakEAmYNcm5rcts/QJ4+nY/gT2HtCU6Rn TFVEH8toXsWX42i3Z5JAfjy4X4/NJ+43yuAugRnkItw9p3P/OB+qnVQCDLEwkj/SIXwy7oYLgH8jY tzfU47M9A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dkd-0004KB-2c; Mon, 01 Feb 2021 18:16:39 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diX-0003CL-MK for linux-arm-kernel@merlin.infradead.org; Mon, 01 Feb 2021 18:14:29 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=PBNis2Le7mMZDVQZFpE5Weqxv7IPb4FFDDpAkRZVBuo=; b=Nfk9idLLEFqgcTYAFvc3s9F2Lj sA7N8dKzKvcUMr6CX/7vWA1rycIsNiqtbGYHBW5PWui8Em2b4OIbWVlW+GeQYHioXYyjEKXNhTfn5 XuVKyD16DB42AF73gfRBRupZaswST/sPh9X/ft+3arhhgduVNW8o3b7+sPV5a545EINpm94SmoVa7 WTxnx8TawtEKukjHD+79kxDfhNfoArFr80d+pDSNoY+libGM0GV4v+19HaX8//JrSsJQkwT9FDHQt iQsEHPNrI3bkzV853flzocLtIEyWFBNlOiR7G/RS37qO0C1NC56VSYKT40xiWBOLqCQPt5I7FKbX4 PpScQHkQ==; Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by casper.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1l6diS-00E8DH-4L for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:26 +0000 Received: by mail-pj1-x1034.google.com with SMTP id lw17so326566pjb.0 for ; Mon, 01 Feb 2021 10:14:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PBNis2Le7mMZDVQZFpE5Weqxv7IPb4FFDDpAkRZVBuo=; b=oGJdf3twifKKOxzMWTxbHs26h/jfYISQ7r0dqOxkpJHd2XrT3wAyyea0/RKuT7ghdA RPcqX24YF6x69/+aMYjktfs4dwXDXgswZPfMFPNvgFlYeIM/LCZaZ/peMYll/Z+Wxz3H rHhKDeLLs3voRJdSjeytXDcFPoZbniDG1bywZMcp2h7/HJfR5ekwiiPYjW+JH16zyw1l Vv1BxiUt0iV66TLE8arp+7EFntLwckLCpuNlod7H807liZGiT9AatoWXoQL18k/Rhhu4 xR58q4OkUXRqdlZwNk8PIhduapiX/CKV5vJPMqdolTYmm7Nxft9xIuUsFM/9mwXfO4Zj R32w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PBNis2Le7mMZDVQZFpE5Weqxv7IPb4FFDDpAkRZVBuo=; b=ab/wnSiuIcFqRyzYvqtXQZKHE3tga/ZY0GNNUr4v9MBMmAANSCthitqXZXgn3tBFX+ 7kMKwPlTIqJA5S1bbTkBBm5Tzuf4JTSyk+jWyHt8RUt4F8GVnX1TJs2YlVMKyA8kTwzC 9eCBi9dgbynNJdNo4HRnyBbUF9vyopUzWyiqGzbRhwzcPXEISyWv9sjR1hh+cmXQ11/I lBRp6oWInXGN/V4a93Y8YHVI8SAhSY3EOsz6OQ+VsrNiRq6TlyY3mbPb822lG2hXQWRn nB6B71OzpDIb2ne75X8JV0g+rrBdPZCea8E/ZRQhoayecsTyFYeXkz8GqcPW3/BUlrcj uVAg== X-Gm-Message-State: AOAM5334pDGOf2HNeZNiPq7FVFujkOqQIAp1sBm/la8h3X9j/zSH+p5B A11F+RjUPN9WONJy15UOZSlPTQ== X-Google-Smtp-Source: ABdhPJypa4yLATjeTzQd8p2ebrRP6WZKQ97kLu31Gwa7amDvHqhCSbOxnwQ6dXzcieuiqVBhDe0Odw== X-Received: by 2002:a17:90a:df15:: with SMTP id gp21mr118981pjb.63.1612203260425; Mon, 01 Feb 2021 10:14:20 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:19 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 25/31] coresight: etm4x: Refactor probing routine Date: Mon, 1 Feb 2021 11:13:45 -0700 Message-Id: <20210201181351.1475223-26-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_181426_789972_D5E98054 X-CRM114-Status: GOOD ( 19.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose CoreSight ETM with system register access may not have a memory mapped i/o access. Refactor the ETM specific probing into a common routine to allow reusing the code for such ETMs. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-24-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 62 ++++++++++++------- 1 file changed, 39 insertions(+), 23 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 48d8e99e31eb..c3e458af618a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1708,14 +1708,11 @@ static void etm4_pm_clear(void) } } -static int etm4_probe(struct amba_device *adev, const struct amba_id *id) +static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) { int ret; - void __iomem *base; - struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; struct etmv4_drvdata *drvdata; - struct resource *res = &adev->res; struct coresight_desc desc = { 0 }; struct etm4_init_arg init_arg = { 0 }; @@ -1739,11 +1736,6 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) drvdata->skip_power_up = true; - /* Validity for the resource is already checked by the AMBA core */ - base = devm_ioremap_resource(dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - drvdata->base = base; spin_lock_init(&drvdata->spinlock); @@ -1773,7 +1765,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) if (IS_ERR(pdata)) return PTR_ERR(pdata); - adev->dev.platform_data = pdata; + dev->platform_data = pdata; desc.type = CORESIGHT_DEV_TYPE_SOURCE; desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; @@ -1793,7 +1785,6 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) etmdrvdata[drvdata->cpu] = drvdata; - pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n", drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch), ETM_ARCH_MINOR_VERSION(drvdata->arch)); @@ -1803,11 +1794,30 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) drvdata->boot_enable = true; } - etm4_check_arch_features(drvdata, id->id); + etm4_check_arch_features(drvdata, etm_pid); return 0; } +static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) +{ + void __iomem *base; + struct device *dev = &adev->dev; + struct resource *res = &adev->res; + int ret; + + /* Validity for the resource is already checked by the AMBA core */ + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + ret = etm4_probe(dev, base, id->id); + if (!ret) + pm_runtime_put(&adev->dev); + + return ret; +} + static struct amba_cs_uci_id uci_id_etm4[] = { { /* ETMv4 UCI data */ @@ -1824,15 +1834,12 @@ static void clear_etmdrvdata(void *info) etmdrvdata[cpu] = NULL; } -static int etm4_remove(struct amba_device *adev) +static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) { - struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev); - etm_perf_symlink(drvdata->csdev, false); - /* - * Taking hotplug lock here to avoid racing between etm4_remove and - * CPU hotplug call backs. + * Taking hotplug lock here to avoid racing between etm4_remove_dev() + * and CPU hotplug call backs. */ cpus_read_lock(); /* @@ -1851,6 +1858,15 @@ static int etm4_remove(struct amba_device *adev) return 0; } +static int __exit etm4_remove_amba(struct amba_device *adev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + if (drvdata) + return etm4_remove_dev(drvdata); + return 0; +} + static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */ CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ @@ -1874,14 +1890,14 @@ static const struct amba_id etm4_ids[] = { MODULE_DEVICE_TABLE(amba, etm4_ids); -static struct amba_driver etm4x_driver = { +static struct amba_driver etm4x_amba_driver = { .drv = { .name = "coresight-etm4x", .owner = THIS_MODULE, .suppress_bind_attrs = true, }, - .probe = etm4_probe, - .remove = etm4_remove, + .probe = etm4_probe_amba, + .remove = etm4_remove_amba, .id_table = etm4_ids, }; @@ -1895,7 +1911,7 @@ static int __init etm4x_init(void) if (ret) return ret; - ret = amba_driver_register(&etm4x_driver); + ret = amba_driver_register(&etm4x_amba_driver); if (ret) { pr_err("Error registering etm4x driver\n"); etm4_pm_clear(); @@ -1906,7 +1922,7 @@ static int __init etm4x_init(void) static void __exit etm4x_exit(void) { - amba_driver_unregister(&etm4x_driver); + amba_driver_unregister(&etm4x_amba_driver); etm4_pm_clear(); } From patchwork Mon Feb 1 18:13:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D2D3C433DB for ; Mon, 1 Feb 2021 18:18:37 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2B16164DE1 for ; Mon, 1 Feb 2021 18:18:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2B16164DE1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6b57Y9jYBhcPdR4goUgI155JtEOIp57hBpbkvttVe/w=; b=zySZ0DU+/v1S9SkhYS1RfMpe5 ZJQjKWOGhiRPiZpcKtF3ZwCrcu88CqXRcAOYi2tr8lCuPftVtzY5isWyS1wQdj/32ZdZXQU677Qwg 5kwo3rjKKFxncAxPgLhzmXZHg1qjvY5JGMlgY297JU+mZpJ1tpxyzwGXWu+pNNWaX99RlWaRp2lJE tE/8HBpeMmJaZprnPDrAdwTIZmEDGjJINOI9P2z0V5WfCd0++m2jQvq9SLqSmLT6YG8h1WhAFE/mp IP5bwEmk/M3VA/WicROylvhGUXn6yODDCI8WhE3zcl+n5QrwtXuYL1JijHTcMNrFtATQ1U9cgS0Bb x1/uXmvoQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dkl-0004R1-AI; Mon, 01 Feb 2021 18:16:47 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diX-0003CU-MG for linux-arm-kernel@merlin.infradead.org; Mon, 01 Feb 2021 18:14:29 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=ujWQ8IDdSbwnxaXGdwQTjjikP4XSbHlkV7TpzfD9xCo=; b=oRDP1zbdHd1ZAU19txNTQIi5DI LkkAsLiqKnGpYKzhCCDBrcbTnj4Jv0R5MXeRMKykRXASZvblMRXjiDyLtZRTysQUsF1lCrYKCa4se EuAClLcP8whnSliYAxJ3tbYfMeYIroekr5/I0oXEEtTffFsZpzTt+dR/AqqcxyRNu/IoBZ+HX4YwU 7BCDBYiikBvGsx58/nL6x9dvqO0BWH2M6QjtnI4ymQz6n/alsgPXfeb1UatFiF3XAjDB1ryoVBgAj lRQQoZNwUCCQdNzxDURBq2C3A0dWPa10AXNI/W2xM1s66YsJOyxdp7PPSVDzBuVRi+s3NLdlrXObK 2rBJHRUg==; Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by casper.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1l6diU-00E8DI-KD for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:27 +0000 Received: by mail-pj1-x102c.google.com with SMTP id kx7so83934pjb.2 for ; Mon, 01 Feb 2021 10:14:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ujWQ8IDdSbwnxaXGdwQTjjikP4XSbHlkV7TpzfD9xCo=; b=QjzcqOoF+3AYpu6gKQF4yC3TQxBXrzL3mj0CT+BimMgQMbTp27c99IwABcp3t2sERt CatbW0kbH4brDMyfDaoidDWbeapQc8XtVxl1yCKP0dSf4OFqSmDP3oYIcxIEhh1CLoR6 mjpAncFt1MAtEDsTW26606Km/TyI1Ux8Rj6R99+VR1kH/REGOu8V7huYvyyff/njmT/V 11nkGTrXuaMGn5f5ciToOMU9nIgoA6aaQSTbkb3GlNL1uS9qcmHrpUGwdPQo9iN2v/Qp ctXRQgmECt5xAtl7XwduDl1hygEDbpj3eTzg+ecY+ttac3jsMunPl0sedhW9SaX+cze6 Bcag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ujWQ8IDdSbwnxaXGdwQTjjikP4XSbHlkV7TpzfD9xCo=; b=RyUEolPeGcwIvuyLOxvmvUr9CryCQMQsCjVBm4P0f3zbpjNanlJyzn5r269aZPTMKQ 53DgyU/MNi7IWjwaphXnOBo+N6qL2trPeboWuLT/AAKYqfWAekhQXPrIfHLH3kx/xz2N jf2/7NYs+XSSY2UhkZzy8UrQe/sQNDpUQdw8CcTwzaW595cjyJBlVrOxIrJsV85r0ypi PqGDTLZc92lVn5BdwhxFT6bnPBn8IlLaNqFsfcGC+jgkqyWyAzp/BaMx2ppo0XfCvpfK wIHjpAtQUhmX6ZUM++Mgcsc5SndHpp7Jc6BFmEZm55crZ1snBrDwFeUXZ8NqQwD4uT54 ygng== X-Gm-Message-State: AOAM532LVHvHq3FMxBrfIpCtSpthmm14h/DMNBKYslpim7vMw70uoiuV D+CBlojP4SBRWLftFB/xC7J13OWddATv3g== X-Google-Smtp-Source: ABdhPJz9ZOmrWeFX+5JZYxQzresYToTz+3Wh8DeKHMzMvM5i51L/SqeO+RvVteVTFPFKCqQV/5TpLA== X-Received: by 2002:a17:90a:f295:: with SMTP id fs21mr105601pjb.227.1612203261415; Mon, 01 Feb 2021 10:14:21 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:20 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 26/31] coresight: etm4x: Run arch feature detection on the CPU Date: Mon, 1 Feb 2021 11:13:46 -0700 Message-Id: <20210201181351.1475223-27-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_181427_270887_3A5F4032 X-CRM114-Status: GOOD ( 15.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose As we are about to add support for system register based devices, we don't get an AMBA pid. So, the detection code could check the system registers running on the CPU to check for the architecture specific features. Thus we move the arch feature detection to run on the CPU. We cannot always read the PID from the HW, as the PID could be overridden by DT for broken devices. So, use the PID from AMBA layer if available. Cc: Mathieu Poirier Cc: Mike Leach Cc: liuqi115@huawei.com Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-25-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index c3e458af618a..fc26ecbc2d87 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -60,6 +60,7 @@ static u64 etm4_get_access_type(struct etmv4_config *config); static enum cpuhp_state hp_online; struct etm4_init_arg { + unsigned int pid; struct etmv4_drvdata *drvdata; struct csdev_access *csa; }; @@ -884,6 +885,8 @@ static void etm4_init_arch_data(void *info) etm4_os_unlock_csa(drvdata, csa); etm4_cs_unlock(drvdata, csa); + etm4_check_arch_features(drvdata, init_arg->pid); + /* find all capabilities of the tracing unit */ etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); @@ -1750,6 +1753,7 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) init_arg.drvdata = drvdata; init_arg.csa = &desc.access; + init_arg.pid = etm_pid; if (smp_call_function_single(drvdata->cpu, etm4_init_arch_data, &init_arg, 1)) @@ -1794,8 +1798,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) drvdata->boot_enable = true; } - etm4_check_arch_features(drvdata, etm_pid); - return 0; } From patchwork Mon Feb 1 18:13:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12060261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A414C433DB for ; Mon, 1 Feb 2021 23:59:17 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D34DF64EDC for ; Mon, 1 Feb 2021 23:59:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D34DF64EDC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fgT3ABOHYsWChIvmaAUB4ph8ConWQwIv6hAwVd1JUjM=; b=h/8Dj6iBprR6FSU7ZJyCisPlc 9rk98YaSeTJwYQG7bK+SkJ3sdBnuEn18Qcy1kq4zfB8DNEL8xDhxpSgSI2Yor09B+rzVGAoL7Qrtj VH94y/Keli0B+bZELsfmKmvGex46arq1JBTCbFNzkfLP6Pc/p4VD7EJsPhrD5OI7FV0Z8uQWeJ+Hy GPrZdOd6e7yqp9otzHeJKZhCwW51qoBYuL757FFWA/wbb8ccCC+9wWowbLugc5P/lz0iNO6eoNoUE rk2+9djcZqvo5iIrDflyDW/C5kFCoiduYLlzy0myVA1I9VRFo3TrDiJrHJ+nDFrzIc9gRcKldS1Wf qxfaKBldA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dqW-0007DD-5I; Mon, 01 Feb 2021 18:22:45 +0000 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diS-0003A0-Ef for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:37 +0000 Received: by mail-pj1-x102d.google.com with SMTP id l18so81298pji.3 for ; Mon, 01 Feb 2021 10:14:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r6MZF2I+EtOQE1SlYRYLpgst5vG63s12bYpfROsNq20=; b=IjBy6Xq2lMnYRbP3Ejtc/LmkvMh2Sa8jSyuaoWtu9fcSvCcqKm0qp7nk2bcNawnQrz T/U70s2x+j51GKG54IsMh2yzO2gRYDGWJS+qyns0vvMTVT9BrpJl7eDSSCCr74PEiAfr swpE1OdZgudfL26fV0tOp32pzdvXqBHiCjlSCSP3Jc29tYdAlSmNG4ErxaBqmqjDxg8P m7csedHcUOe3oVM1h9g8nAEHgPv2StUwXklYGMLkZn0jntYzDqD/j7gy/EvRp4ZpEAMk RdJwLHKezgqvIhwE3K4KAWQhAJDXN9PpcgnT3Gs0CFIQqWhi6k5lYJLNFohgjUMFKK7X vMGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r6MZF2I+EtOQE1SlYRYLpgst5vG63s12bYpfROsNq20=; b=Fx5w9GLURbRiPfHKtFN4fOKOANtTncyHyvUxmZmiHjso5bp92ebABuOIS5XXsk4pGF JXflOGCXDG/nDU24wB7UXvXIOdTpY00URTFdz8WWDcq7M3KWm3g6cc54xxZJTAWyv8Qw hBIYK/zOI2oUMlQ9c8hWZq24r4HzAhqjOimuf5DossQyGqeQLoPgIh88uIX9z8pEQPNF J3TPKGIjYr/PQZV+FG7gLkgnFXgFZIx5BnnyE5n6UiaSHkSu8STVnN3twAB2O+zIZpd7 JqCdk+O8QaehkVC9yQZqvCr8K53P0u5Ew9JHLuCh7o+6pAkqePYFeC3vcVRnyG7yYIam kjeQ== X-Gm-Message-State: AOAM5313aEaV1CQR7HuUs5E/pytQQxjSPQXYSVRkl3F3cIBDv3z3veP3 HOdZjsxztH7SALSiM9AetQIavw== X-Google-Smtp-Source: ABdhPJyQScyV4qottp3h9tV17KkDMs4Qrdf8uhR12hijrNHwEevNIqNPuBNvQ5MmIR4bXeMzIcrg9w== X-Received: by 2002:a17:90a:5c81:: with SMTP id r1mr109235pji.175.1612203262477; Mon, 01 Feb 2021 10:14:22 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:21 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 27/31] coresight: etm4x: Add support for sysreg only devices Date: Mon, 1 Feb 2021 11:13:47 -0700 Message-Id: <20210201181351.1475223-28-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131424_680056_1B014866 X-CRM114-Status: GOOD ( 23.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose Add support for devices with system instruction access only. They don't have a memory mapped interface and thus are not AMBA devices. System register access is not permitted to TRCPDCR and thus skip access to them. Cc: Mike Leach Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-26-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 68 +++++++++++++++++-- 1 file changed, 63 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index fc26ecbc2d87..c6238e208685 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -1736,9 +1737,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) return -ENOMEM; } - if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) - drvdata->skip_power_up = true; - drvdata->base = base; spin_lock_init(&drvdata->spinlock); @@ -1762,6 +1760,11 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) if (!drvdata->arch) return -EINVAL; + /* TRCPDCR is not accessible with system instructions. */ + if (!desc.access.io_mem || + fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) + drvdata->skip_power_up = true; + etm4_init_trace_id(drvdata); etm4_set_default(&drvdata->config); @@ -1820,6 +1823,25 @@ static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) return ret; } +static int etm4_probe_platform_dev(struct platform_device *pdev) +{ + int ret; + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + /* + * System register based devices could match the + * HW by reading appropriate registers on the HW + * and thus we could skip the PID. + */ + ret = etm4_probe(&pdev->dev, NULL, 0); + + pm_runtime_put(&pdev->dev); + return ret; +} + static struct amba_cs_uci_id uci_id_etm4[] = { { /* ETMv4 UCI data */ @@ -1869,6 +1891,17 @@ static int __exit etm4_remove_amba(struct amba_device *adev) return 0; } +static int __exit etm4_remove_platform_dev(struct platform_device *pdev) +{ + int ret = 0; + struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev); + + if (drvdata) + ret = etm4_remove_dev(drvdata); + pm_runtime_disable(&pdev->dev); + return ret; +} + static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */ CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ @@ -1903,6 +1936,21 @@ static struct amba_driver etm4x_amba_driver = { .id_table = etm4_ids, }; +static const struct of_device_id etm4_sysreg_match[] = { + { .compatible = "arm,coresight-etm4x-sysreg" }, + {} +}; + +static struct platform_driver etm4_platform_driver = { + .probe = etm4_probe_platform_dev, + .remove = etm4_remove_platform_dev, + .driver = { + .name = "coresight-etm4x", + .of_match_table = etm4_sysreg_match, + .suppress_bind_attrs = true, + }, +}; + static int __init etm4x_init(void) { int ret; @@ -1915,16 +1963,26 @@ static int __init etm4x_init(void) ret = amba_driver_register(&etm4x_amba_driver); if (ret) { - pr_err("Error registering etm4x driver\n"); - etm4_pm_clear(); + pr_err("Error registering etm4x AMBA driver\n"); + goto clear_pm; } + ret = platform_driver_register(&etm4_platform_driver); + if (!ret) + return 0; + + pr_err("Error registering etm4x platform driver\n"); + amba_driver_unregister(&etm4x_amba_driver); + +clear_pm: + etm4_pm_clear(); return ret; } static void __exit etm4x_exit(void) { amba_driver_unregister(&etm4x_amba_driver); + platform_driver_unregister(&etm4_platform_driver); etm4_pm_clear(); } From patchwork Mon Feb 1 18:13:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67D2FC433DB for ; Mon, 1 Feb 2021 18:45:58 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2F82D64DDF for ; Mon, 1 Feb 2021 18:45:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2F82D64DDF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=j8+Rq4685shj8mh2l8uKb30ZMSrUkZA8hpH/xZthYb8=; b=n94z8QYOgYULkmG5IrR7j36co JOy9784UjaDOoF/Uq23U9GSrYCkGDz3xDmRM8crGMDxRjN9OWvSH9GAoXijbitaHxLb9aXSAtvqh4 fssiWb3PJm2yWWQeJt6VKwTmpLD7nXV5tyhFCbPULKyDuDNjrwJQS1fC/4SK+dRjdiW11sOItlWNo CZ+2eeqsfu9QvcEPfVBtOIu5/EQMJtx1NLR09bVMGubTYjJk1U2UY8YYu67xzaQWoUEd0ru32M5Xr cat0p2DEIXx7bKcvg++TU96zju0+orI0rlvgEkjPd+QXq5RuLyifwjborBaAYmPJdazS8ZoYPpBng FPKldiSyQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6drO-0007Wg-Hh; Mon, 01 Feb 2021 18:23:38 +0000 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diT-0003AM-P1 for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:38 +0000 Received: by mail-pj1-x102e.google.com with SMTP id z9so72890pjl.5 for ; Mon, 01 Feb 2021 10:14:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ud8fSYQS4d3P26sJXvIE1jVhQWMgH/q2+4y/hg0WOzE=; b=Bq142QzhKaao2VxJy5mJjbxcbYKOYG5x7RP7xQ/EzMs+IrSq4M4BKdnRAfy7zVyQX7 YhdJbF2EX6Z9GrI6l8RN9S2y/ZjZAcK4XcMIopxQwEehv66fWF6XkWVvCNJvU6RE15x3 Cv0tQJouHYxfo3TCIA+d1p4ecdlKCRKNYsRMhf9j1tvthHv40Au3FEw+W3fggZG5v+ly VuPhpCfLXhrMofcHTNjeVVIPHzyvWzmK0IeAxMKvpKLjme6Gtgk8/i+7vEuWQwZ0NgRF fAjHoltk0zn8SEDGxWppuL29JeOsR0VSDQ9UUl6hHh5ZuNCG14huFoCXoy+LApJrWWaV Xlog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ud8fSYQS4d3P26sJXvIE1jVhQWMgH/q2+4y/hg0WOzE=; b=lsbUaZtRSwhwzAhEbt5n8uro5WXUttI/DuGIDr7gts6g71Cw3vIDqOhs1/ynKbQuFT KZyGd9d81lCohIg8Rab47iyWrpmWBnzyfHWpxeYwkNTcRYxwGLil8kVXqaJ8gumo0MX6 Bq9LDp1Bxy/XfRr1f0IdJ23fODCvvOTLXbJeZte3rZ9Pm6X/LKwDbZ1orUj/9FzeqDqO qX+USsrABmKUMTPFOVJYXHQEq3bxlu/oU41DUqrZHFKsbUdUs+ogyai+Lkzdl5cP/fG5 b8nIdvs7FVt0GEOamxJxvYz3JsVAy2kMlY2lX6qJtuPArd5WXvVorB8r0G8vVFxAgjuX 6fBQ== X-Gm-Message-State: AOAM532uphlma/st1b7H+Hhrw1j+e2257t85nAz01Xf214+//aZXak3e Lj+B3v4fCW7UGgja3bD0leK1yQ== X-Google-Smtp-Source: ABdhPJwuhnxfgWa+/10wsinybLQICKg8hNRPHx1P5G+mblYZOUxwiPeN6OAd49yfOTnD4wB1ai1N7g== X-Received: by 2002:a17:90a:4890:: with SMTP id b16mr171042pjh.36.1612203263428; Mon, 01 Feb 2021 10:14:23 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:22 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 28/31] dts: bindings: coresight: ETM system register access only units Date: Mon, 1 Feb 2021 11:13:48 -0700 Message-Id: <20210201181351.1475223-29-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131425_925375_967430A9 X-CRM114-Status: GOOD ( 10.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose Document the bindings for ETMs with system register accesses. Cc: devicetree@vger.kernel.org Cc: Mathieu Poirier Cc: Mike Leach Acked-by: Rob Herring Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-27-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- Documentation/devicetree/bindings/arm/coresight.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index d711676b4a51..7f9c1ca87487 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -34,9 +34,12 @@ its hardware characteristcs. Program Flow Trace Macrocell: "arm,coresight-etm3x", "arm,primecell"; - - Embedded Trace Macrocell (version 4.x): + - Embedded Trace Macrocell (version 4.x), with memory mapped access. "arm,coresight-etm4x", "arm,primecell"; + - Embedded Trace Macrocell (version 4.x), with system register access only. + "arm,coresight-etm4x-sysreg"; + - Coresight programmable Replicator : "arm,coresight-dynamic-replicator", "arm,primecell"; From patchwork Mon Feb 1 18:13:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12060079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFBD0C433E0 for ; Mon, 1 Feb 2021 21:12:14 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4FED860232 for ; Mon, 1 Feb 2021 21:12:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4FED860232 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=YigJs0raoEClOvO5LkhuJXqqPYkBRdJ9tTi6odKQjGM=; b=w8g8sJk0Ro6IRuL/bSfR1u2ic KlTXiWYkOf30cAXwuC5GEza7VjC10jdXrONE4BHW7MmfFJ1MRw9suwGwyusQ9gKEUZI8HxzzhYDpX avEMzcBx6zfjf/AD7a+AcORHKtySVfu/AdG8PZrlMU6/If3NnxvVRu/Um0DOPw9n02efFQFJ1kL1H TuAA76YX9a44w0zwdWIQ4HK6Po+v1XI93VNvOE9MXr1KLq7PlUP8qTBsH7jO5A/JABvV/dw9stNX1 DoalH1g1/akFbmhWINI9sR6Gr4oASb1hS3NDAe6vdH1b/Rtt7howh/4TAWV2ZjpFFbKCNsgL8Ew0C rqA6Yy7tA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6drs-0007hh-To; Mon, 01 Feb 2021 18:24:09 +0000 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diU-0003Av-Ft for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:38 +0000 Received: by mail-pf1-x42f.google.com with SMTP id o20so12161506pfu.0 for ; Mon, 01 Feb 2021 10:14:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GFqKuZ77avnBtk4IXulMi5+rMq2IVk2aYxin4FMvrHc=; b=tNNaYYA/FAcx8YboDKjEYK/Wz/LrfjztgM5lacaRKXdWUchh2exQCqCnSGcd4pwP/J x883SkfZtJXTAa7Ums8VNSySNpP+avQLDWK3tE0isDG69mbmsZZ+cmBCJoFIGzye5kmI /dQYBzVFq4IaupP2yakuWg7qslDt7+4hGuvQ4LHzF4oxG6ge3jZqFo1oxW1e7YcQ/DOZ 4vz+iFW7DLx0JZwZwxaqj4dm0ucOirZNsXByPCWnqC3QQlvRBw1q1eOXPl+W895PJTxa l1ORRKEttD/18O0eoI7b2T0XqM2wTWlpjNreTQftgW5K2nVl6mlM8cwCecZNPo/bYgGs XHkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GFqKuZ77avnBtk4IXulMi5+rMq2IVk2aYxin4FMvrHc=; b=ofBl+WTLunqnPNi1mpwu1p6E3zld/3uXGSiyZnQYFpEIUihFVkG1EnsAB1kGdrkb9Q +go1i6+sykkqLRI9+2v+lMfnLsNldaLoqlhbgQvpTcV5an3pbIzyBSMECLtKiInD37YG O6nxNWLnTybp+GKiML0On9zsVQvxcXIIe1nIhrcJBXbIK745n1gOiDE95ysSSJuFMwNH NzdPxl3kuTECJe04K3iu0qaM7UlBFcnVe7ERB/vqfY/O8JGDdnKRWWouIsWe3YMiMooe Bzvb420CVJ3fpnhR0CDPRFyHG9dPIYJlNtrxdMcYnexZrhduACRZc5lOmPg8oddae7ly YPHA== X-Gm-Message-State: AOAM530iZbyViBRg04n6tNaYGub4xxzZnmYdSK+rSFRFQMe3LT7R7psX paXT3pjDjxhFlbm7oS6F88poHQ== X-Google-Smtp-Source: ABdhPJydvY3uPmmMFUTcp+l1QuiF/pjOU53aOlMUba7lcWpTTYa8bHT6ZxhKjX7IFLTet5G927uiKA== X-Received: by 2002:a65:498e:: with SMTP id r14mr18021647pgs.235.1612203264546; Mon, 01 Feb 2021 10:14:24 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:23 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 29/31] arm64: Add TRFCR_ELx definitions Date: Mon, 1 Feb 2021 11:13:49 -0700 Message-Id: <20210201181351.1475223-30-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_131426_659859_F68FBF00 X-CRM114-Status: GOOD ( 13.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jonathan Zhou Add definitions for the Arm v8.4 SelfHosted trace extensions registers. Acked-by: Catalin Marinas Cc: Will Deacon Signed-off-by: Jonathan Zhou [ split the register definitions to separate patch rename some of the symbols ] Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-28-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- arch/arm64/include/asm/sysreg.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 8b5e7e5c3cc8..4acff97519b9 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -191,6 +191,7 @@ #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) @@ -471,6 +472,7 @@ #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) +#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) @@ -829,6 +831,7 @@ #define ID_AA64MMFR2_CNP_SHIFT 0 /* id_aa64dfr0 */ +#define ID_AA64DFR0_TRACE_FILT_SHIFT 40 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 #define ID_AA64DFR0_PMSVER_SHIFT 32 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 @@ -1003,6 +1006,14 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) +#define TRFCR_ELx_TS_SHIFT 5 +#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) +#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) +#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) +#define TRFCR_EL2_CX BIT(3) +#define TRFCR_ELx_ExTRE BIT(1) +#define TRFCR_ELx_E0TRE BIT(0) + #ifdef __ASSEMBLY__ .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 From patchwork Mon Feb 1 18:13:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 392F1C433DB for ; Mon, 1 Feb 2021 18:19:44 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5F3564E50 for ; Mon, 1 Feb 2021 18:19:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D5F3564E50 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=kqYfo7AvRDJtvB9iv/hKE7TnXdbz4fGWrWdlGOwe73A=; b=Jhcuqd9dvJRKGcg3WKayISPmB d2VF7pyos+toWVjWkWt5X9ZNURZ9zwhmWfF4KDMcplJmWKSvbFyeJ1z+e2LBl4RpIElgKwzFkeuYT ymQ9+dG9+/J+UADA9/1XvP7hT+svqNOJPquD3BP6ap3VqtSAT4kNG9garnH4Pl7Fntxy3gvXRFAYx hfwV5rJcaUR9A6PUgKnIlRszqcv7KoGNbjRnUxYOytBWUbDmmt6EaSQeewbbU3/146HhSDlw5fXlt yQkVHmDpPWrRiq11KwxaAuTNBlJe38TgQ4chf3G3NhdBHKc9H7q/S2UQJI+BdxQlm6IaOtM1yfCc/ MJp6vaaAw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dlZ-0004rb-Gb; Mon, 01 Feb 2021 18:17:37 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6diY-0003D0-DK for linux-arm-kernel@merlin.infradead.org; Mon, 01 Feb 2021 18:14:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=UUTXKEyDoj2yYHV7VRlaeVtzyllZkVV0kWljFdybBQc=; b=FHom6d0ZTwMooSmvWqaKuhU1AO O7f80Z3X/WbFPN5eymacp3YonE7WPqTz05pxrwJyuccMj7Aff9Q1tVg144oDMPh85vgatHNlS86Sl B6SHaq9/tpCS93yA1nGHZ2XpKuta5xgv0ub7AlH0vbUSQfqWYVeN0J1Ds81RjhN49xvfep3t5crC1 bAp2f/RGGqlubGMxusc0sY3VOvMBza6LGwrLNov1oMq5V1nEbOl1YUPPYTUWGGoBJqPXdDW3Exrj0 HyUUErkyPts46W2rhAlxMp2BCQf5fTHMXzFVgbXZ+KkRvc7pqocikAG3lwyxqtXtnkQkfD+uJa/Ts eDDF6YuQ==; Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by casper.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1l6diV-00E8Dh-Rs for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:28 +0000 Received: by mail-pj1-x1032.google.com with SMTP id d2so76897pjs.4 for ; Mon, 01 Feb 2021 10:14:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UUTXKEyDoj2yYHV7VRlaeVtzyllZkVV0kWljFdybBQc=; b=opEvKWv5QoRwT30WTVzp5yrWzeuFQtpKLqPwN8Uyb+jH4PdqkIXmeagv0guR0tAaRp 5wdxYueQ+YTMW8fqWq8tWfxtdL1zH/MBesu0wlKxKEoIDDohAiJ0U3quFRHBYMXaSWUD px8hRCQAT+318iemlpV699CeudNUzgiMAvRU9f7RhAzx3gQ1cTCUm21zauI60nHw68Uj U4UPizNOJWPdmd11tDOT5WulZhz6Rdw6y3Z/YMkMD6UUpPN8iZTL3qGxRvr5ydRH5X7o hAwmdU0sWBeDlbsihAaODfX9iAJn9IImiYUf/60LG4znVAAGl37aXYVhhmqnOkp3voCw muGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UUTXKEyDoj2yYHV7VRlaeVtzyllZkVV0kWljFdybBQc=; b=CF0jIsSfdih7YGKPcfv+aRlqGQCAF2ayXNN1gws6KnHih9bBTsWe1H+e18C3gC+h0S j/9/VQT0RWmvbjwVEEfoPbfsxcf2KBHI9NtWHlZKfiyHS6eucepgIA/MohToZwDCDtgg Eu9YXxmAqiScgLNv7ebtz1h5kCh8vDWL1nQa+bGqI2RWa1uPuMn65uJu4OtS0PKhYsFR yG6v4zbQWE0GIxK9LIzJY9pROPJXp3Cbs9Qin5RmFWKGZ4LvENMLWI9ayeK0JYXURLxB 3hcoSdbFDDhPMnseh15GlCv4Y8TAcFDO5QO6+SwZE3DwSJCVHfFhbg8SlsNjFX4mm/RP M8ww== X-Gm-Message-State: AOAM532w8byyRff/iqeh1P95WEldweCBpNlYAaifzpG0fI/aW6Y7sorH pvOMPByF5IlwBGlE6XOp7ZZPmQ== X-Google-Smtp-Source: ABdhPJw/nAiZDK/T+Pgg2La1m2T8BiZb/t0a59Wp8Mcd+RaxYAaOlqp3bhxJDqV3tO8KAEN95i4sdA== X-Received: by 2002:a17:90a:8c13:: with SMTP id a19mr152090pjo.80.1612203265683; Mon, 01 Feb 2021 10:14:25 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:25 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 30/31] coresight: Add support for v8.4 SelfHosted tracing Date: Mon, 1 Feb 2021 11:13:50 -0700 Message-Id: <20210201181351.1475223-31-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_181428_352634_2EAB86BA X-CRM114-Status: GOOD ( 14.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jonathan Zhou v8.4 tracing extensions added support for trace filtering controlled by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2 tracing if we are running the kernel at EL2. Cc: Catalin Marinas Cc: Mike Leach Cc: Will Deacon Reviewed-by: Mathieu Poirier Signed-off-by: Jonathan Zhou [ Move the trace filtering setup etm_init_arch_data() and clean ups] Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210110224850.1880240-29-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- .../coresight/coresight-etm4x-core.c | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index c6238e208685..473ab7480a36 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -859,6 +859,30 @@ static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata, return false; } +static void cpu_enable_tracing(void) +{ + u64 dfr0 = read_sysreg(id_aa64dfr0_el1); + u64 trfcr; + + if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT)) + return; + + /* + * If the CPU supports v8.4 SelfHosted Tracing, enable + * tracing at the kernel EL and EL0, forcing to use the + * virtual time as the timestamp. + */ + trfcr = (TRFCR_ELx_TS_VIRTUAL | + TRFCR_ELx_ExTRE | + TRFCR_ELx_E0TRE); + + /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */ + if (is_kernel_in_hyp_mode()) + trfcr |= TRFCR_EL2_CX; + + write_sysreg_s(trfcr, SYS_TRFCR_EL1); +} + static void etm4_init_arch_data(void *info) { u32 etmidr0; @@ -1044,6 +1068,7 @@ static void etm4_init_arch_data(void *info) /* NUMCNTR, bits[30:28] number of counters available for tracing */ drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); etm4_cs_lock(drvdata, csa); + cpu_enable_tracing(); } static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config) From patchwork Mon Feb 1 18:13:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 12059681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2885EC433DB for ; Mon, 1 Feb 2021 18:20:30 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 78B0F64E50 for ; Mon, 1 Feb 2021 18:20:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 78B0F64E50 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lqCqB8TT60a7SYYaaZJlkP0vm9pBP7rtJgJPSP1SxIQ=; b=hpfo/hxVLto00eOFrykbFPUXi 3/f4ub0iPpz2KjabV3jrEv9wTC2GVo9OKFLb18puGuRDhwZOujdmyfpRY8yd9q170mxvb0Us5Ad/B 1S6qUS/eaj8QM5BHXc4NluvMfvT2NcipuuwwaRVJeNNiWCaTAMCzoYWTEffuiNgKxcG/HLCLzWmN/ NcJ2lmtI2IlR02C67/33ihdPeyzIP1KbGidOMqI3sR2zBSBJdjNHli7OFktj3yU8UeiHWNfuxfyzj SGLHu0yOOVLMuEMBIbP7nuBg8LmQtFfW8YsK4ous3MBYrD3b62YOGNt5RTdNrtCQxp92Ha+XDcFUT tPMGB4W9A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dm2-00055V-AX; Mon, 01 Feb 2021 18:18:06 +0000 Received: from casper.infradead.org ([90.155.50.34]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6dia-0003DK-6C for linux-arm-kernel@merlin.infradead.org; Mon, 01 Feb 2021 18:14:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=nr70diwKm9rfL7MM7qHNXTK5sP1+kROD5tDezAlipcU=; b=KSwUW0kvTIAi5E0KAP4+vDO7+1 aeYings3hk/qox3xoGDV9jJyDiQLxSapqCioH+THMf944htmTwdGJkhG3bD2dM8KJXVqioK+o3zEA c2w0cEeFl21cBECoVWNXDf4F7d+cPf1H+RsfYt2bwSUx4CKvSmKCGZSX2YUasc5Y+G0Oj8MjtO64t ZUZLgOkF7kHWhD4J7TIgC7sIHaghcA/5y1DSaKjaqxidIyXvh/Ad0UGK2obLdYuDuuVYhgHZsOooU DKiV2GuqbDGvgW3GxVw/3+EGLeVv1vLJQGNYL384oKsYjTuw+zaMGEAnwT5i8PdWEKz9lNJKlcTNP 6FLbxoXQ==; Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by casper.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1l6diW-00E8E0-PA for linux-arm-kernel@lists.infradead.org; Mon, 01 Feb 2021 18:14:29 +0000 Received: by mail-pg1-x52f.google.com with SMTP id t25so12643177pga.2 for ; Mon, 01 Feb 2021 10:14:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nr70diwKm9rfL7MM7qHNXTK5sP1+kROD5tDezAlipcU=; b=MweWa4R7QAtD77x3C6hFfsPVEwdDdzzg2MD23DvRQbnCZqpsh1VWYPKZhhTEiXxk7d o3GSAr6sxoiE+hut5dWYJka3Fqcjrgebg2NkGx7paQu7MLA+ryo5Dxl+PJ1krr6axQmJ BVZ/3nXL7XJwpEY6c4fXt4AaERVP+PgpPh+/+5J1ysGDhkVmFz0vDV5f4Y+elbyeXk0c yTGofEMPyb6S94+d4oeJVf+HV64D2vYiOTYNBXcIYNIkv2Lc0OA2oI5QnUGqMFGXg8qH AWZMHBO2wMIbdtNPorCO175mb+9kwcJsgUH+pv3UFv5soO7tL6PDOwEmIMAYDqlvmPeI bFAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nr70diwKm9rfL7MM7qHNXTK5sP1+kROD5tDezAlipcU=; b=QwYdeXQR63DpN+0qP69D8vKD8/Tic3lXlVPBHQyEErKNA7+epbgygdYkIFofSFL3/E i3q9L6Eh44A/yuFpAn87nmCBjU0VGXxhh9RV4MZi00fc9udY7TsXe1/iWiItyFqra6rC EXca2XCjaOxoTlKLIMUvbLdYpSNO+4/TVlkp0pJgv84pksgCmAcXoJvXn6O88HI1+s8m AW43i2mX7Hij7xilLbWuyYb0xXJghIWPtTlg9pNUus3N4Y1yvZiJzWP7ruFY1nPhRQ02 p4OPC56iprHOaf9DADpy7adEXxjUBySz3XTgjxC53gd01STIVqt2NqvHOMpje2VO2F5s JwaA== X-Gm-Message-State: AOAM5308Ud2FSmzD9mjDQJBQNQS9zcf1QP8wM+a/dcDE393yld9RBYPG ElY7hjkCMTwUxS3ezAuDSoeRAqF4WTyg3w== X-Google-Smtp-Source: ABdhPJwzdaVIdOZgQQgRIn5605WsBCr6WfU13mva0Y8/Hs+/Czbt+LpbG0ndGzNOxhoJR65jJJNgIQ== X-Received: by 2002:a62:4e10:0:b029:1c9:9015:dc5b with SMTP id c16-20020a624e100000b02901c99015dc5bmr17643686pfb.30.1612203266668; Mon, 01 Feb 2021 10:14:26 -0800 (PST) Received: from xps15.cg.shawcable.net (S0106889e681aac74.cg.shawcable.net. [68.147.0.187]) by smtp.gmail.com with ESMTPSA id e12sm75784pjj.23.2021.02.01.10.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Feb 2021 10:14:26 -0800 (PST) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 31/31] coresight: etm4x: Handle accesses to TRCSTALLCTLR Date: Mon, 1 Feb 2021 11:13:51 -0700 Message-Id: <20210201181351.1475223-32-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210201181351.1475223-1-mathieu.poirier@linaro.org> References: <20210201181351.1475223-1-mathieu.poirier@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210201_181429_147379_4FB10CE2 X-CRM114-Status: GOOD ( 13.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Suzuki K Poulose TRCSTALLCTLR register is only implemented if TRCIDR3.STALLCTL == 0b1 Make sure the driver touches the register only it is implemented. Cc: stable@vger.kernel.org Cc: Mathieu Poirier Cc: Mike Leach Cc: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210127184617.3684379-1-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 ++++++--- drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 473ab7480a36..5017d33ba4f5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -306,7 +306,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR); etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R); - etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); + if (drvdata->stallctl) + etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR); etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR); etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR); @@ -1463,7 +1464,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR); state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R); - state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR); + if (drvdata->stallctl) + state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR); state->trctsctlr = etm4x_read32(csa, TRCTSCTLR); state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR); state->trcccctlr = etm4x_read32(csa, TRCCCCTLR); @@ -1575,7 +1577,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR); etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R); - etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); + if (drvdata->stallctl) + etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR); etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR); etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index b646d53a3133..0995a10790f4 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -389,7 +389,7 @@ static ssize_t mode_store(struct device *dev, config->eventctrl1 &= ~BIT(12); /* bit[8], Instruction stall bit */ - if (config->mode & ETM_MODE_ISTALL_EN) + if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true)) config->stall_ctrl |= BIT(8); else config->stall_ctrl &= ~BIT(8);