From patchwork Tue Feb 2 13:29:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85BA6C433E6 for ; Tue, 2 Feb 2021 13:31:40 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42C4264DBD for ; Tue, 2 Feb 2021 13:31:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 42C4264DBD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=v85RrsxrUAMW8l8hzhCVxlDcp7d9UEz5AElBRVzJK3M=; b=ldy7PDD50s3yp+qOmH78btxj5 BN/quT18IDBhKMEQMiN+Ns+V+ZtgKQbpIW6jFSvR5ZmDd2wKu1GQ7WsmZ5XTsqPpJ55OtXop5GiyA ffIsbtpqsYQ9Y6bZm+gtqwLAkozyqkaHRimdM7uZNClnBxu6wdrB/f9lzGebJjxufXu+YJVsrB9ko kjrb0TBRG0EOdBO3GWS2yuzVhAoKlzvmAGFkJnl7Q3edo95HXgUgfW+nI4XneOR80PjjmCxXrFZwG TnMBVyRkC7oNNZm+0dnumL46/6DWd6cRsrO9WFZ2Y1iiI4KCB++jN/DkSjn+v0j8YlBXNIHec48sz 3bQJNktiw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6vl4-0000a4-Dq; Tue, 02 Feb 2021 13:30:18 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6vkp-0000Th-Nt; Tue, 02 Feb 2021 13:30:13 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2310764F76; Tue, 2 Feb 2021 13:30:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=nJFVkFVcxLt04mnBQIBfm4IXRi2ERW4Q1DqINzouepk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PPTE7k8kTk+XXzwTslQP0Ritd+T4aPUY8VCOztRnA7mqy4ZhQaU13lMM9J+EHkc0b yHwbrU5KYbfnq7JwpONZhJCQD/Di55pgcdQKKTe1A1eH6OI/ZwrRwUhK3UBmPyXzDC W4Xpyu5c2qmm8psfC/oPx0S9HEzxNZBhGCMmHnPs/RB7YKB0JX4AR4RwxUvZdTkn8i tSD6s1rzTdzE75rWsXszeu9TLr8mzm4G9X5mH7xiIfRuVg7+2ZuLQ4T2h3CcQljtK/ 4UBVJP+WXDZnacBS1vF+DGD8+gZ1M5qSrMEKnOzmksi1K9bu2AUlO4BAKSOTtNlWyw T4oAWoVR/1HPQ== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011yn-Db; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab To: Subject: [PATCH 01/13] doc: bindings: pci: designware-pcie.txt: convert it to yaml Date: Tue, 2 Feb 2021 14:29:46 +0100 Message-Id: <706e684f571e142362d7be74eb1dcee2c8558052.1612271903.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210202_083003_964917_156A8B0C X-CRM114-Status: GOOD ( 20.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kunihiko Hayashi , Neil Armstrong , linux-pci@vger.kernel.org, Bjorn Andersson , linux-tegra@vger.kernel.org, Thierry Reding , linux-arm-kernel@axis.com, Thomas Petazzoni , Jonathan Chocron , Jonathan Hunter , Fabio Estevam , Marek Szyprowski , Jesper Nilsson , linux-samsung-soc@vger.kernel.org, Mauro Carvalho Chehab , Kevin Hilman , Krzysztof Kozlowski , Kishon Vijay Abraham I , Jaehoon Chung , Andy Gross , NXP Linux Team , Jerome Brunet , devicetree@vger.kernel.org, Richard Zhu , Martin Blumenstingl , linux-arm-msm@vger.kernel.org, Sascha Hauer , Rob Herring , Bjorn Helgaas , linux-amlogic@lists.infradead.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Gustavo Pimentel , linux-kernel@vger.kernel.org, Zhou Wang , Pengutronix Kernel Team , Jingoo Han , Shawn Guo , Lucas Stach Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert the file into a DT schema. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/amlogic,meson-pcie.txt | 4 +- .../bindings/pci/axis,artpec6-pcie.txt | 2 +- .../bindings/pci/designware-pcie.txt | 77 ---------- .../bindings/pci/fsl,imx6q-pcie.txt | 2 +- .../bindings/pci/hisilicon-histb-pcie.txt | 2 +- .../bindings/pci/hisilicon-pcie.txt | 2 +- .../devicetree/bindings/pci/kirin-pcie.txt | 2 +- .../bindings/pci/layerscape-pci.txt | 2 +- .../bindings/pci/nvidia,tegra194-pcie.txt | 4 +- .../devicetree/bindings/pci/pci-armada8k.txt | 2 +- .../devicetree/bindings/pci/pci-keystone.txt | 10 +- .../devicetree/bindings/pci/pcie-al.txt | 2 +- .../devicetree/bindings/pci/qcom,pcie.txt | 14 +- .../bindings/pci/samsung,exynos-pcie.yaml | 2 +- .../devicetree/bindings/pci/snps,pcie.yaml | 139 ++++++++++++++++++ .../pci/socionext,uniphier-pcie-ep.yaml | 2 +- .../devicetree/bindings/pci/ti-pci.txt | 4 +- .../devicetree/bindings/pci/uniphier-pcie.txt | 2 +- MAINTAINERS | 2 +- 19 files changed, 169 insertions(+), 107 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/snps,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt index b6acbe694ffb..da9253d43550 100644 --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt @@ -3,7 +3,7 @@ Amlogic Meson AXG DWC PCIE SoC controller Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: @@ -33,7 +33,7 @@ Required properties: - phy-names: must contain "pcie" - device_type: - should be "pci". As specified in designware-pcie.txt + should be "pci". As specified in snps,pcie.yaml Example configuration: diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt index 979dc7b6cfe8..84b53ae2c376 100644 --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt @@ -1,7 +1,7 @@ * Axis ARTPEC-6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt deleted file mode 100644 index 78494c4050f7..000000000000 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Synopsys DesignWare PCIe interface - -Required properties: -- compatible: - "snps,dw-pcie" for RC mode; - "snps,dw-pcie-ep" for EP mode; -- reg: For designware cores version < 4.80 contains the configuration - address space. For designware core version >= 4.80, contains - the configuration and ATU address space -- reg-names: Must be "config" for the PCIe configuration space and "atu" for - the ATU address space. - (The old way of getting the configuration address space from "ranges" - is deprecated and should be avoided.) -RC mode: -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI - properties to define the mapping of the PCIe interface to interrupt - numbers. -EP mode: -- num-ib-windows: number of inbound address translation windows -- num-ob-windows: number of outbound address translation windows - -Optional properties: -- num-lanes: number of lanes to use (this property should be specified unless - the link is brought already up in BIOS) -- reset-gpio: GPIO pin number of power good signal -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "pcie" - - "pcie_bus" -- snps,enable-cdm-check: This is a boolean property and if present enables - automatic checking of CDM (Configuration Dependent Module) registers - for data corruption. CDM registers include standard PCIe configuration - space registers, Port Logic registers, DMA and iATU (internal Address - Translation Unit) registers. -RC mode: -- num-viewport: number of view ports configured in hardware. If a platform - does not specify it, the driver assumes 2. -- bus-range: PCI bus numbers covered (it is recommended for new devicetrees - to specify this property, to keep backwards compatibility a range of - 0x00-0xff is assumed if not present) - -EP mode: -- max-functions: maximum number of functions that can be configured - -Example configuration: - - pcie: pcie@dfc00000 { - compatible = "snps,dw-pcie"; - reg = <0xdfc00000 0x0001000>, /* IP registers */ - <0xd0000000 0x0002000>; /* Configuration space */ - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000 - 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; - interrupts = <25>, <24>; - #interrupt-cells = <1>; - num-lanes = <1>; - }; -or - pcie: pcie@dfc00000 { - compatible = "snps,dw-pcie-ep"; - reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ - <0xdfc01000 0x0001000>, /* IP registers 2 */ - <0xd0000000 0x2000000>; /* Configuration space */ - reg-names = "dbi", "dbi2", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <2>; - num-lanes = <1>; - }; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index de4b2baf91e8..9470b279e3e4 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -1,7 +1,7 @@ * Freescale i.MX6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: diff --git a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt index 760b4d740616..2f62119d97b9 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt @@ -3,7 +3,7 @@ HiSilicon STB PCIe host bridge DT description The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core. It shares common functions with the DesignWare PCIe core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index d6796ef54ea1..4d243bfb9709 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -3,7 +3,7 @@ HiSilicon Hip05 and Hip06 PCIe host bridge DT description HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt index 6bbe43818ad5..a38f8e38a67b 100644 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -3,7 +3,7 @@ HiSilicon Kirin SoCs PCIe host DT description Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index daa99f7d4c3f..8070adfc1746 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -1,7 +1,7 @@ Freescale Layerscape PCIe controller This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. This controller derives its clocks from the Reset Configuration Word (RCW) which is used to describe the PLL settings at the time of chip-reset. diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt index bd43f3c3ece4..4644d79e0e0c 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -1,7 +1,7 @@ NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) This PCIe controller is based on the Synopsis Designware PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Some of the controller instances are dual mode where in they can work either in root port mode or endpoint mode but one at a time. @@ -22,7 +22,7 @@ Required properties: property. - reg-names: Must include the following entries: "appl": Controller's application logic registers - "config": As per the definition in designware-pcie.txt + "config": As per the definition in snps,pcie.yaml "atu_dma": iATU and DMA registers. This is where the iATU (internal Address Translation Unit) registers of the PCIe core are made available for SW access. diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index 7a813d0e6d63..4531b895e9ea 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -1,7 +1,7 @@ * Marvell Armada 7K/8K PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: "marvell,armada8k-pcie" diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 47202a2938f2..ac271a0ca078 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -3,9 +3,9 @@ TI Keystone PCIe interface Keystone PCI host Controller is based on the Synopsys DesignWare PCI hardware version 3.65. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt +Documentation/devicetree/bindings/pci/snps,pcie.yaml -Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt +Please refer to Documentation/devicetree/bindings/pci/snps,pcie.yaml for the details of DesignWare DT bindings. Additional properties are described here as well as properties that are not applicable. @@ -82,11 +82,11 @@ reg-names: "dbics" for the DesignWare PCIe registers, "app" for the Address Translation Unit configuration registers and "addr_space" used to map remote RC address space num-ib-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml num-ob-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml num-lanes: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml power-domains: As documented by the generic PM domain bindings in Documentation/devicetree/bindings/power/power_domain.txt. ti,syscon-pcie-mode: phandle to the device control module required to configure diff --git a/Documentation/devicetree/bindings/pci/pcie-al.txt b/Documentation/devicetree/bindings/pci/pcie-al.txt index 557a5089229d..6e1e20e15ae9 100644 --- a/Documentation/devicetree/bindings/pci/pcie-al.txt +++ b/Documentation/devicetree/bindings/pci/pcie-al.txt @@ -2,7 +2,7 @@ Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare PCI core. It inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Properties of the host controller node that differ from it are: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3b55310390a0..43c3086cf6ea 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -33,22 +33,22 @@ - device_type: Usage: required Value type: - Definition: Should be "pci". As specified in designware-pcie.txt + Definition: Should be "pci". As specified in snps,pcie.yaml - #address-cells: Usage: required Value type: - Definition: Should be 3. As specified in designware-pcie.txt + Definition: Should be 3. As specified in snps,pcie.yaml - #size-cells: Usage: required Value type: - Definition: Should be 2. As specified in designware-pcie.txt + Definition: Should be 2. As specified in snps,pcie.yaml - ranges: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - interrupts: Usage: required @@ -63,17 +63,17 @@ - #interrupt-cells: Usage: required Value type: - Definition: Should be 1. As specified in designware-pcie.txt + Definition: Should be 1. As specified in snps,pcie.yaml - interrupt-map-mask: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - interrupt-map: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - clocks: Usage: required diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml index 1810bf722350..8a4fe2d021ed 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -13,7 +13,7 @@ maintainers: description: |+ Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in - designware-pcie.txt. + snps,pcie.yaml. allOf: - $ref: /schemas/pci/pci-bus.yaml# diff --git a/Documentation/devicetree/bindings/pci/snps,pcie.yaml b/Documentation/devicetree/bindings/pci/snps,pcie.yaml new file mode 100644 index 000000000000..eeb5dad6937d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/snps,pcie.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/snps,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare PCIe interface + +maintainers: + - Jingoo Han + - Gustavo Pimentel + +description: | + Synopsys DesignWare PCIe host controller + +anyOf: + - {} + - items: + contains: + enum: + - snps,dw-pcie + - snps,dw-pcie-ep + +properties: + compatible: + description: | + The compatible can be either: + - snps,dw-pcie # for RC mode + - snps,dw-pcie-ep # For EP mode + or some other value, when there's a host-specific driver + + reg: + description: | + Contains DBI and the configuration address space for all + Designware versions. + For Designware core version >= 4.80, should also contain the + ATU address space. + minItems: 2 + maxItems: 4 + + reset-gpio: + description: GPIO pin number for the PERST# signal + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 8 + + clock-names: + items: + contains: + enum: [ pcie, pcie_bus ] + minItems: 2 + maxItems: 8 + + "snps,enable-cdm-check": + $ref: /schemas/types.yaml#definitions/flag + description: | + This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. + + # The following are optional properties for RC mode + + num-viewport: + description: | + number of view ports configured in hardware. If a platform + does not specify it, the driver assumes 2. + deprecated: true + + # The following are mandatory properties for EP Mode + + num-ib-windows: + description: number of inbound address translation windows + maxItems: 1 + deprecated: true + + num-ob-windows: + description: number of outbound address translation windows + maxItems: 1 + deprecated: true + + # The following are optional properties for EP mode + + max-functions: + description: maximum number of functions that can be configured + +required: + - reg + - reg-names + +allOf: + - if: + properties: + compatible: + contains: + const: snps,dw-pcie + then: + allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - if: + properties: + compatible: + contains: + const: snps,dw-pcie-ep + then: + required: + - compatible + +additionalProperties: false + +examples: + - | + pcie: pcie@dfc00000 { + compatible = "snps,dw-pcie"; + reg = <0xdfc00000 0x0001000>, /* IP registers */ + <0xd0000000 0x0002000>; /* Configuration space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + interrupts = <25>, <24>; + #interrupt-cells = <1>; + num-lanes = <1>; + }; + pcie_ep: pcie_ep@dfd00000 { + compatible = "snps,dw-pcie-ep"; + reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ + <0xdfc01000 0x0001000>, /* IP registers 2 */ + <0xd0000000 0x2000000>; /* Configuration space */ + reg-names = "dbi", "dbi2", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <2>; + num-lanes = <1>; + }; diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml index d6cf8a560ef0..9c8733d21de4 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -10,7 +10,7 @@ description: | UniPhier PCIe endpoint controller is based on the Synopsys DesignWare PCI core. It shares common features with the PCIe DesignWare core and inherits common properties defined in - Documentation/devicetree/bindings/pci/designware-pcie.txt. + Documentation/devicetree/bindings/pci/snps,pcie.yaml. maintainers: - Kunihiko Hayashi diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index d5cbfe6b0d89..dfebfdb9b819 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -12,7 +12,7 @@ PCIe DesignWare Controller number of PHYs as specified in *phys* property. - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - - num-lanes as specified in ../designware-pcie.txt + - num-lanes as specified in ../snps,pcie.yaml - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the register offset to specify lane selection. @@ -32,7 +32,7 @@ HOST MODE device_type, ranges, interrupt-map-mask, - interrupt-map : as specified in ../designware-pcie.txt + interrupt-map : as specified in ../snps,pcie.yaml - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument should contain the register offset within syscon and the 2nd argument should contain the bit field diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index c4b7381733a0..17cfe504d800 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -6,7 +6,7 @@ on Socionext UniPhier SoCs. UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Required properties: - compatible: Should be "socionext,uniphier-pcie". diff --git a/MAINTAINERS b/MAINTAINERS index 2dd0a662d931..0bcba0d4994c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13673,7 +13673,7 @@ M: Jingoo Han M: Gustavo Pimentel L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/designware-pcie.txt +F: Documentation/devicetree/bindings/pci/snps,pcie.yaml F: drivers/pci/controller/dwc/*designware* PCI DRIVER FOR TI DRA7XX/J721E From patchwork Tue Feb 2 13:29:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF0A3C433DB for ; Tue, 2 Feb 2021 13:31:17 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 777BA64DBD for ; Tue, 2 Feb 2021 13:31:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 777BA64DBD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/WJkz0YhGMU1tg95bEl/eJGLiUD6fu/aTIQPHhwOC88=; b=k6A5RWme6E6G5fgCiM/ff/UvD dhlzqbYhB3sX2F/yAbae86KhW+tFSnlsOzP2d15m7VzzFRvkYai6lXm0NNIttab4es5FqkivcN9ef SQTvxcUBjUMa6bUfoRgWSg3vGEJ/OuCekp7OT0C8ZXOxfKSWJ/oZbnHimEd5gTaq2/WAOK6VEfJKI YxBVr9RY3vRTt6W8q9dC60clIXgppv4dsxMJn6Is9QkWiNTd7zMRwbFeh6ZXB7TNY8cn9Sk84bEV9 NhLLA4wmjsv+92VeYUP0sOfzaZUP2fYcBj/VTsZQQCf2s/I2NpUpmcUylF4/RUelIFwgcXZqrbnZ4 o6X+qes4A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6vku-0000XP-AG; Tue, 02 Feb 2021 13:30:08 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l6vkp-0000Se-1F for linux-arm-kernel@lists.infradead.org; Tue, 02 Feb 2021 13:30:06 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id E2C3F64F68; Tue, 2 Feb 2021 13:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612272602; bh=0k8G1hBpz4Np2I1ZDNqtU5gVCYWWxmCauHG4Ld/0WK8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B4qfx5bMt2weX0iSbqs43jbBq7MKFCkC+FAJ01PO13+R8QCwYAebtYke1AoVPZk9x bZuEFcOZHpH+IiAsJI1oTiGuJi6ou9tmvb1lV4y9zEWI0HOixjPBw9XQNYfDbNJeZy aMhJkU15oINMOcElK36EbUDelf3C/SLz4UIaNbg6RJgrIDxOlYIIIrcSgM/t/ATC9l 9BBrR5GqhEHcxfONkpUSkWOTUgoR89XtR2VJvNGRHnjzYKlxLHvQm4TzF1fDtokOvd Kt5epQ4fiFS4iuE9AC2T9ql1IiZcBs+kpLmjjh6C2jOmDQWuX5H9/rEjjETWRR53sD 5TJxwRQP/HImA== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011yv-KY; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab To: Subject: [PATCH 05/13] arm64: dts: hisilicon: Add HI3670 PCI-E controller support Date: Tue, 2 Feb 2021 14:29:50 +0100 Message-Id: <301bbde15f7a248222745c8ab98c0e20ae877db0.1612271903.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210202_083003_382778_3D9E2872 X-CRM114-Status: GOOD ( 10.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Mauro Carvalho Chehab , linux-kernel@vger.kernel.org, Wei Xu , Rob Herring , Manivannan Sadhasivam , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Manivannan Sadhasivam Add PCI-E controller support for HiSilicon HI3670 SoC. [mchehab+huawei@kernel.org: fix merge conflicts] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 64 +++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 5522a5de07a8..c0a0336a8ea4 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -660,6 +666,64 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie", "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xfc000000 0x0 0x80000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + switch,reset-gpios = <&gpio7 0 0 >; + eth,reset-gpios = <&gpio25 2 0 >; + m_2,reset-gpios = <&gpio3 1 0 >; + mini1,reset-gpios = <&gpio27 4 0 >; + + eth,clkreq-gpios = <&gpio20 6 0 >; + m_2,clkreq-gpios = <&gpio27 3 0 >; + mini1,clkreq-gpios = <&gpio17 0 0 >; + + /*vboost iboost pre post main*/ + eye_param = <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq_pmx_func &pcie_clkreq_cfg_func>; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; From patchwork Tue Feb 2 13:29:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12061623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0910C4332D for ; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YUkXaIK68CSCM4Vaqzz+PupuMY7Sx73apJkS8Xl4sbkCGrzk8MrdEzhZE6j+RdKe9 +izykXTBqxMbvIJiuJZFJ4bk6rsKfrIqVE3mINm2G5XA2BdaD5xENhF2Pw66Zz+iKe eWG7PDVyR51IWYcV9BWvGOqM4e++q49pG3jQFfCPOmxT8wf2MgHQt6LHKk/Yhzt6cc p/eXYzxcfCN4Qeas+X4jSHM69+9Tn9cnrjHeg+oled73uFHHa+9K6k4kv010HteMkq mrbZJSUNjLc+IMrNjNivP3karOUuCWU26EnB4r0G8V1Ib6B9Bs5BhWiv782OSctKVU 1LjICCl9cFN1g== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l6vkl-0011zH-Tr; Tue, 02 Feb 2021 14:29:59 +0100 From: Mauro Carvalho Chehab To: Subject: [PATCH 13/13] arm64: dts: hisilicon: cleanup Hikey 970 PCI schema Date: Tue, 2 Feb 2021 14:29:58 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210202_083003_441162_05AA26ED X-CRM114-Status: GOOD ( 11.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Mauro Carvalho Chehab , linux-kernel@vger.kernel.org, Wei Xu , Rob Herring , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The original schema was not generic enough and not properly documented. Those got updated via some driver changes. Apply those changes also to Hikey 970 schema. Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 +++++++++--------- .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index c0a0336a8ea4..7e96d5eda13a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -673,11 +673,12 @@ its_pcie: interrupt-controller@f4000000 { }; pcie@f4000000 { - compatible = "hisilicon,kirin970-pcie", "hisilicon,kirin960-pcie"; + compatible = "hisilicon,kirin970-pcie"; reg = <0x0 0xf4000000 0x0 0x1000000>, <0x0 0xfc180000 0x0 0x1000>, <0x0 0xfc000000 0x0 0x80000>, <0x0 0xf5000000 0x0 0x2000>; + pci-supply = <&ldo33>; reg-names = "dbi", "apb", "phy", "config"; bus-range = <0x0 0x1>; msi-parent = <&its_pcie>; @@ -705,19 +706,18 @@ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - switch,reset-gpios = <&gpio7 0 0 >; - eth,reset-gpios = <&gpio25 2 0 >; - m_2,reset-gpios = <&gpio3 1 0 >; - mini1,reset-gpios = <&gpio27 4 0 >; - eth,clkreq-gpios = <&gpio20 6 0 >; - m_2,clkreq-gpios = <&gpio27 3 0 >; - mini1,clkreq-gpios = <&gpio17 0 0 >; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; - /*vboost iboost pre post main*/ + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, + <&gpio17 0 0 >; + + /* vboost iboost pre post main */ eye_param = <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi index 8cf45b962fea..49afcd7c00ce 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi @@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */ regulator-name = "ldo33"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; }; ldo34: LDO34 { /* GPS AUX IN VDD */