From patchwork Wed Feb 3 07:01:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063519 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67F0FC433E0 for ; Wed, 3 Feb 2021 07:05:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0A18C64F5D for ; Wed, 3 Feb 2021 07:05:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231862AbhBCHF0 (ORCPT ); Wed, 3 Feb 2021 02:05:26 -0500 Received: from mail.kernel.org ([198.145.29.99]:35530 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232020AbhBCHD1 (ORCPT ); Wed, 3 Feb 2021 02:03:27 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9144864F74; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335721; bh=nJFVkFVcxLt04mnBQIBfm4IXRi2ERW4Q1DqINzouepk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dGRtKb0i4HMj94TBtnNezfk1bY7Db4Y2IOYOT1gq0o8AmV9/BTWPtOJQq0wr+ijGk NR+UKz9zNtGRNQznPZ/3atj0aYsTZPUw6DqQ5Hd9+adHZUNvrEX4CLFAk3zbEeorOy IDjMlorc8V8mE07/D3zCiEjxx/pjRUOnAVHqrkWVjIlKwAYykJOdV35Ko+pkg7e9/0 oJAWf6Yyci4LNgOmdTInEQEc6pADOmAiFAnQjZ70bDGKumNmruzHgAEqZCUa0OT8Jr VGP/5g6kOVfQCE/7FKSUgMjLyp7+gyb5Xgp9nHZX1LztmYx2M8QX44wrVO45kOPi8M 3KwOje6tgrxTA== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAn-001CAQ-WF; Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Fabio Estevam , Gustavo Pimentel , Jaehoon Chung , Jerome Brunet , Jesper Nilsson , Jingoo Han , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kunihiko Hayashi , Lucas Stach , Marek Szyprowski , Martin Blumenstingl , NXP Linux Team , Neil Armstrong , Pengutronix Kernel Team , Richard Zhu , Rob Herring , Sascha Hauer , Shawn Guo , Thierry Reding , Thomas Petazzoni , Zhou Wang , devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 01/11] doc: bindings: PCI: designware-pcie.txt: convert it to YAML Date: Wed, 3 Feb 2021 08:01:45 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert the file into a DT schema. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/amlogic,meson-pcie.txt | 4 +- .../bindings/pci/axis,artpec6-pcie.txt | 2 +- .../bindings/pci/designware-pcie.txt | 77 ---------- .../bindings/pci/fsl,imx6q-pcie.txt | 2 +- .../bindings/pci/hisilicon-histb-pcie.txt | 2 +- .../bindings/pci/hisilicon-pcie.txt | 2 +- .../devicetree/bindings/pci/kirin-pcie.txt | 2 +- .../bindings/pci/layerscape-pci.txt | 2 +- .../bindings/pci/nvidia,tegra194-pcie.txt | 4 +- .../devicetree/bindings/pci/pci-armada8k.txt | 2 +- .../devicetree/bindings/pci/pci-keystone.txt | 10 +- .../devicetree/bindings/pci/pcie-al.txt | 2 +- .../devicetree/bindings/pci/qcom,pcie.txt | 14 +- .../bindings/pci/samsung,exynos-pcie.yaml | 2 +- .../devicetree/bindings/pci/snps,pcie.yaml | 139 ++++++++++++++++++ .../pci/socionext,uniphier-pcie-ep.yaml | 2 +- .../devicetree/bindings/pci/ti-pci.txt | 4 +- .../devicetree/bindings/pci/uniphier-pcie.txt | 2 +- MAINTAINERS | 2 +- 19 files changed, 169 insertions(+), 107 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/snps,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt index b6acbe694ffb..da9253d43550 100644 --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt @@ -3,7 +3,7 @@ Amlogic Meson AXG DWC PCIE SoC controller Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: @@ -33,7 +33,7 @@ Required properties: - phy-names: must contain "pcie" - device_type: - should be "pci". As specified in designware-pcie.txt + should be "pci". As specified in snps,pcie.yaml Example configuration: diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt index 979dc7b6cfe8..84b53ae2c376 100644 --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt @@ -1,7 +1,7 @@ * Axis ARTPEC-6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt deleted file mode 100644 index 78494c4050f7..000000000000 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ /dev/null @@ -1,77 +0,0 @@ -* Synopsys DesignWare PCIe interface - -Required properties: -- compatible: - "snps,dw-pcie" for RC mode; - "snps,dw-pcie-ep" for EP mode; -- reg: For designware cores version < 4.80 contains the configuration - address space. For designware core version >= 4.80, contains - the configuration and ATU address space -- reg-names: Must be "config" for the PCIe configuration space and "atu" for - the ATU address space. - (The old way of getting the configuration address space from "ranges" - is deprecated and should be avoided.) -RC mode: -- #address-cells: set to <3> -- #size-cells: set to <2> -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI - properties to define the mapping of the PCIe interface to interrupt - numbers. -EP mode: -- num-ib-windows: number of inbound address translation windows -- num-ob-windows: number of outbound address translation windows - -Optional properties: -- num-lanes: number of lanes to use (this property should be specified unless - the link is brought already up in BIOS) -- reset-gpio: GPIO pin number of power good signal -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - "pcie" - - "pcie_bus" -- snps,enable-cdm-check: This is a boolean property and if present enables - automatic checking of CDM (Configuration Dependent Module) registers - for data corruption. CDM registers include standard PCIe configuration - space registers, Port Logic registers, DMA and iATU (internal Address - Translation Unit) registers. -RC mode: -- num-viewport: number of view ports configured in hardware. If a platform - does not specify it, the driver assumes 2. -- bus-range: PCI bus numbers covered (it is recommended for new devicetrees - to specify this property, to keep backwards compatibility a range of - 0x00-0xff is assumed if not present) - -EP mode: -- max-functions: maximum number of functions that can be configured - -Example configuration: - - pcie: pcie@dfc00000 { - compatible = "snps,dw-pcie"; - reg = <0xdfc00000 0x0001000>, /* IP registers */ - <0xd0000000 0x0002000>; /* Configuration space */ - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000 - 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; - interrupts = <25>, <24>; - #interrupt-cells = <1>; - num-lanes = <1>; - }; -or - pcie: pcie@dfc00000 { - compatible = "snps,dw-pcie-ep"; - reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ - <0xdfc01000 0x0001000>, /* IP registers 2 */ - <0xd0000000 0x2000000>; /* Configuration space */ - reg-names = "dbi", "dbi2", "addr_space"; - num-ib-windows = <6>; - num-ob-windows = <2>; - num-lanes = <1>; - }; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index de4b2baf91e8..9470b279e3e4 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -1,7 +1,7 @@ * Freescale i.MX6 PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: diff --git a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt index 760b4d740616..2f62119d97b9 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt @@ -3,7 +3,7 @@ HiSilicon STB PCIe host bridge DT description The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core. It shares common functions with the DesignWare PCIe core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index d6796ef54ea1..4d243bfb9709 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -3,7 +3,7 @@ HiSilicon Hip05 and Hip06 PCIe host bridge DT description HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt index 6bbe43818ad5..a38f8e38a67b 100644 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -3,7 +3,7 @@ HiSilicon Kirin SoCs PCIe host DT description Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Additional properties are described here: diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index daa99f7d4c3f..8070adfc1746 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -1,7 +1,7 @@ Freescale Layerscape PCIe controller This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. This controller derives its clocks from the Reset Configuration Word (RCW) which is used to describe the PLL settings at the time of chip-reset. diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt index bd43f3c3ece4..4644d79e0e0c 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -1,7 +1,7 @@ NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) This PCIe controller is based on the Synopsis Designware PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Some of the controller instances are dual mode where in they can work either in root port mode or endpoint mode but one at a time. @@ -22,7 +22,7 @@ Required properties: property. - reg-names: Must include the following entries: "appl": Controller's application logic registers - "config": As per the definition in designware-pcie.txt + "config": As per the definition in snps,pcie.yaml "atu_dma": iATU and DMA registers. This is where the iATU (internal Address Translation Unit) registers of the PCIe core are made available for SW access. diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index 7a813d0e6d63..4531b895e9ea 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -1,7 +1,7 @@ * Marvell Armada 7K/8K PCIe interface This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in designware-pcie.txt. +and thus inherits all the common properties defined in snps,pcie.yaml. Required properties: - compatible: "marvell,armada8k-pcie" diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 47202a2938f2..ac271a0ca078 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -3,9 +3,9 @@ TI Keystone PCIe interface Keystone PCI host Controller is based on the Synopsys DesignWare PCI hardware version 3.65. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt +Documentation/devicetree/bindings/pci/snps,pcie.yaml -Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt +Please refer to Documentation/devicetree/bindings/pci/snps,pcie.yaml for the details of DesignWare DT bindings. Additional properties are described here as well as properties that are not applicable. @@ -82,11 +82,11 @@ reg-names: "dbics" for the DesignWare PCIe registers, "app" for the Address Translation Unit configuration registers and "addr_space" used to map remote RC address space num-ib-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml num-ob-windows: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml num-lanes: As specified in - Documentation/devicetree/bindings/pci/designware-pcie.txt + Documentation/devicetree/bindings/pci/snps,pcie.yaml power-domains: As documented by the generic PM domain bindings in Documentation/devicetree/bindings/power/power_domain.txt. ti,syscon-pcie-mode: phandle to the device control module required to configure diff --git a/Documentation/devicetree/bindings/pci/pcie-al.txt b/Documentation/devicetree/bindings/pci/pcie-al.txt index 557a5089229d..6e1e20e15ae9 100644 --- a/Documentation/devicetree/bindings/pci/pcie-al.txt +++ b/Documentation/devicetree/bindings/pci/pcie-al.txt @@ -2,7 +2,7 @@ Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare PCI core. It inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Properties of the host controller node that differ from it are: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3b55310390a0..43c3086cf6ea 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -33,22 +33,22 @@ - device_type: Usage: required Value type: - Definition: Should be "pci". As specified in designware-pcie.txt + Definition: Should be "pci". As specified in snps,pcie.yaml - #address-cells: Usage: required Value type: - Definition: Should be 3. As specified in designware-pcie.txt + Definition: Should be 3. As specified in snps,pcie.yaml - #size-cells: Usage: required Value type: - Definition: Should be 2. As specified in designware-pcie.txt + Definition: Should be 2. As specified in snps,pcie.yaml - ranges: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - interrupts: Usage: required @@ -63,17 +63,17 @@ - #interrupt-cells: Usage: required Value type: - Definition: Should be 1. As specified in designware-pcie.txt + Definition: Should be 1. As specified in snps,pcie.yaml - interrupt-map-mask: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - interrupt-map: Usage: required Value type: - Definition: As specified in designware-pcie.txt + Definition: As specified in snps,pcie.yaml - clocks: Usage: required diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml index 1810bf722350..8a4fe2d021ed 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -13,7 +13,7 @@ maintainers: description: |+ Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in - designware-pcie.txt. + snps,pcie.yaml. allOf: - $ref: /schemas/pci/pci-bus.yaml# diff --git a/Documentation/devicetree/bindings/pci/snps,pcie.yaml b/Documentation/devicetree/bindings/pci/snps,pcie.yaml new file mode 100644 index 000000000000..eeb5dad6937d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/snps,pcie.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/snps,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare PCIe interface + +maintainers: + - Jingoo Han + - Gustavo Pimentel + +description: | + Synopsys DesignWare PCIe host controller + +anyOf: + - {} + - items: + contains: + enum: + - snps,dw-pcie + - snps,dw-pcie-ep + +properties: + compatible: + description: | + The compatible can be either: + - snps,dw-pcie # for RC mode + - snps,dw-pcie-ep # For EP mode + or some other value, when there's a host-specific driver + + reg: + description: | + Contains DBI and the configuration address space for all + Designware versions. + For Designware core version >= 4.80, should also contain the + ATU address space. + minItems: 2 + maxItems: 4 + + reset-gpio: + description: GPIO pin number for the PERST# signal + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 8 + + clock-names: + items: + contains: + enum: [ pcie, pcie_bus ] + minItems: 2 + maxItems: 8 + + "snps,enable-cdm-check": + $ref: /schemas/types.yaml#definitions/flag + description: | + This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. + + # The following are optional properties for RC mode + + num-viewport: + description: | + number of view ports configured in hardware. If a platform + does not specify it, the driver assumes 2. + deprecated: true + + # The following are mandatory properties for EP Mode + + num-ib-windows: + description: number of inbound address translation windows + maxItems: 1 + deprecated: true + + num-ob-windows: + description: number of outbound address translation windows + maxItems: 1 + deprecated: true + + # The following are optional properties for EP mode + + max-functions: + description: maximum number of functions that can be configured + +required: + - reg + - reg-names + +allOf: + - if: + properties: + compatible: + contains: + const: snps,dw-pcie + then: + allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - if: + properties: + compatible: + contains: + const: snps,dw-pcie-ep + then: + required: + - compatible + +additionalProperties: false + +examples: + - | + pcie: pcie@dfc00000 { + compatible = "snps,dw-pcie"; + reg = <0xdfc00000 0x0001000>, /* IP registers */ + <0xd0000000 0x0002000>; /* Configuration space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + interrupts = <25>, <24>; + #interrupt-cells = <1>; + num-lanes = <1>; + }; + pcie_ep: pcie_ep@dfd00000 { + compatible = "snps,dw-pcie-ep"; + reg = <0xdfc00000 0x0001000>, /* IP registers 1 */ + <0xdfc01000 0x0001000>, /* IP registers 2 */ + <0xd0000000 0x2000000>; /* Configuration space */ + reg-names = "dbi", "dbi2", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <2>; + num-lanes = <1>; + }; diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml index d6cf8a560ef0..9c8733d21de4 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -10,7 +10,7 @@ description: | UniPhier PCIe endpoint controller is based on the Synopsys DesignWare PCI core. It shares common features with the PCIe DesignWare core and inherits common properties defined in - Documentation/devicetree/bindings/pci/designware-pcie.txt. + Documentation/devicetree/bindings/pci/snps,pcie.yaml. maintainers: - Kunihiko Hayashi diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index d5cbfe6b0d89..dfebfdb9b819 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -12,7 +12,7 @@ PCIe DesignWare Controller number of PHYs as specified in *phys* property. - ti,hwmods : Name of the hwmod associated to the pcie, "pcie", where is the instance number of the pcie from the HW spec. - - num-lanes as specified in ../designware-pcie.txt + - num-lanes as specified in ../snps,pcie.yaml - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control module and the register offset to specify lane selection. @@ -32,7 +32,7 @@ HOST MODE device_type, ranges, interrupt-map-mask, - interrupt-map : as specified in ../designware-pcie.txt + interrupt-map : as specified in ../snps,pcie.yaml - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument should contain the register offset within syscon and the 2nd argument should contain the bit field diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index c4b7381733a0..17cfe504d800 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -6,7 +6,7 @@ on Socionext UniPhier SoCs. UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in -Documentation/devicetree/bindings/pci/designware-pcie.txt. +Documentation/devicetree/bindings/pci/snps,pcie.yaml. Required properties: - compatible: Should be "socionext,uniphier-pcie". diff --git a/MAINTAINERS b/MAINTAINERS index 2dd0a662d931..0bcba0d4994c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13673,7 +13673,7 @@ M: Jingoo Han M: Gustavo Pimentel L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/designware-pcie.txt +F: Documentation/devicetree/bindings/pci/snps,pcie.yaml F: drivers/pci/controller/dwc/*designware* PCI DRIVER FOR TI DRA7XX/J721E From patchwork Wed Feb 3 07:01:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063511 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28D8FC433E0 for ; Wed, 3 Feb 2021 07:03:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD89464F60 for ; Wed, 3 Feb 2021 07:03:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231659AbhBCHDG (ORCPT ); Wed, 3 Feb 2021 02:03:06 -0500 Received: from mail.kernel.org ([198.145.29.99]:34052 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231542AbhBCHCl (ORCPT ); Wed, 3 Feb 2021 02:02:41 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5CAF164F5D; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335720; bh=E7yUqQo8Xn6JFXZwfNI1IGv93ZrxMNRZcf6mv6VtGWY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iuhKsqo+otYUgU/fiLZBZYudsjQYEMq+U1nY2q51juNEp1wLW8Nt2NNSWCE5K7E58 knbIl41FPMlMspDz6AEZ0ogi4GVxkrBZx+GpXNRnpQMKLL0ckZ2pd6096GFMgR6uUM 6ZsOMihsfokZhiTxoGhROsr8Vzzx4+rdDjx9bWR276VCwS9VH8S91w6N8TRis6dJpX Yhquj7aZZn4SZ2oTv0UFdNLtQpcnGZl2p56HLbb6wvPGe9cAPOawpkhEvsspMqg5QV ej+h7+ABq2QHAQI3Z+7pQcbBQnq6xEgXuEodWc1Xs1la+Mfgd4sxdMJgtGJyJXGRA4 tJlVSkAmDrz4Q== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAo-001CAS-1k; Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 02/11] doc: bindings: kirin-pcie.txt: convert it to YAML Date: Wed, 3 Feb 2021 08:01:46 +0100 Message-Id: <8617cb4f27b1f4146b956686f0410e5fc3827379.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert the file into a DT schema. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 90 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ----------- MAINTAINERS | 2 +- 3 files changed, 91 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file mode 100644 index 000000000000..46f9f3f25dbc --- /dev/null +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Xiaowei Song + - Binghui Wang + +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# +# - $ref: snps,pcie.yaml# + +properties: + compatible: + const: hisilicon,kirin960-pcie + + reg: + description: | + Should contain rc_dbi, apb, phy, config registers location and length. + + reg-names: + items: + - const: dbi # controller configuration registers + - const: apb # apb Ctrl register defined by Kirin + - const: phy # apb PHY register defined by Kirin + - const: config # PCIe configuration space registers + + reset-gpios: + description: The GPIO to generate PCIe PERST# assert and deassert signal. + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - reset-gpios + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@f4000000 { + compatible = "hisilicon,kirin960-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, + <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb","phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy", + "pcie_apb_sys", "pcie_aclk"; + reset-gpios = <&gpio11 1 0 >; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted file mode 100644 index a38f8e38a67b..000000000000 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ /dev/null @@ -1,50 +0,0 @@ -HiSilicon Kirin SoCs PCIe host DT description - -Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and -inherits common properties defined in -Documentation/devicetree/bindings/pci/snps,pcie.yaml. - -Additional properties are described here: - -Required properties -- compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC -- reg: Should contain rc_dbi, apb, phy, config registers location and length. -- reg-names: Must include the following entries: - "dbi": controller configuration registers; - "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; - "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - -Optional properties: - -Example based on kirin960: - - pcie@f4000000 { - compatible = "hisilicon,kirin-pcie"; - reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names = "dbi","apb","phy", "config"; - bus-range = <0x0 0x1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; - num-lanes = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, - <0x0 0 0 2 &gic 0 0 0 283 4>, - <0x0 0 0 3 &gic 0 0 0 284 4>, - <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 0bcba0d4994c..701d7115af74 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13817,7 +13817,7 @@ M: Xiaowei Song M: Binghui Wang L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/kirin-pcie.txt +F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml F: drivers/pci/controller/dwc/pcie-kirin.c PCIE DRIVER FOR HISILICON STB From patchwork Wed Feb 3 07:01:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063507 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CD93C43381 for ; Wed, 3 Feb 2021 07:03:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 523A764F5D for ; Wed, 3 Feb 2021 07:03:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231723AbhBCHDH (ORCPT ); Wed, 3 Feb 2021 02:03:07 -0500 Received: from mail.kernel.org ([198.145.29.99]:34064 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231636AbhBCHCl (ORCPT ); Wed, 3 Feb 2021 02:02:41 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5F67964F60; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335720; bh=718ZInNYsVDn+vu4wb8Pkopea6oBPczm2EkAavwDlgE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j8QqLCXYFRX630qd5yiwa8ak0iKhF5TfZyIlXp3727KMX/ATrS7whGPP5dycQK9iw 5Z1zL/PKmerGv2/lebhs0aeBJGaVK9eX5yltULC3Rx+TQUEVUGt+n0C3rc7ifO5F5+ PwqI1YbPZSN/toAkKRn0f4PlfAu9ghTjfwq+AkNsb5AFqj89F1huYu5OJNRW7xjeqJ z8A4kEV2u9o9v+34iqyV6zVoHHeBbcbsVcG5qy+PMtnhZcCxpyDSfk/8t+Tovlk+5p OlJzARTDjywDCwhEQ1ONWe0QA6K/qn+S/HFO0VYvTps0vH8UKqbmEoU8Sbu90u4J3a I9fL/vhtdZxuA== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAo-001CAU-3B; Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Rob Herring , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 03/11] doc: bindings: add new parameters used by Kirin 970 Date: Wed, 3 Feb 2021 08:01:47 +0100 Message-Id: <4d081ef108091aefd46cd7a520a63b94d2911f90.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There are a few extra optional bindings that are needed for Kirin 970 based PCIe designs to work. Add them. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 60 ++++++++++++++++++- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml index 46f9f3f25dbc..7a58883e07ec 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -34,8 +34,18 @@ properties: - const: config # PCIe configuration space registers reset-gpios: - description: The GPIO to generate PCIe PERST# assert and deassert signal. - maxItems: 1 + description: The GPIOs to generate PCIe PERST# assert and deassert signal. + minItems: 1 + maxItems: 4 + + clkreq-gpios: + description: CLKREQ signal GPIO pins to be enabled during PCI power on + minItems: 1 + maxItems: 3 + + eye_param: + description: items to adjust the eye parameters + maxItems: 5 required: - compatible @@ -52,12 +62,13 @@ examples: - | #include #include + #include soc { #address-cells = <2>; #size-cells = <2>; - pcie: pcie@f4000000 { + pcie1: pcie@f4000000 { compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, @@ -87,4 +98,47 @@ examples: "pcie_apb_sys", "pcie_aclk"; reset-gpios = <&gpio11 1 0 >; }; + + pcie2: pcie@f5000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xfc000000 0x0 0x80000>, + <0x0 0xf5000000 0x0 0x2000>; + pci-supply = <&ldo33>; + reg-names = "dbi", "apb", "phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", + "pcie_aclk"; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; + + /* vboost iboost pre post main */ + eye_param = <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + msi-parent = <&its_pcie>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq_pmx_func &pcie_clkreq_cfg_func>; + }; }; From patchwork Wed Feb 3 07:01:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063525 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E41DFC433E6 for ; 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Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Manivannan Sadhasivam , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH v2 04/11] PCI: dwc: pcie-kirin: add support for Kirin 970 PCIe controller Date: Wed, 3 Feb 2021 08:01:48 +0100 Message-Id: <4c9d6581478aa966698758c0420933f5defab4dd.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Manivannan Sadhasivam Add support for HiSilicon Kirin 970 (hi3670) SoC PCIe controller, based on Synopsys DesignWare PCIe controller IP. [mchehab+huawei@kernel.org: fix merge conflicts] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab Reported-by: kernel test robot --- drivers/pci/controller/dwc/pcie-kirin.c | 723 +++++++++++++++++++++++- 1 file changed, 707 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 026fd1e42a55..5925d2b345a8 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -29,6 +29,7 @@ #define to_kirin_pcie(x) dev_get_drvdata((x)->dev) #define REF_CLK_FREQ 100000000 +#define AXI_CLK_FREQ 207500000 /* PCIe ELBI registers */ #define SOC_PCIECTRL_CTRL0_ADDR 0x000 @@ -60,6 +61,65 @@ #define PCIE_DEBOUNCE_PARAM 0xF0F400 #define PCIE_OE_BYPASS (0x3 << 28) +/* PCIe CTRL registers */ +#define SOC_PCIECTRL_CTRL0_ADDR 0x000 +#define SOC_PCIECTRL_CTRL1_ADDR 0x004 +#define SOC_PCIECTRL_CTRL7_ADDR 0x01c +#define SOC_PCIECTRL_CTRL12_ADDR 0x030 +#define SOC_PCIECTRL_CTRL20_ADDR 0x050 +#define SOC_PCIECTRL_CTRL21_ADDR 0x054 +#define SOC_PCIECTRL_STATE0_ADDR 0x400 + +/* PCIe PHY registers */ +#define SOC_PCIEPHY_CTRL0_ADDR 0x000 +#define SOC_PCIEPHY_CTRL1_ADDR 0x004 +#define SOC_PCIEPHY_CTRL2_ADDR 0x008 +#define SOC_PCIEPHY_CTRL3_ADDR 0x00c +#define SOC_PCIEPHY_CTRL38_ADDR 0x0098 +#define SOC_PCIEPHY_STATE0_ADDR 0x400 + +#define PCIE_LINKUP_ENABLE (0x8020) +#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) +#define PCIE_LTSSM_ENABLE_BIT (0x1 << 11) +#define PCIEPHY_RESET_BIT (0x1 << 17) +#define PCIEPHY_PIPE_LINE0_RESET_BIT (0x1 << 19) + +#define PORT_MSI_CTRL_ADDR 0x820 +#define PORT_MSI_CTRL_UPPER_ADDR 0x824 +#define PORT_MSI_CTRL_INT0_ENABLE 0x828 + +#define EYEPARAM_NOCFG 0xFFFFFFFF +#define RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1 0x3001 +#define SUP_DIG_LVL_OVRD_IN 0xf +#define LANEN_DIG_ASIC_TX_OVRD_IN_1 0x1002 +#define LANEN_DIG_ASIC_TX_OVRD_IN_2 0x1003 + +/* kirin970 pciephy register */ +#define SOC_PCIEPHY_MMC1PLL_CTRL1 0xc04 +#define SOC_PCIEPHY_MMC1PLL_CTRL16 0xC40 +#define SOC_PCIEPHY_MMC1PLL_CTRL17 0xC44 +#define SOC_PCIEPHY_MMC1PLL_CTRL20 0xC50 +#define SOC_PCIEPHY_MMC1PLL_CTRL21 0xC54 +#define SOC_PCIEPHY_MMC1PLL_STAT0 0xE00 + +#define CRGPERIPH_PEREN12 0x470 +#define CRGPERIPH_PERDIS12 0x474 +#define CRGPERIPH_PCIECTRL0 0x800 + +/* define ie,oe cfg */ +#define IO_IE_EN_HARD_BYPASS (0x1 << 27) +#define IO_OE_EN_HARD_BYPASS (0x1 << 11) +#define IO_HARD_CTRL_DEBOUNCE_BYPASS (0x1 << 10) +#define IO_OE_GT_MODE (0x2 << 7) +#define DEBOUNCE_WAITCFG_IN (0xf << 20) +#define DEBOUNCE_WAITCFG_OUT (0xf << 13) + +/* noc power domain */ +#define NOC_POWER_IDLEREQ_1 0x38c +#define NOC_POWER_IDLE_1 0x394 +#define NOC_PW_MASK 0x10000 +#define NOC_PW_SET_BIT 0x1 + /* peri_crg ctrl */ #define CRGCTRL_PCIE_ASSERT_OFFSET 0x88 #define CRGCTRL_PCIE_ASSERT_BIT 0x8c000000 @@ -84,12 +144,21 @@ struct kirin_pcie { void __iomem *phy_base; struct regmap *crgctrl; struct regmap *sysctrl; + struct regmap *pmctrl; struct clk *apb_sys_clk; struct clk *apb_phy_clk; struct clk *phy_ref_clk; struct clk *pcie_aclk; struct clk *pcie_aux_clk; - int gpio_id_reset; + int gpio_id_reset[4]; + int gpio_id_clkreq[3]; + u32 eye_param[5]; +}; + +struct kirin_pcie_ops { + long (*get_resource)(struct kirin_pcie *kirin_pcie, + struct platform_device *pdev); + int (*power_on)(struct kirin_pcie *kirin_pcie); }; /* Registers in PCIeCTRL */ @@ -116,6 +185,28 @@ static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg) return readl(kirin_pcie->phy_base + reg); } +static inline void kirin970_apb_phy_writel(struct kirin_pcie *kirin_pcie, + u32 val, u32 reg) +{ + writel(val, kirin_pcie->phy_base + 0x40000 + reg); +} + +static inline u32 kirin970_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg) +{ + return readl(kirin_pcie->phy_base + 0x40000 + reg); +} + +static inline void kirin_apb_natural_phy_writel(struct kirin_pcie *kirin_pcie, + u32 val, u32 reg) +{ + writel(val, kirin_pcie->phy_base + reg * 4); +} + +static inline u32 kirin_apb_natural_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg) +{ + return readl(kirin_pcie->phy_base + reg * 4); +} + static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { @@ -144,9 +235,68 @@ static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie, return 0; } -static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, - struct platform_device *pdev) +void kirin970_pcie_get_eyeparam(struct kirin_pcie *pcie) { + struct device *dev = pcie->pci->dev; + int i; + struct device_node *np; + + np = dev->of_node; + + if (of_property_read_u32_array(np, "eye_param", pcie->eye_param, 5)) { + for (i = 0; i < 5; i++) + pcie->eye_param[i] = EYEPARAM_NOCFG; + } + + dev_dbg(dev, "eye_param_vboost = [0x%x]\n", pcie->eye_param[0]); + dev_dbg(dev, "eye_param_iboost = [0x%x]\n", pcie->eye_param[1]); + dev_dbg(dev, "eye_param_pre = [0x%x]\n", pcie->eye_param[2]); + dev_dbg(dev, "eye_param_post = [0x%x]\n", pcie->eye_param[3]); + dev_dbg(dev, "eye_param_main = [0x%x]\n", pcie->eye_param[4]); +} + +static void kirin970_pcie_set_eyeparam(struct kirin_pcie *kirin_pcie) +{ + u32 val; + + val = kirin_apb_natural_phy_readl(kirin_pcie, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1); + + if (kirin_pcie->eye_param[1] != EYEPARAM_NOCFG) { + val &= (~0xf00); + val |= (kirin_pcie->eye_param[1] << 8) | (0x1 << 12); + } + kirin_apb_natural_phy_writel(kirin_pcie, val, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1); + + val = kirin_apb_natural_phy_readl(kirin_pcie, LANEN_DIG_ASIC_TX_OVRD_IN_2); + val &= (~0x1FBF); + if (kirin_pcie->eye_param[2] != EYEPARAM_NOCFG) + val |= (kirin_pcie->eye_param[2]<< 0) | (0x1 << 6); + + if (kirin_pcie->eye_param[3] != EYEPARAM_NOCFG) + val |= (kirin_pcie->eye_param[3] << 7) | (0x1 << 13); + + kirin_apb_natural_phy_writel(kirin_pcie, val, LANEN_DIG_ASIC_TX_OVRD_IN_2); + + val = kirin_apb_natural_phy_readl(kirin_pcie, SUP_DIG_LVL_OVRD_IN); + if (kirin_pcie->eye_param[0] != EYEPARAM_NOCFG) { + val &= (~0x1C0); + val |= (kirin_pcie->eye_param[0] << 6) | (0x1 << 9); + } + kirin_apb_natural_phy_writel(kirin_pcie, val, SUP_DIG_LVL_OVRD_IN); + + val = kirin_apb_natural_phy_readl(kirin_pcie, LANEN_DIG_ASIC_TX_OVRD_IN_1); + if (kirin_pcie->eye_param[4] != EYEPARAM_NOCFG) { + val &= (~0x7E00); + val |= (kirin_pcie->eye_param[4] << 9) | (0x1 << 15); + } + kirin_apb_natural_phy_writel(kirin_pcie, val, LANEN_DIG_ASIC_TX_OVRD_IN_1); +} + +static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); if (IS_ERR(kirin_pcie->apb_base)) @@ -167,6 +317,122 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, if (IS_ERR(kirin_pcie->sysctrl)) return PTR_ERR(kirin_pcie->sysctrl); + kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, + "reset-gpios", 0); + if (kirin_pcie->gpio_id_reset[0] < 0) + return -ENODEV; + + return 0; +} + +static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *apb; + struct resource *phy; + struct resource *dbi; + int ret; + + apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb"); + kirin_pcie->apb_base = devm_ioremap_resource(dev, apb); + if (IS_ERR(kirin_pcie->apb_base)) + return PTR_ERR(kirin_pcie->apb_base); + + phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); + kirin_pcie->phy_base = devm_ioremap_resource(dev, phy); + if (IS_ERR(kirin_pcie->phy_base)) + return PTR_ERR(kirin_pcie->phy_base); + + dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi); + if (IS_ERR(kirin_pcie->pci->dbi_base)) + return PTR_ERR(kirin_pcie->pci->dbi_base); + + kirin970_pcie_get_eyeparam(kirin_pcie); + + kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, + "switch,reset-gpios", 0); + if (kirin_pcie->gpio_id_reset[0] < 0) + return -ENODEV; + + kirin_pcie->gpio_id_reset[1] = of_get_named_gpio(dev->of_node, + "eth,reset-gpios", 0); + if (kirin_pcie->gpio_id_reset[1] < 0) + return -ENODEV; + + kirin_pcie->gpio_id_reset[2] = of_get_named_gpio(dev->of_node, + "m_2,reset-gpios", 0); + if (kirin_pcie->gpio_id_reset[2] < 0) + return -ENODEV; + + kirin_pcie->gpio_id_reset[3] = of_get_named_gpio(dev->of_node, + "mini1,reset-gpios", 0); + if (kirin_pcie->gpio_id_reset[3] < 0) + return -ENODEV; + + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[0], + "pcie_switch_reset"); + if (ret) + return ret; + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[1], + "pcie_eth_reset"); + if (ret) + return ret; + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[2], + "pcie_m_2_reset"); + if (ret) + return ret; + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[3], + "pcie_mini1_reset"); + if (ret) + return ret; + + kirin_pcie->gpio_id_clkreq[0] = of_get_named_gpio(dev->of_node, + "eth,clkreq-gpios", 0); + if (kirin_pcie->gpio_id_clkreq[0] < 0) + return -ENODEV; + + kirin_pcie->gpio_id_clkreq[1] = of_get_named_gpio(dev->of_node, + "m_2,clkreq-gpios", 0); + if (kirin_pcie->gpio_id_clkreq[1] < 0) + return -ENODEV; + + kirin_pcie->gpio_id_clkreq[2] = of_get_named_gpio(dev->of_node, + "mini1,clkreq-gpios", 0); + if (kirin_pcie->gpio_id_clkreq[2] < 0) + return -ENODEV; + + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[0], + "pcie_eth_clkreq"); + if (ret) + return ret; + + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[1], + "pcie_m_2_clkreq"); + if (ret) + return ret; + + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[2], + "pcie_mini1_clkreq"); + if (ret) + return ret; + + kirin_pcie->crgctrl = + syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl"); + if (IS_ERR(kirin_pcie->crgctrl)) + return PTR_ERR(kirin_pcie->crgctrl); + + kirin_pcie->sysctrl = + syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl"); + if (IS_ERR(kirin_pcie->sysctrl)) + return PTR_ERR(kirin_pcie->sysctrl); + + kirin_pcie->pmctrl = + syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl"); + if (IS_ERR(kirin_pcie->sysctrl)) + return PTR_ERR(kirin_pcie->sysctrl); + return 0; } @@ -208,6 +474,21 @@ static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie) regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val); } +static int kirin970_pcie_clk_ctrl(struct clk *clk, int clk_on) +{ + int ret = 0; + + if (clk_on) { + ret = clk_prepare_enable(clk); + if (ret) + return ret; + } else { + clk_disable_unprepare(clk); + } + + return ret; +} + static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable) { int ret = 0; @@ -255,7 +536,401 @@ static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable) return ret; } -static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie) +static void kirin970_pcie_natural_cfg(struct kirin_pcie *kirin_pcie) +{ + u32 val; + + /* change 2p mem_ctrl */ + kirin_apb_ctrl_writel(kirin_pcie, 0x02605550, SOC_PCIECTRL_CTRL20_ADDR); + + /* pull up sys_aux_pwr_det */ + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL7_ADDR); + val |= (0x1 << 10); + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL7_ADDR); + + /* output, pull down */ + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL12_ADDR); + val &= ~(0x3 << 2); + val |= (0x1 << 1); + val &= ~(0x1 << 0); + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL12_ADDR); + + /* Handle phy_reset and lane0_reset to HW */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_CTRL1_ADDR); + val |= PCIEPHY_RESET_BIT; + val &= ~PCIEPHY_PIPE_LINE0_RESET_BIT; + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_CTRL1_ADDR); + + /* fix chip bug: TxDetectRx fail */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_CTRL38_ADDR); + val |= (0x1 << 2); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_CTRL38_ADDR); +} + +static void kirin970_pcie_pll_init(struct kirin_pcie *kirin_pcie) +{ + u32 val; + + /* choose FNPLL */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL1); + val |= (0x1 << 27); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL1); + + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL16); + val &= 0xF000FFFF; + /* fnpll fbdiv = 0xD0 */ + val |= (0xd0 << 16); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL16); + + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL17); + val &= 0xFF000000; + /* fnpll fracdiv = 0x555555 */ + val |= (0x555555 << 0); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL17); + + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL20); + val &= 0xF5FF88FF; + /* fnpll dll_en = 0x1 */ + val |= (0x1 << 27); + /* fnpll postdiv1 = 0x5 */ + val |= (0x5 << 8); + /* fnpll postdiv2 = 0x4 */ + val |= (0x4 << 12); + /* fnpll pll_mode = 0x0 */ + val &= ~(0x1 << 25); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL20); + + kirin970_apb_phy_writel(kirin_pcie, 0x20, SOC_PCIEPHY_MMC1PLL_CTRL21); +} + +static int kirin970_pcie_pll_ctrl(struct kirin_pcie *kirin_pcie, bool enable) +{ + struct device *dev = kirin_pcie->pci->dev; + u32 val; + int time = 200; + + if (enable) { + /* pd = 0 */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL16); + val &= ~(0x1 << 0); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL16); + + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_STAT0); + + /* choose FNPLL */ + while (!(val & 0x10)) { + if (!time) { + dev_err(dev, "wait for pll_lock timeout\n"); + return -1; + } + time --; + udelay(1); + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_STAT0); + } + + /* pciepll_bp = 0 */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL20); + val &= ~(0x1 << 16); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL20); + + } else { + /* pd = 1 */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL16); + val |= (0x1 << 0); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL16); + + /* pciepll_bp = 1 */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_MMC1PLL_CTRL20); + val |= (0x1 << 16); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_MMC1PLL_CTRL20); + } + + return 0; +} + +static void kirin970_pcie_hp_debounce_gt(struct kirin_pcie *kirin_pcie, bool open) +{ + if (open) + /* gt_clk_pcie_hp/gt_clk_pcie_debounce open */ + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PEREN12, 0x9000); + else + /* gt_clk_pcie_hp/gt_clk_pcie_debounce close */ + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PERDIS12, 0x9000); +} + +static void kirin970_pcie_phyref_gt(struct kirin_pcie *kirin_pcie, bool open) +{ + unsigned int val; + + regmap_read(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, &val); + + if (open) + val &= ~(0x1 << 1); //enable hard gt mode + else + val |= (0x1 << 1); //disable hard gt mode + + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, val); + + /* disable soft gt mode */ + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PERDIS12, 0x4000); +} + +static void kirin970_pcie_oe_ctrl(struct kirin_pcie *kirin_pcie, bool en_flag) +{ + unsigned int val; + + regmap_read(kirin_pcie->crgctrl , CRGPERIPH_PCIECTRL0, &val); + + /* set ie cfg */ + val |= IO_IE_EN_HARD_BYPASS; + + /* set oe cfg */ + val &= ~IO_HARD_CTRL_DEBOUNCE_BYPASS; + + /* set phy_debounce in&out time */ + val |= (DEBOUNCE_WAITCFG_IN | DEBOUNCE_WAITCFG_OUT); + + /* select oe_gt_mode */ + val |= IO_OE_GT_MODE; + + if (en_flag) + val &= ~IO_OE_EN_HARD_BYPASS; + else + val |= IO_OE_EN_HARD_BYPASS; + + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, val); +} + +static void kirin970_pcie_ioref_gt(struct kirin_pcie *kirin_pcie, bool open) +{ + unsigned int val; + + if (open) { + kirin_apb_ctrl_writel(kirin_pcie, 0x20000070, SOC_PCIECTRL_CTRL21_ADDR); + + kirin970_pcie_oe_ctrl(kirin_pcie, true); + + /* en hard gt mode */ + regmap_read(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, &val); + val &= ~(0x1 << 0); + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, val); + + /* disable soft gt mode */ + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PERDIS12, 0x2000); + + } else { + /* disable hard gt mode */ + regmap_read(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, &val); + val |= (0x1 << 0); + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PCIECTRL0, val); + + /* disable soft gt mode */ + regmap_write(kirin_pcie->crgctrl, CRGPERIPH_PERDIS12, 0x2000); + + kirin970_pcie_oe_ctrl(kirin_pcie, false); + } +} + +static int kirin970_pcie_allclk_ctrl(struct kirin_pcie *kirin_pcie, bool clk_on) +{ + struct device *dev = kirin_pcie->pci->dev; + u32 val; + int ret = 0; + + if (!clk_on) + goto ALL_CLOSE; + + /* choose 100MHz clk src: Bit[8]==1 pad, Bit[8]==0 pll */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_CTRL1_ADDR); + val &= ~(0x1 << 8); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_CTRL1_ADDR); + + kirin970_pcie_pll_init(kirin_pcie); + + ret = kirin970_pcie_pll_ctrl(kirin_pcie, true); + if (ret) { + dev_err(dev, "Failed to enable pll\n"); + return -1; + } + kirin970_pcie_hp_debounce_gt(kirin_pcie, true); + kirin970_pcie_phyref_gt(kirin_pcie, true); + kirin970_pcie_ioref_gt(kirin_pcie, true); + + ret = clk_set_rate(kirin_pcie->pcie_aclk, AXI_CLK_FREQ); + if (ret) { + dev_err(dev, "Failed to set rate\n"); + goto GT_CLOSE; + } + + ret = kirin970_pcie_clk_ctrl(kirin_pcie->pcie_aclk, true); + if (ret) { + dev_err(dev, "Failed to enable pcie_aclk\n"); + goto GT_CLOSE; + } + + ret = kirin970_pcie_clk_ctrl(kirin_pcie->pcie_aux_clk, true); + if (ret) { + dev_err(dev, "Failed to enable pcie_aux_clk\n"); + goto AUX_CLK_FAIL; + } + + return 0; + +ALL_CLOSE: + kirin970_pcie_clk_ctrl(kirin_pcie->pcie_aux_clk, false); +AUX_CLK_FAIL: + kirin970_pcie_clk_ctrl(kirin_pcie->pcie_aclk, false); +GT_CLOSE: + kirin970_pcie_ioref_gt(kirin_pcie, false); + kirin970_pcie_phyref_gt(kirin_pcie, false); + kirin970_pcie_hp_debounce_gt(kirin_pcie, false); + + kirin970_pcie_pll_ctrl(kirin_pcie, false); + + return ret; +} + +static bool is_pipe_clk_stable(struct kirin_pcie *kirin_pcie) +{ + struct device *dev = kirin_pcie->pci->dev; + u32 val; + u32 time = 100; + u32 pipe_clk_stable = 0x1 << 19; + + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_STATE0_ADDR); + while (val & pipe_clk_stable) { + mdelay(1); + if (time == 0) { + dev_err(dev, "PIPE clk is not stable\n"); + return false; + } + time--; + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_STATE0_ADDR); + } + + return true; +} + +static int kirin970_pcie_noc_power(struct kirin_pcie *kirin_pcie, bool enable) +{ + struct device *dev = kirin_pcie->pci->dev; + u32 time = 100; + unsigned int val = NOC_PW_MASK; + int rst; + + if (enable) + val = NOC_PW_MASK | NOC_PW_SET_BIT; + else + val = NOC_PW_MASK; + rst = enable ? 1 : 0; + + regmap_write(kirin_pcie->pmctrl, NOC_POWER_IDLEREQ_1, val); + + time = 100; + regmap_read(kirin_pcie->pmctrl, NOC_POWER_IDLE_1, &val); + while((val & NOC_PW_SET_BIT) != rst) { + udelay(10); + if (!time) { + dev_err(dev, "Failed to reverse noc power-status\n"); + return -1; + } + time--; + regmap_read(kirin_pcie->pmctrl, NOC_POWER_IDLE_1, &val); + } + + return 0; +} + +static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) +{ + struct device *dev = kirin_pcie->pci->dev; + int ret; + u32 val; + + /* Power supply for Host */ + regmap_write(kirin_pcie->sysctrl, + SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT); + usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); + kirin_pcie_oe_enable(kirin_pcie); + + ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[0], 0); + if (ret) + dev_err(dev, "Failed to pulse eth clkreq signal\n"); + + ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[1], 0); + if (ret) + dev_err(dev, "Failed to pulse m.2 clkreq signal\n"); + + ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[2], 0); + if (ret) + dev_err(dev, "Failed to pulse mini1 clkreq signal\n"); + + ret = kirin_pcie_clk_ctrl(kirin_pcie, true); + if (ret) + return ret; + + /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */ + regmap_write(kirin_pcie->sysctrl, + SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT); + regmap_write(kirin_pcie->crgctrl, + CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT); + regmap_write(kirin_pcie->sysctrl, + SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT); + + kirin970_pcie_natural_cfg(kirin_pcie); + + ret = kirin970_pcie_allclk_ctrl(kirin_pcie, true); + if (ret) + goto close_clk; + + /* pull down phy_test_powerdown signal */ + val = kirin970_apb_phy_readl(kirin_pcie, SOC_PCIEPHY_CTRL0_ADDR); + val &= ~(0x1 << 22); + kirin970_apb_phy_writel(kirin_pcie, val, SOC_PCIEPHY_CTRL0_ADDR); + + /* deassert controller perst_n */ + val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL12_ADDR); + val |= (0x1 << 2); + kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL12_ADDR); + udelay(10); + + /* perst assert Endpoints */ + usleep_range(21000, 23000); + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[0], 1); + if (ret) + goto close_clk; + + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[1], 1); + if (ret) + goto close_clk; + + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[2], 1); + if (ret) + goto close_clk; + + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[3], 1); + if (ret) + goto close_clk; + + usleep_range(10000, 11000); + + ret = is_pipe_clk_stable(kirin_pcie); + if (!ret) + goto close_clk; + + kirin970_pcie_set_eyeparam(kirin_pcie); + + ret = kirin970_pcie_noc_power(kirin_pcie, false); + if (ret) + goto close_clk; + + return 0; +close_clk: + kirin_pcie_clk_ctrl(kirin_pcie, false); + return ret; +} + +static int kirin960_pcie_power_on(struct kirin_pcie *kirin_pcie) { int ret; @@ -282,9 +957,9 @@ static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie) goto close_clk; /* perst assert Endpoint */ - if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) { + if (!gpio_request(kirin_pcie->gpio_id_reset[0], "pcie_perst")) { usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); - ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1); + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[0], 1); if (ret) goto close_clk; usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); @@ -419,11 +1094,29 @@ static const struct dw_pcie_host_ops kirin_pcie_host_ops = { .host_init = kirin_pcie_host_init, }; +struct kirin_pcie_ops kirin960_pcie_ops = { + .get_resource = kirin960_pcie_get_resource, + .power_on = kirin960_pcie_power_on, +}; + +struct kirin_pcie_ops kirin970_pcie_ops = { + .get_resource = kirin970_pcie_get_resource, + .power_on = kirin970_pcie_power_on, +}; + +static const struct of_device_id kirin_pcie_match[] = { + { .compatible = "hisilicon,kirin960-pcie", .data = &kirin960_pcie_ops }, + { .compatible = "hisilicon,kirin970-pcie", .data = &kirin970_pcie_ops }, + {}, +}; + static int kirin_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct kirin_pcie *kirin_pcie; struct dw_pcie *pci; + const struct of_device_id *of_id; + struct kirin_pcie_ops *ops; int ret; if (!dev->of_node) { @@ -431,6 +1124,9 @@ static int kirin_pcie_probe(struct platform_device *pdev) return -EINVAL; } + of_id = of_match_node(kirin_pcie_match, dev->of_node); + ops = (struct kirin_pcie_ops *)of_id->data; + kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL); if (!kirin_pcie) return -ENOMEM; @@ -448,20 +1144,20 @@ static int kirin_pcie_probe(struct platform_device *pdev) if (ret) return ret; - ret = kirin_pcie_get_resource(kirin_pcie, pdev); + ret = ops->get_resource(kirin_pcie, pdev); if (ret) return ret; - kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node, + kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, "reset-gpios", 0); - if (kirin_pcie->gpio_id_reset == -EPROBE_DEFER) { + if (kirin_pcie->gpio_id_reset[0] == -EPROBE_DEFER) { return -EPROBE_DEFER; - } else if (!gpio_is_valid(kirin_pcie->gpio_id_reset)) { + } else if (!gpio_is_valid(kirin_pcie->gpio_id_reset[0])) { dev_err(dev, "unable to get a valid gpio pin\n"); return -ENODEV; } - ret = kirin_pcie_power_on(kirin_pcie); + ret = ops->power_on(kirin_pcie); if (ret) return ret; @@ -470,11 +1166,6 @@ static int kirin_pcie_probe(struct platform_device *pdev) return dw_pcie_host_init(&pci->pp); } -static const struct of_device_id kirin_pcie_match[] = { - { .compatible = "hisilicon,kirin960-pcie" }, - {}, -}; - static struct platform_driver kirin_pcie_driver = { .probe = kirin_pcie_probe, .driver = { From patchwork Wed Feb 3 07:01:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063523 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17845C433E6 for ; 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Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 05/11] PCI: dwc: pcie-kirin: simplify error handling logic Date: Wed, 3 Feb 2021 08:01:49 +0100 Message-Id: <6298de2ed4384c2a3f012e9dedc101ae5f184ab2.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Instead of returning -ENODEV when of_get_named_gpio() fails, make it return the actual error code. With that, there's no need anymore to check for -EPROBE_DEFER at kirin_pcie_probe(). Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 5925d2b345a8..f46a51ffd2c8 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -320,7 +320,7 @@ static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, "reset-gpios", 0); if (kirin_pcie->gpio_id_reset[0] < 0) - return -ENODEV; + return kirin_pcie->gpio_id_reset[0]; return 0; } @@ -354,22 +354,22 @@ static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, "switch,reset-gpios", 0); if (kirin_pcie->gpio_id_reset[0] < 0) - return -ENODEV; + return kirin_pcie->gpio_id_reset[0]; kirin_pcie->gpio_id_reset[1] = of_get_named_gpio(dev->of_node, "eth,reset-gpios", 0); if (kirin_pcie->gpio_id_reset[1] < 0) - return -ENODEV; + return kirin_pcie->gpio_id_reset[1]; kirin_pcie->gpio_id_reset[2] = of_get_named_gpio(dev->of_node, "m_2,reset-gpios", 0); if (kirin_pcie->gpio_id_reset[2] < 0) - return -ENODEV; + return kirin_pcie->gpio_id_reset[2]; kirin_pcie->gpio_id_reset[3] = of_get_named_gpio(dev->of_node, "mini1,reset-gpios", 0); if (kirin_pcie->gpio_id_reset[3] < 0) - return -ENODEV; + return kirin_pcie->gpio_id_reset[3]; ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[0], "pcie_switch_reset"); @@ -1148,11 +1148,7 @@ static int kirin_pcie_probe(struct platform_device *pdev) if (ret) return ret; - kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, - "reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[0] == -EPROBE_DEFER) { - return -EPROBE_DEFER; - } else if (!gpio_is_valid(kirin_pcie->gpio_id_reset[0])) { + if (!gpio_is_valid(kirin_pcie->gpio_id_reset[0])) { dev_err(dev, "unable to get a valid gpio pin\n"); return -ENODEV; } From patchwork Wed Feb 3 07:01:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063513 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85233C43381 for ; Wed, 3 Feb 2021 07:03:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3BA1464F60 for ; Wed, 3 Feb 2021 07:03:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232046AbhBCHD3 (ORCPT ); Wed, 3 Feb 2021 02:03:29 -0500 Received: from mail.kernel.org ([198.145.29.99]:35490 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231733AbhBCHDY (ORCPT ); Wed, 3 Feb 2021 02:03:24 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7E50E64F6C; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335720; bh=zwb0Mth7eELiBcTxYlfdtlD0vrsPIqLk3jGGMShKrvQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XdoNItloIeoArk4MUx2zYkCAhvcYhv947i1IzqdN+/ZNB5S2ahUwEU9r7jgdtMM0a B62L8211BpsLwv5gcJSH+gUgXk2MI6btRR/jnFSX/dXeDJzQ8DOOe+gcVz0ra1xwdI yMjV7YYTB2742Zif3tzBoi5oKTDOmfrWdJGVM+EIDqlxNNlpKoPLjpgqIzJn47vX9F MPdoz+OPj6iS6ZCCUF+JSJQJtoFXwJ19DxFa5MRw6RK08fRsxhixRpxhevT2eB+5ZV pCqGZ2sHwq7PQZS3b0HGoP7jcL5WrtPBPJLQZGGfh49f7PuiQ+uta7DyKnKBy42S4W pCa6F4i0ZWvVQ== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAo-001CAb-6A; Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 06/11] PCI: dwc: pcie-kirin: simplify Kirin 970 get resource logic Date: Wed, 3 Feb 2021 08:01:50 +0100 Message-Id: <360a7aec5005ccb0ce3bed3795b848288286e3f2.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use devm_platform_ioremap_resource_byname() in order to simplify the logic and to make the logic for Kirin 970 similar to the one for Kirin 960. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index f46a51ffd2c8..e1ebe0747978 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -297,13 +297,13 @@ static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, { struct device *dev = &pdev->dev; - kirin_pcie->apb_base = - devm_platform_ioremap_resource_byname(pdev, "apb"); + kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, + "apb"); if (IS_ERR(kirin_pcie->apb_base)) return PTR_ERR(kirin_pcie->apb_base); - kirin_pcie->phy_base = - devm_platform_ioremap_resource_byname(pdev, "phy"); + kirin_pcie->phy_base = devm_platform_ioremap_resource_byname(pdev, + "phy"); if (IS_ERR(kirin_pcie->phy_base)) return PTR_ERR(kirin_pcie->phy_base); @@ -329,23 +329,20 @@ static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct resource *apb; - struct resource *phy; - struct resource *dbi; int ret; - apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb"); - kirin_pcie->apb_base = devm_ioremap_resource(dev, apb); + kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, + "apb"); if (IS_ERR(kirin_pcie->apb_base)) return PTR_ERR(kirin_pcie->apb_base); - phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); - kirin_pcie->phy_base = devm_ioremap_resource(dev, phy); + kirin_pcie->phy_base = devm_platform_ioremap_resource_byname(pdev, + "phy"); if (IS_ERR(kirin_pcie->phy_base)) return PTR_ERR(kirin_pcie->phy_base); - dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); - kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi); + kirin_pcie->pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, + "dbi"); if (IS_ERR(kirin_pcie->pci->dbi_base)) return PTR_ERR(kirin_pcie->pci->dbi_base); From patchwork Wed Feb 3 07:01:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063505 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7972BC433E6 for ; Wed, 3 Feb 2021 07:02:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E49264F67 for ; Wed, 3 Feb 2021 07:02:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231845AbhBCHCo (ORCPT ); Wed, 3 Feb 2021 02:02:44 -0500 Received: from mail.kernel.org ([198.145.29.99]:34050 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231659AbhBCHCl (ORCPT ); Wed, 3 Feb 2021 02:02:41 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 59F6B64F58; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335720; bh=aiSfGloGjZNBvqVkuwBAlS4U5H6KEaC6gLpGGLAMPa4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tj73VGPQysEec8IsoH6FwOU1UcsJVNL1MG8RzNtmfxB6fB9eDdqcEepaT0+oVSgvw wvJnWmhAG94UIWr2RFQJ+5x2W9jE8AX2P0KLg57/3XBdqiy6emkS2mYPu7+MIjDqL/ mIsbx0141Vpfq9zd8ERJGQmhxhNG8Sztp2xO2yXOPbszlltznt9l0OtcUazx/xDYxy BdfDjQhlwC1NtcniAXH63QpQ6dvOGF2s2kucTroJQjCIsra3S6+7alr91lqrHTTafq jLsSOi2/BqR9rGHeL/8gnF7qcWSPqyJap47+BsgdJa8/S2RUwJ1dB3Y/HHWAxJOu9b 3C1pKwFxb07RA== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAo-001CAd-73; Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 07/11] PCI: dwc: pcie-kirin: place common init code altogether Date: Wed, 3 Feb 2021 08:01:51 +0100 Message-Id: <768a60e538735a426c18c4fd1b3f95d53f678eac.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Both Kirin 960 and Kirin 970 need to do ioremap for apb, phy and dbi. So, use a shared code for those. It should be noticed that the dbi remap is now done by dwc core, so it can simply be removed from kirin970_pcie_get_resource(). Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 45 +++++++++++-------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index e1ebe0747978..2bce6e3750d4 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -292,21 +292,27 @@ static void kirin970_pcie_set_eyeparam(struct kirin_pcie *kirin_pcie) kirin_apb_natural_phy_writel(kirin_pcie, val, LANEN_DIG_ASIC_TX_OVRD_IN_1); } +static long kirin_common_pcie_get_resource(struct kirin_pcie *kirin_pcie, + struct platform_device *pdev) +{ + kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, + "apb"); + if (IS_ERR(kirin_pcie->apb_base)) + return PTR_ERR(kirin_pcie->apb_base); + + kirin_pcie->phy_base = devm_platform_ioremap_resource_byname(pdev, + "phy"); + if (IS_ERR(kirin_pcie->phy_base)) + return PTR_ERR(kirin_pcie->phy_base); + + return 0; +} + static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { struct device *dev = &pdev->dev; - kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, - "apb"); - if (IS_ERR(kirin_pcie->apb_base)) - return PTR_ERR(kirin_pcie->apb_base); - - kirin_pcie->phy_base = devm_platform_ioremap_resource_byname(pdev, - "phy"); - if (IS_ERR(kirin_pcie->phy_base)) - return PTR_ERR(kirin_pcie->phy_base); - kirin_pcie->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); if (IS_ERR(kirin_pcie->crgctrl)) @@ -331,21 +337,6 @@ static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct device *dev = &pdev->dev; int ret; - kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, - "apb"); - if (IS_ERR(kirin_pcie->apb_base)) - return PTR_ERR(kirin_pcie->apb_base); - - kirin_pcie->phy_base = devm_platform_ioremap_resource_byname(pdev, - "phy"); - if (IS_ERR(kirin_pcie->phy_base)) - return PTR_ERR(kirin_pcie->phy_base); - - kirin_pcie->pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, - "dbi"); - if (IS_ERR(kirin_pcie->pci->dbi_base)) - return PTR_ERR(kirin_pcie->pci->dbi_base); - kirin970_pcie_get_eyeparam(kirin_pcie); kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, @@ -1141,6 +1132,10 @@ static int kirin_pcie_probe(struct platform_device *pdev) if (ret) return ret; + ret = kirin_common_pcie_get_resource(kirin_pcie, pdev); + if (ret) + return ret; + ret = ops->get_resource(kirin_pcie, pdev); if (ret) return ret; From patchwork Wed Feb 3 07:01:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063521 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F2D6C433E0 for ; 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Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 08/11] PCI: dwc: pcie-kirin: add support for a regulator Date: Wed, 3 Feb 2021 08:01:52 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Kirin 970 designs, a power supply is required to enable a PCI bridge and other components of the board. For instance, on HiKey 970, the Hi6421v600 regulator provides a power line (LDO33) which powers on the PCI bridge, the M.2 slot, the mini PCIe 1x slot and the Realtek 8169 Ethernet card. Without enabling such power supply, the PCI resource allocation fails. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 2bce6e3750d4..005fc4c2ad7f 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include "pcie-designware.h" @@ -335,8 +336,21 @@ static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct regulator *reg; int ret; + reg = devm_regulator_get(dev, "pcie_vdd"); + if (IS_ERR_OR_NULL(reg)) { + if (PTR_ERR(reg) == -EPROBE_DEFER) + return PTR_ERR(reg); + } else { + ret = regulator_enable(reg); + if (ret) { + dev_err(dev, "Failed to enable regulator\n"); + return ret; + } + } + kirin970_pcie_get_eyeparam(kirin_pcie); kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, From patchwork Wed Feb 3 07:01:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063509 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47ABCC433E0 for ; Wed, 3 Feb 2021 07:03:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B5B864F65 for ; Wed, 3 Feb 2021 07:03:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231778AbhBCHDI (ORCPT ); Wed, 3 Feb 2021 02:03:08 -0500 Received: from mail.kernel.org ([198.145.29.99]:34088 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231722AbhBCHCl (ORCPT ); Wed, 3 Feb 2021 02:02:41 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7546E64F67; Wed, 3 Feb 2021 07:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1612335720; bh=Ak/SRsEmbodWMQWHFspw9muj+HO1Me4jb6bnXOYqzhE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MqG0svQLWL7rHYbDeySYu4wgCVEuodKSDui116khReRU58QCixf8ZBSBO8bGNlJQV pR/ss9sTK1VDSUj/yv7yBT+3BUTGXPUE0jOCZ3kPZUmrnPcMerlaxpwOXTeTNeMQ+V aq3oqEqI1htL2PQOMw+uuUN2esIJyzvQkn8GC7sajNMm7Cc2TlWBix5lcSUagpZsTh EQh7LlXejZxF4ysQyNoujMNhyLYkQ2zuTYb5dFVFS1a+Cn30UjZwPOAZ5pm/P/+vao BQwshIEhIRI8SEi5dKC2371Q2wh9sLyt8RBOsNJpuyo0RS8vodg9NlNmUORMkVvE1H 4sYS54piqf6lQ== Received: by mail.kernel.org with local (Exim 4.94) (envelope-from ) id 1l7CAo-001CAi-8c; Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Liam Girdwood , Lorenzo Pieralisi , Mark Brown , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 09/11] PCI: dwc: pcie-kirin: allow using multiple reset GPIOs Date: Wed, 3 Feb 2021 08:01:53 +0100 Message-Id: <4fb97b1fc3fe6df9a2fea8f96bdef433e75463a6.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On HiKey 970, the PCI hardware contains a bridge (PEX 8606), an Ethernet controller (RTL8169), a M.2 connector and a mini 1X connector. They work out of the box, but each of them requires its own reset line, which should be initialized when the PCI hardware is reset. So, add support for the DTS to contain multiple reset lines. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 148 +++++++++++++----------- 1 file changed, 79 insertions(+), 69 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 005fc4c2ad7f..4124c6ace349 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -139,6 +139,7 @@ #define TIME_PHY_PD_MIN 10 #define TIME_PHY_PD_MAX 11 +#define MAX_GPIO_RESETS 4 struct kirin_pcie { struct dw_pcie *pci; void __iomem *apb_base; @@ -151,8 +152,10 @@ struct kirin_pcie { struct clk *phy_ref_clk; struct clk *pcie_aclk; struct clk *pcie_aux_clk; - int gpio_id_reset[4]; + int n_gpio_resets; int gpio_id_clkreq[3]; + int gpio_id_reset[MAX_GPIO_RESETS]; + const char *reset_names[MAX_GPIO_RESETS]; u32 eye_param[5]; }; @@ -296,6 +299,24 @@ static void kirin970_pcie_set_eyeparam(struct kirin_pcie *kirin_pcie) static long kirin_common_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct regulator *reg; + char name[32]; + int ret, i; + + reg = devm_regulator_get_optional(dev, "pci"); + if (IS_ERR_OR_NULL(reg)) { + if (PTR_ERR(reg) == -EPROBE_DEFER) + return PTR_ERR(reg); + } else { + ret = regulator_enable(reg); + if (ret) { + dev_err(dev, "Failed to enable regulator\n"); + return ret; + } + } + kirin_pcie->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb"); if (IS_ERR(kirin_pcie->apb_base)) @@ -306,14 +327,47 @@ static long kirin_common_pcie_get_resource(struct kirin_pcie *kirin_pcie, if (IS_ERR(kirin_pcie->phy_base)) return PTR_ERR(kirin_pcie->phy_base); + kirin_pcie->n_gpio_resets = of_gpio_named_count(np, "reset-gpios"); + if (kirin_pcie->n_gpio_resets > MAX_GPIO_RESETS) { + dev_err(dev, "Too many GPIO resets!\n"); + return -EINVAL; + } + for (i = 0; i < kirin_pcie->n_gpio_resets; i++) { + kirin_pcie->gpio_id_reset[i] = of_get_named_gpio(dev->of_node, + "reset-gpios", i); + if (kirin_pcie->gpio_id_reset[i] < 0) + return kirin_pcie->gpio_id_reset[i]; + + sprintf(name, "pcie_perst_%d", i); + kirin_pcie->reset_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!kirin_pcie->reset_names[i]) + return -ENOMEM; + } + return 0; } +static int kirin_gpio_request(struct kirin_pcie *kirin_pcie, + struct device *dev) +{ + int ret, i; + + for (i = 0; i < kirin_pcie->n_gpio_resets; i++) { + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[i], + kirin_pcie->reset_names[i]); + if (ret) + return ret; + } + + + return ret; +} + + static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { - struct device *dev = &pdev->dev; - kirin_pcie->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); if (IS_ERR(kirin_pcie->crgctrl)) @@ -324,16 +378,11 @@ static long kirin960_pcie_get_resource(struct kirin_pcie *kirin_pcie, if (IS_ERR(kirin_pcie->sysctrl)) return PTR_ERR(kirin_pcie->sysctrl); - kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, - "reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[0] < 0) - return kirin_pcie->gpio_id_reset[0]; - return 0; } static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, - struct platform_device *pdev) + struct platform_device *pdev) { struct device *dev = &pdev->dev; struct regulator *reg; @@ -353,40 +402,7 @@ static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, kirin970_pcie_get_eyeparam(kirin_pcie); - kirin_pcie->gpio_id_reset[0] = of_get_named_gpio(dev->of_node, - "switch,reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[0] < 0) - return kirin_pcie->gpio_id_reset[0]; - - kirin_pcie->gpio_id_reset[1] = of_get_named_gpio(dev->of_node, - "eth,reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[1] < 0) - return kirin_pcie->gpio_id_reset[1]; - - kirin_pcie->gpio_id_reset[2] = of_get_named_gpio(dev->of_node, - "m_2,reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[2] < 0) - return kirin_pcie->gpio_id_reset[2]; - - kirin_pcie->gpio_id_reset[3] = of_get_named_gpio(dev->of_node, - "mini1,reset-gpios", 0); - if (kirin_pcie->gpio_id_reset[3] < 0) - return kirin_pcie->gpio_id_reset[3]; - - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[0], - "pcie_switch_reset"); - if (ret) - return ret; - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[1], - "pcie_eth_reset"); - if (ret) - return ret; - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[2], - "pcie_m_2_reset"); - if (ret) - return ret; - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_reset[3], - "pcie_mini1_reset"); + ret = kirin_gpio_request(kirin_pcie, dev); if (ret) return ret; @@ -846,7 +862,7 @@ static int kirin970_pcie_noc_power(struct kirin_pcie *kirin_pcie, bool enable) static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) { struct device *dev = kirin_pcie->pci->dev; - int ret; + int ret, i; u32 val; /* Power supply for Host */ @@ -898,22 +914,11 @@ static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) /* perst assert Endpoints */ usleep_range(21000, 23000); - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[0], 1); - if (ret) - goto close_clk; - - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[1], 1); - if (ret) - goto close_clk; - - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[2], 1); - if (ret) - goto close_clk; - - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[3], 1); - if (ret) - goto close_clk; - + for (i = 0; i < kirin_pcie->n_gpio_resets; i++) { + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[i], 1); + if (ret) + return ret; + } usleep_range(10000, 11000); ret = is_pipe_clk_stable(kirin_pcie); @@ -934,6 +939,7 @@ static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) static int kirin960_pcie_power_on(struct kirin_pcie *kirin_pcie) { + struct device *dev = kirin_pcie->pci->dev; int ret; /* Power supply for Host */ @@ -959,15 +965,19 @@ static int kirin960_pcie_power_on(struct kirin_pcie *kirin_pcie) goto close_clk; /* perst assert Endpoint */ - if (!gpio_request(kirin_pcie->gpio_id_reset[0], "pcie_perst")) { - usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); - ret = gpio_direction_output(kirin_pcie->gpio_id_reset[0], 1); - if (ret) - goto close_clk; - usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); - - return 0; - } + ret = kirin_gpio_request(kirin_pcie, dev); + if (ret) + goto close_clk; + + usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX); + + ret = gpio_direction_output(kirin_pcie->gpio_id_reset[0], 1); + if (ret) + goto close_clk; + + usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX); + + return 0; close_clk: kirin_pcie_clk_ctrl(kirin_pcie, false); From patchwork Wed Feb 3 07:01:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063503 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57F41C433E0 for ; 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Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 10/11] PCI: dwc: pcie-kirin: add support for clkreq GPIOs Date: Wed, 3 Feb 2021 08:01:54 +0100 Message-Id: X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The hardware on Kirin 970 designs use external components as part of their PCIe hardware support. Fo instance, in the case of HiKey 970, it has separate clkreq lines that are needed to be enabled on its PCIe bridge, Ethernet chip and even at the M.2 connector hardware. Those should be enabled during PCIe hardware power on logic, as otherwise the resource allocation will fail. Add support for them. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 77 +++++++++++-------------- 1 file changed, 34 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 4124c6ace349..c5404f1eca28 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -140,6 +140,8 @@ #define TIME_PHY_PD_MAX 11 #define MAX_GPIO_RESETS 4 +#define MAX_GPIO_CLKREQ 3 + struct kirin_pcie { struct dw_pcie *pci; void __iomem *apb_base; @@ -153,9 +155,11 @@ struct kirin_pcie { struct clk *pcie_aclk; struct clk *pcie_aux_clk; int n_gpio_resets; - int gpio_id_clkreq[3]; + int n_gpio_clkreq; int gpio_id_reset[MAX_GPIO_RESETS]; const char *reset_names[MAX_GPIO_RESETS]; + int gpio_id_clkreq[MAX_GPIO_CLKREQ]; + const char *clkreq_names[MAX_GPIO_CLKREQ]; u32 eye_param[5]; }; @@ -345,6 +349,24 @@ static long kirin_common_pcie_get_resource(struct kirin_pcie *kirin_pcie, return -ENOMEM; } + kirin_pcie->n_gpio_clkreq = of_gpio_named_count(np, "clkreq-gpios"); + if (kirin_pcie->n_gpio_clkreq > MAX_GPIO_CLKREQ) { + dev_err(dev, "Too many GPIO clock requests!\n"); + return -EINVAL; + } + for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) { + kirin_pcie->gpio_id_clkreq[i] = of_get_named_gpio(dev->of_node, + "clkreq-gpios", i); + if (kirin_pcie->gpio_id_clkreq[i] < 0) + return kirin_pcie->gpio_id_clkreq[i]; + + sprintf(name, "pcie_clkreq_%d", i); + kirin_pcie->clkreq_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!kirin_pcie->clkreq_names[i]) + return -ENOMEM; + } + return 0; } @@ -360,6 +382,12 @@ static int kirin_gpio_request(struct kirin_pcie *kirin_pcie, return ret; } + for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) { + ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[i], + kirin_pcie->clkreq_names[i]); + if (ret) + return ret; + } return ret; } @@ -406,36 +434,6 @@ static long kirin970_pcie_get_resource(struct kirin_pcie *kirin_pcie, if (ret) return ret; - kirin_pcie->gpio_id_clkreq[0] = of_get_named_gpio(dev->of_node, - "eth,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[0] < 0) - return -ENODEV; - - kirin_pcie->gpio_id_clkreq[1] = of_get_named_gpio(dev->of_node, - "m_2,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[1] < 0) - return -ENODEV; - - kirin_pcie->gpio_id_clkreq[2] = of_get_named_gpio(dev->of_node, - "mini1,clkreq-gpios", 0); - if (kirin_pcie->gpio_id_clkreq[2] < 0) - return -ENODEV; - - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[0], - "pcie_eth_clkreq"); - if (ret) - return ret; - - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[1], - "pcie_m_2_clkreq"); - if (ret) - return ret; - - ret = devm_gpio_request(dev, kirin_pcie->gpio_id_clkreq[2], - "pcie_mini1_clkreq"); - if (ret) - return ret; - kirin_pcie->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl"); if (IS_ERR(kirin_pcie->crgctrl)) @@ -861,7 +859,6 @@ static int kirin970_pcie_noc_power(struct kirin_pcie *kirin_pcie, bool enable) static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) { - struct device *dev = kirin_pcie->pci->dev; int ret, i; u32 val; @@ -871,17 +868,11 @@ static int kirin970_pcie_power_on(struct kirin_pcie *kirin_pcie) usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX); kirin_pcie_oe_enable(kirin_pcie); - ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[0], 0); - if (ret) - dev_err(dev, "Failed to pulse eth clkreq signal\n"); - - ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[1], 0); - if (ret) - dev_err(dev, "Failed to pulse m.2 clkreq signal\n"); - - ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[2], 0); - if (ret) - dev_err(dev, "Failed to pulse mini1 clkreq signal\n"); + for (i = 0; i < kirin_pcie->n_gpio_clkreq; i++) { + ret = gpio_direction_output(kirin_pcie->gpio_id_clkreq[i], 0); + if (ret) + return ret; + } ret = kirin_pcie_clk_ctrl(kirin_pcie, true); if (ret) From patchwork Wed Feb 3 07:01:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 12063515 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AD78C433E6 for ; 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Wed, 03 Feb 2021 08:01:58 +0100 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Xiaowei Song , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 11/11] pci: dwc: pcie-kirin: cleanup kirin970_pcie_get_eyeparam() Date: Wed, 3 Feb 2021 08:01:55 +0100 Message-Id: <1584b35df936f50bb3187c233b9110c53652a518.1612335031.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Cleanup the routine, to let it clearer that eye_param is optional and that, if not specified, the driver will assume the default. While here, also drop the useless debug prints. Signed-off-by: Mauro Carvalho Chehab --- drivers/pci/controller/dwc/pcie-kirin.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index c5404f1eca28..88f10aff8b09 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -246,21 +246,18 @@ static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie, void kirin970_pcie_get_eyeparam(struct kirin_pcie *pcie) { struct device *dev = pcie->pci->dev; - int i; struct device_node *np; + int ret, i; np = dev->of_node; - if (of_property_read_u32_array(np, "eye_param", pcie->eye_param, 5)) { - for (i = 0; i < 5; i++) + ret = of_property_read_u32_array(np, "eye_param", pcie->eye_param, 5); + if (!ret) + return; + + /* There's no optional eye_param property. Set array to default */ + for (i = 0; i < 5; i++) pcie->eye_param[i] = EYEPARAM_NOCFG; - } - - dev_dbg(dev, "eye_param_vboost = [0x%x]\n", pcie->eye_param[0]); - dev_dbg(dev, "eye_param_iboost = [0x%x]\n", pcie->eye_param[1]); - dev_dbg(dev, "eye_param_pre = [0x%x]\n", pcie->eye_param[2]); - dev_dbg(dev, "eye_param_post = [0x%x]\n", pcie->eye_param[3]); - dev_dbg(dev, "eye_param_main = [0x%x]\n", pcie->eye_param[4]); } static void kirin970_pcie_set_eyeparam(struct kirin_pcie *kirin_pcie)