From patchwork Wed Feb 3 10:26:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 12063935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3632BC43333 for ; Wed, 3 Feb 2021 10:28:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F1D5A64DF2 for ; Wed, 3 Feb 2021 10:28:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233912AbhBCK2Q (ORCPT ); Wed, 3 Feb 2021 05:28:16 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:15410 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233840AbhBCK1i (ORCPT ); Wed, 3 Feb 2021 05:27:38 -0500 X-UUID: 4f3509ed5a864599ae31313abd2c1798-20210203 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=oRQwwEBqC4tKIu7cXvamzV8CPVw7VRwU+JGP2zYTRyU=; b=VNzHi5FwcNFawbvb3kelq0+m02Q+mqSnGRZozUL+EB6RQ8tOSMoszXr89xzvmXC5EuBmGjCmsMMnf3PMbUvFVRO90qNJC/sT3KPNijEPQsb04Y3LI4ykrBeyK7mwXYJotMBao7c2AQFnyqg7HutZmU9nzENKb/HmO1zEKgNbqLo=; X-UUID: 4f3509ed5a864599ae31313abd2c1798-20210203 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1460794024; Wed, 03 Feb 2021 18:26:52 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 3 Feb 2021 18:26:46 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 3 Feb 2021 18:26:46 +0800 From: Chunfeng Yun To: Rob Herring , Matthias Brugger , Mathias Nyman CC: Greg Kroah-Hartman , , , , , , Ikjoon Jang , Nicolas Boichat , Chunfeng Yun Subject: [RFC PATCH v2 1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195 Date: Wed, 3 Feb 2021 18:26:40 +0800 Message-ID: <20210203102642.7353-1-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: B45C9A23E638F617A8804501C1C14A4441E4A31D6616F8B7CF5DFAD9D9CF1FB82000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we should set the accurate interval according to 48Mhz. Here add a new compatible for MT8195, it's also supported in driver. But the first controller (IP0) has no such issue, we prefer to use generic compatible, e.g. mt8192's compatible. Signed-off-by: Chunfeng Yun Acked-by: Rob Herring --- v2: no changes --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt index 42d8814f903a..02cba4212f7d 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt @@ -16,6 +16,7 @@ Required properties: "mediatek,mtk-xhci" compatible string, you need SoC specific ones in addition, one of: - "mediatek,mt8173-xhci" + - "mediatek,mt8195-xhci" - reg : specifies physical base address and size of the registers - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control - interrupts : interrupt used by the controller From patchwork Wed Feb 3 10:26:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 12063933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F969C433E9 for ; Wed, 3 Feb 2021 10:28:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE39264E38 for ; Wed, 3 Feb 2021 10:28:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233863AbhBCK1w (ORCPT ); Wed, 3 Feb 2021 05:27:52 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:36954 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233694AbhBCK1f (ORCPT ); Wed, 3 Feb 2021 05:27:35 -0500 X-UUID: 109044f3a5c24026a4f5930e4b0eaccf-20210203 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qJXyUkhTG3EiVikkkhafwsut5EHurgvUe+hMMeVXd64=; b=dnXVX1CYwJ4CMKrJYba4h/XDMwcANiwlJNop0YS7rA8ksPjSd55Yfm2RU5+Bw/82EJmsTGnOU8bnwRh3GBrzS0rOvzxdJ9iA8DTPuBGI8P7PP/cK62joq/xd1efg4pWLFzoNoLGesHCBDw9Sc0S136Lh17jGLgbpJ5D9/588zWo=; X-UUID: 109044f3a5c24026a4f5930e4b0eaccf-20210203 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 328501113; Wed, 03 Feb 2021 18:26:51 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 3 Feb 2021 18:26:46 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 3 Feb 2021 18:26:46 +0800 From: Chunfeng Yun To: Rob Herring , Matthias Brugger , Mathias Nyman CC: Greg Kroah-Hartman , , , , , , Ikjoon Jang , Nicolas Boichat , Chunfeng Yun Subject: [RFC PATCH v2 2/3] usb: xhci-mtk: modify the SOF/ITP interval for mt8195 Date: Wed, 3 Feb 2021 18:26:41 +0800 Message-ID: <20210203102642.7353-2-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210203102642.7353-1-chunfeng.yun@mediatek.com> References: <20210203102642.7353-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 69C95C417298EC51AE23FB6CAB8FFF25126E6644A83787837E3078CAF3F85B592000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we should set the accurate interval according to 48Mhz for those controllers. Note: the first controller no need set it. Signed-off-by: Chunfeng Yun --- v2: fix typo of comaptible --- drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index 8f321f39ab96..0a68c4ac8b48 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -68,11 +68,71 @@ #define SSC_IP_SLEEP_EN BIT(4) #define SSC_SPM_INT_EN BIT(1) +/* xHCI csr */ +#define LS_EOF 0x930 +#define LS_EOF_OFFSET 0x89 + +#define FS_EOF 0x934 +#define FS_EOF_OFFSET 0x2e + +#define SS_GEN1_EOF 0x93c +#define SS_GEN1_EOF_OFFSET 0x78 + +#define HFCNTR_CFG 0x944 +#define ITP_DELTA_CLK (0xa << 1) +#define ITP_DELTA_CLK_MASK GENMASK(5, 1) +#define FRMCNT_LEV1_RANG (0x12b << 8) +#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8) + +#define SS_GEN2_EOF 0x990 +#define SS_GEN2_EOF_OFFSET 0x3c +#define EOF_OFFSET_MASK GENMASK(11, 0) + enum ssusb_uwk_vers { SSUSB_UWK_V1 = 1, SSUSB_UWK_V2, }; +/* + * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval + * is calculated from the frame counter clock 24M, but in fact, the clock + * is 48M, so need change the interval. + */ +static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk) +{ + struct device *dev = mtk->dev; + struct usb_hcd *hcd = mtk->hcd; + u32 value; + + if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci")) + return; + + value = readl(hcd->regs + HFCNTR_CFG); + value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK); + value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG); + writel(value, hcd->regs + HFCNTR_CFG); + + value = readl(hcd->regs + LS_EOF); + value &= ~EOF_OFFSET_MASK; + value |= LS_EOF_OFFSET; + writel(value, hcd->regs + LS_EOF); + + value = readl(hcd->regs + FS_EOF); + value &= ~EOF_OFFSET_MASK; + value |= FS_EOF_OFFSET; + writel(value, hcd->regs + FS_EOF); + + value = readl(hcd->regs + SS_GEN1_EOF); + value &= ~EOF_OFFSET_MASK; + value |= SS_GEN1_EOF_OFFSET; + writel(value, hcd->regs + SS_GEN1_EOF); + + value = readl(hcd->regs + SS_GEN2_EOF); + value &= ~EOF_OFFSET_MASK; + value |= SS_GEN2_EOF_OFFSET; + writel(value, hcd->regs + SS_GEN2_EOF); +} + static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) { struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; @@ -407,6 +467,8 @@ static int xhci_mtk_setup(struct usb_hcd *hcd) ret = xhci_mtk_ssusb_config(mtk); if (ret) return ret; + + xhci_mtk_set_frame_interval(mtk); } ret = xhci_gen_setup(hcd, xhci_mtk_quirks); @@ -655,6 +717,7 @@ static const struct dev_pm_ops xhci_mtk_pm_ops = { #ifdef CONFIG_OF static const struct of_device_id mtk_xhci_of_match[] = { { .compatible = "mediatek,mt8173-xhci"}, + { .compatible = "mediatek,mt8195-xhci"}, { .compatible = "mediatek,mtk-xhci"}, { }, }; From patchwork Wed Feb 3 10:26:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 12063937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A02AEC4332E for ; Wed, 3 Feb 2021 10:28:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 68EE364E38 for ; Wed, 3 Feb 2021 10:28:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233671AbhBCK2J (ORCPT ); Wed, 3 Feb 2021 05:28:09 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:54928 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233773AbhBCK1h (ORCPT ); Wed, 3 Feb 2021 05:27:37 -0500 X-UUID: 95a42418049a4c368d6b7d0d801cb796-20210203 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=P6HkMNngDEu0ovs7YYGRzlSjmF2Z+miarHYHEVeGcuA=; b=ErSpRwkk+90JI1AWve2UDGzcNiTEgSoRy2Y/nXKWSZOXx8qVBTdkqivOAAAOdTptYj1zqUQc6x7bEVHUdwIq7kMYB/Doqcuh1MBKFP/a0N7mmCZ+OGRGAL7ogkcCrSH/SDjcVTZ5HI6FDnW8s5VjsvmyLuD46Qb2lUikXu8zIlQ=; X-UUID: 95a42418049a4c368d6b7d0d801cb796-20210203 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1134430158; Wed, 03 Feb 2021 18:26:51 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 3 Feb 2021 18:26:47 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 3 Feb 2021 18:26:47 +0800 From: Chunfeng Yun To: Rob Herring , Matthias Brugger , Mathias Nyman CC: Greg Kroah-Hartman , , , , , , Ikjoon Jang , Nicolas Boichat , Chunfeng Yun Subject: [RFC PATCH v2 3/3] arm64: dts: mt8195: add USB related nodes Date: Wed, 3 Feb 2021 18:26:42 +0800 Message-ID: <20210203102642.7353-3-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210203102642.7353-1-chunfeng.yun@mediatek.com> References: <20210203102642.7353-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 4801882163939865DB0AE9CB9384AE084FE94C5432E8984B4432855FD9A416BB2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add USB nodes, PHY nodes and some fixed regulator nodes. We prefer to use mt8192's compatible for the first USB controller (port0), there is no wrong with the SOF/ITP interval; but for other controllers (port1~port3) should use mt8195's one due to the wrong default setting of SOF/ITP interval which should be calculated from 48M, but not 24M by default. Signed-off-by: Chunfeng Yun --- v2: no changes --- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 70 +++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 163 ++++++++++++++++++++ 2 files changed, 233 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index 7264232bb7e9..a60682752e19 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "mt8195.dtsi" #include "mt6359.dtsi" +#include / { model = "MediaTek MT8195 evaluation board"; @@ -49,6 +50,36 @@ enable-active-high; regulator-always-on; }; + + usb_p0_vbus: regulator@2 { + compatible = "regulator-fixed"; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; + + usb_p2_vbus: regulator@3 { + compatible = "regulator-fixed"; + gpio = <&pio 131 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; + + usb_p3_vbus: regulator@4 { + compatible = "regulator-fixed"; + gpio = <&pio 5 GPIO_ACTIVE_HIGH>; + regulator-name = "vbus3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + }; }; &pmic { @@ -156,6 +187,22 @@ status = "okay"; }; +&u3phy0 { + status="okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status="okay"; +}; + +&u3phy3 { + status="okay"; +}; + &pio { nor_pins_default: nordefault { pins0 { @@ -311,3 +358,26 @@ }; }; + +&xhci0 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_p0_vbus>; + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_p2_vbus>; + status = "okay"; +}; + +&xhci3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_p3_vbus>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index ccb9d24b1c1e..60c75b23cf03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -914,6 +915,83 @@ status = "disabled"; }; + xhci0: usb@11200000 { + compatible = "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>, + <&topckgen CLK_TOP_SSUSB_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + + xhci1: usb@11290000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11290000 0 0x1000>, + <0 0x11293e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_1P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_1P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P1_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + + xhci2: usb@112a0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112a0000 0 0x1000>, + <0 0x112a3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port2 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_2P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_2P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P2_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + + xhci3: usb@112b0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port3 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_3P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_3P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P3_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + pcie0: pcie@112f0000 { device_type = "pci"; compatible = "mediatek,mt8195-pcie"; @@ -998,6 +1076,40 @@ status = "disabled"; }; + u3phy2: usb-phy2@11c40000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c40000 0x700>; + status = "disabled"; + + u2port2: usb2-phy2@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + u3phy3: usb-phy3@11c50000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x700>; + status = "disabled"; + + u2port3: usb2-phy3@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + i2c5: i2c5@11d00000 { compatible = "mediatek,mt8195-i2c", "mediatek,mt8192-i2c"; @@ -1138,6 +1250,57 @@ #clock-cells = <1>; }; + u3phy1: usb-phy1@11e30000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e30000 0x1000>; + status = "disabled"; + + u2port1: usb2-phy1@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb3-phy1@700 { + reg = <0x700 0x900>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + u3phy0: usb-phy0@11e40000 { + compatible = "mediatek,mt8195-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e40000 0x1000>; + status = "disabled"; + + u2port0: usb2-phy0@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb3-phy0@700 { + reg = <0x700 0 0x900>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + pciephy: phy@11e80000 { compatible = "mediatek,mt8195-pcie-phy"; #address-cells = <2>;