From patchwork Wed Nov 14 10:56:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Faggioli X-Patchwork-Id: 10682353 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7CBA513BB for ; Wed, 14 Nov 2018 10:59:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6EED92ADE8 for ; Wed, 14 Nov 2018 10:59:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6106A2AE63; Wed, 14 Nov 2018 10:59:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 059012ADE8 for ; Wed, 14 Nov 2018 10:59:29 +0000 (UTC) Received: from localhost ([::1]:59467 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMstM-0005DF-Dq for patchwork-qemu-devel@patchwork.kernel.org; Wed, 14 Nov 2018 05:59:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33146) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMsqm-000321-MD for qemu-devel@nongnu.org; Wed, 14 Nov 2018 05:56:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMsqj-0007ws-0j for qemu-devel@nongnu.org; Wed, 14 Nov 2018 05:56:48 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:55411) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gMsqi-0007vs-QT for qemu-devel@nongnu.org; Wed, 14 Nov 2018 05:56:44 -0500 Received: by mail-wm1-f66.google.com with SMTP id i73-v6so9689308wmd.5 for ; Wed, 14 Nov 2018 02:56:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=S0twy0PVPP3duPNkDv9U15J+RGIRtaCPW0bjLDfEDC4=; b=i6+4ZEYhsI2oY8NJs/JiJ0MdtiZXQTOKCWwZwB//Ili90bJE5AtRa0UbDb+tu1/SNC rXeQWS2x/CWhBBcF359/GqGMgBucfAiZxjweAsH2PqBCYGVB9VqAKJ84FTvugavNoM9G USBzxTUmyuA5E+VTNmlG8SsvgLK8cgLM70eZZFibgFr5ANd/N+BK0HbkNzVeK5+EOYZS RYFdJE9QcX5JmbGKc4AU/3aoKCN+F0SmmUjWlZ4Q3RWPZdMHvsu3TzeRqTqkOmIlH04V 8JfjjMV/58VyhffplMsvNyhxr3Bj4o0EAcnBIvaZmYrOYWaOtIipWdlJHDMgpLBSUC2c yqdw== X-Gm-Message-State: AGRZ1gKNgaYsjB9JyIy1VA9lMM4IudxBWOouX/9DMQIOLxWwZRc6hbjo flmZKPAgVQ9T+2JpQPHGmV8= X-Google-Smtp-Source: AJdET5fuwt7fMcH9Ha8doxD4DD4Z51vPz9cHoiaMA4SR4VxpxlE20Pf1bIPd4UnldxJbqkRTikUXxA== X-Received: by 2002:a7b:c083:: with SMTP id r3-v6mr1463036wmh.101.1542192999095; Wed, 14 Nov 2018 02:56:39 -0800 (PST) Received: from [127.0.0.1] (96-210-66-80.hosts.abilene.it. [80.66.210.96]) by smtp.gmail.com with ESMTPSA id x2-v6sm15019671wrw.42.2018.11.14.02.56.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Nov 2018 02:56:38 -0800 (PST) From: Dario Faggioli To: qemu-devel@nongnu.org Date: Wed, 14 Nov 2018 11:56:54 +0100 Message-ID: <154219301447.19470.4834273682384554888.stgit@wayrath> In-Reply-To: <154219299016.19470.9372139354280787961.stgit@wayrath> References: <154219299016.19470.9372139354280787961.stgit@wayrath> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.66 Subject: [Qemu-devel] [RFC PATCH 1/3] i386: add properties for customizing L2 and L3 caches size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Make it possible to specify a custom size for the L2 and L3 caches, from the command line. This can be useful in cases where applications or libraries check, within the guest, the cache size and behave differently depending on what they actually see. Signed-off-by: Dario Faggioli --- I am not entirely sure I got the include/hw/i386 bits right (i.e., whether I should include the new properties in PC_COMPAT_3_0 and, if yes, if the stanzas are correct). I'll dig further (and accept any help/advice :-D ) --- Cc: "Michael S. Tsirkin" Cc: Marcel Apfelbaum Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost --- 0 files changed diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 136fe497b6..1094bba68c 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -308,6 +308,14 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,\ .property = "pku",\ .value = "off",\ + },{\ + .driver = TYPE_X86_CPU,\ + .property = "l3-cache-size",\ + .value = "off",\ + },{\ + .driver = TYPE_X86_CPU,\ + .property = "l2-cache-size",\ + .value = "off",\ }, #define PC_COMPAT_2_12 \ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f81d35e1f9..b8ccb2be04 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5778,6 +5778,14 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, false), + + /* + * Custom size for L2 and/or L3 cache. Default (0) means we use the + * default value for the CPU. + */ + DEFINE_PROP_SIZE("l2-cache-size", X86CPU, l2_cache_size, 0), + DEFINE_PROP_SIZE("l3-cache-size", X86CPU, l3_cache_size, 0), + DEFINE_PROP_END_OF_LIST() }; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9c52d0cbeb..ba0b913448 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1476,6 +1476,9 @@ struct X86CPU { int32_t core_id; int32_t thread_id; + uint64_t l2_cache_size; + uint64_t l3_cache_size; + int32_t hv_max_vps; }; From patchwork Wed Nov 14 10:57:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Faggioli X-Patchwork-Id: 10682351 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E003B1709 for ; Wed, 14 Nov 2018 10:58:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D230D2978F for ; Wed, 14 Nov 2018 10:58:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C68712997A; Wed, 14 Nov 2018 10:58:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B770E2978F for ; Wed, 14 Nov 2018 10:58:11 +0000 (UTC) Received: from localhost ([::1]:59455 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMss7-0004Pc-4L for patchwork-qemu-devel@patchwork.kernel.org; Wed, 14 Nov 2018 05:58:11 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMsqx-00039W-TX for qemu-devel@nongnu.org; Wed, 14 Nov 2018 05:57:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMsqm-0007xx-DG for qemu-devel@nongnu.org; Wed, 14 Nov 2018 05:56:55 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:46790) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gMsql-0007xS-Si for qemu-devel@nongnu.org; Wed, 14 Nov 2018 05:56:48 -0500 Received: by mail-wr1-f67.google.com with SMTP id l9so3876703wrt.13 for ; Wed, 14 Nov 2018 02:56:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=pOG+EZxr7+WbAbeqxvYU403kCPWA7FhfD0as/JuGO1w=; b=Yzu1D+/aMvKz0iJaSFScTl6lavUoLHw1A7Nf+vVEjw2QEUhmZj+Fgaqn/vRwFWXSnF 9znm6CS3AqwiK99C9EdFS8uZwsL99ss4LLIlrEwmowpwgr7BrNUMnzEIBCA+sSADYRRP uJcWimo/WlG4XqXtFMTAgWkNxCPhjsTFmih3yVWMesCnjkTJK7bhJrlj/6OoKZzqqgN7 x0nHke+NhSU0eKqBpVUCa7tYxnxMcG6OSi5qunW1hnDSGYhXfrEQpXAbiC9m2fIGAsMH W9JuRJoKa+PmlqoN+yBLD/FvIsTIIhV1FEBRQlqZ2mRmlD1u69gDUktACo1NTA/oIuZE vPtw== X-Gm-Message-State: AGRZ1gJNrtlLN5a4GBBJIE81y2Ex/j/Uw+oV0OTXmQVqXtR9J08JQ5Lw 9AgTzVh/6Ur0D1PusXVRrmk= X-Google-Smtp-Source: AJdET5dyEA1vTJpcgv5Bo/l/0TsclMBmWSoPFTvVrVy1QfSXdug3HT9oB50jqsCRwxsS1pYiajb2Ag== X-Received: by 2002:adf:eb48:: with SMTP id u8-v6mr1291085wrn.22.1542193006551; Wed, 14 Nov 2018 02:56:46 -0800 (PST) Received: from [127.0.0.1] (96-210-66-80.hosts.abilene.it. [80.66.210.96]) by smtp.gmail.com with ESMTPSA id t4-v6sm10649106wrb.67.2018.11.14.02.56.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Nov 2018 02:56:45 -0800 (PST) From: Dario Faggioli To: qemu-devel@nongnu.org Date: Wed, 14 Nov 2018 11:57:02 +0100 Message-ID: <154219302196.19470.10725052065694275300.stgit@wayrath> In-Reply-To: <154219299016.19470.9372139354280787961.stgit@wayrath> References: <154219299016.19470.9372139354280787961.stgit@wayrath> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.67 Subject: [Qemu-devel] [RFC PATCH 2/3] i386: custom cache size in CPUID2 and CPUID4 descriptors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP If specified on the command line, alter the cache(s) properties accordingly, before encoding them in the CPUID descriptors. Tweak the number of sets (if defined), to retain consistency. Unless some specific size values are used (either by chance or voluntarily), we won't find any matching CPUID-2 descriptor, and 0xFF will be used. This shouldn't be a problem, as we have CPUID-4. Signed-off-by: Dario Faggioli --- I'm no CPUID expert. I'm not sure I've fully understodd the relationship between CPUID-2 and CPUID-4. The solution implemented here, is the best I could come up with, and it worked on all the CPU types that I've tried. If it's wrong/suboptimal, I'm happy to think to something else/rework. --- Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost --- 0 files changed diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b8ccb2be04..17aff19561 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -426,6 +426,24 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); } +static void set_custom_cache_size(CPUCacheInfo *c, uint64_t sz) +{ + /* + * Descriptors that have 'sets', also have 'partitions' initialized, + * so we can compute the new number of sets. For others, just tweak the + * size. + */ + assert(c->partitions > 0 || c->sets == 0); + if (c->sets > 0) { + uint32_t sets = sz / (c->line_size * c->associativity * c->partitions); + + if (sets == 0) + return; + c->sets = sets; + } + c->size = sz; +} + /* Data structure to hold the configuration info for a given core index */ struct core_topology { /* core complex id of the current core index */ @@ -4193,8 +4211,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (!cpu->enable_l3_cache) { *ecx = 0; } else { + if (cpu->l3_cache_size > 0) + set_custom_cache_size(env->cache_info_cpuid2.l3_cache, + cpu->l3_cache_size); *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); } + if (cpu->l2_cache_size > 0) + set_custom_cache_size(env->cache_info_cpuid2.l2_cache, + cpu->l2_cache_size); *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); @@ -4222,6 +4246,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + if (cpu->l2_cache_size > 0) + set_custom_cache_size(env->cache_info_cpuid4.l2_cache, + cpu->l2_cache_size); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, cs->nr_threads, cs->nr_cores, eax, ebx, ecx, edx); @@ -4229,6 +4256,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, case 3: /* L3 cache info */ pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads); if (cpu->enable_l3_cache) { + if (cpu->l3_cache_size > 0) + set_custom_cache_size(env->cache_info_cpuid4.l3_cache, + cpu->l3_cache_size); encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, (1 << pkg_offset), cs->nr_cores, eax, ebx, ecx, edx); From patchwork Wed Nov 14 10:57:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Faggioli X-Patchwork-Id: 10682355 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B839D13BF for ; Wed, 14 Nov 2018 11:00:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A81C42B3AD for ; Wed, 14 Nov 2018 11:00:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C2E92B3BC; Wed, 14 Nov 2018 11:00:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 360C32B3B6 for ; Wed, 14 Nov 2018 11:00:43 +0000 (UTC) Received: from localhost ([::1]:59475 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMsuZ-0005uh-BQ for patchwork-qemu-devel@patchwork.kernel.org; Wed, 14 Nov 2018 06:00:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33225) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gMsr5-0003Ey-3Y for qemu-devel@nongnu.org; Wed, 14 Nov 2018 05:57:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gMsr1-00083p-Tc for qemu-devel@nongnu.org; Wed, 14 Nov 2018 05:57:07 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:50906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gMsqz-0007zI-Pz for qemu-devel@nongnu.org; Wed, 14 Nov 2018 05:57:03 -0500 Received: by mail-wm1-f65.google.com with SMTP id 124-v6so15068777wmw.0 for ; Wed, 14 Nov 2018 02:56:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=JUdUD+YhsYNwA7UqdptYtOmTpt+DoJexbYK9RmQ1lg0=; b=G06WcAbhGdGH04AmNspRKW6O9zN26MMZs9lm7zCtKNUUgsweR8dG94iJGw5dzy+oGv TAQRdR/jGymMm+SttOTWR+Oib1zVO/RwUH6sDqcfGLO7Du1u26e88fXS287MD3j9w11w lXekCZU81gc/GWL1RFKqARkcwzsX+4v3dhvFJYD6ffoSzD/opWKnwRaAbSJ5xBOWJD+o ZS1HOjJ7P3op5Kc+Vw3Ep7oc9Z1VyHa9StWDrKxMKILqAcSvMUs6Z0IRrV76ZsXIYFRj 5bliieNbZCNgA1+TN2Yo91zKxYQvr6gG/m3QZ7LCsK5Zej+ItB4OUXOgbAz2tKBLn9Q5 DZ9g== X-Gm-Message-State: AGRZ1gITHn08O2yU8a6GkdxAp+Viu6RqcjRVnFWG9W0oGIOec1bCahZ2 0Vuhzsb+/eE+JTQ+SPz1HNg= X-Google-Smtp-Source: AJdET5d9cfc/ELZAHfDsM3/GiNBdQ40jXcDf4I+l2p69OvYg/trU/7M1T1UqvFDU34nAzrvS3b238g== X-Received: by 2002:a1c:6555:: with SMTP id z82-v6mr1503964wmb.66.1542193013904; Wed, 14 Nov 2018 02:56:53 -0800 (PST) Received: from [127.0.0.1] (96-210-66-80.hosts.abilene.it. [80.66.210.96]) by smtp.gmail.com with ESMTPSA id y19sm5478737wmj.2.2018.11.14.02.56.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Nov 2018 02:56:53 -0800 (PST) From: Dario Faggioli To: qemu-devel@nongnu.org Date: Wed, 14 Nov 2018 11:57:09 +0100 Message-ID: <154219302946.19470.14979106134197499918.stgit@wayrath> In-Reply-To: <154219299016.19470.9372139354280787961.stgit@wayrath> References: <154219299016.19470.9372139354280787961.stgit@wayrath> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.65 Subject: [Qemu-devel] [RFC PATCH 3/3] i386: custom cache size in AMD's CPUID descriptors too X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Eduardo Habkost , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP If specified on the command line, alter the cache size(s) properties accordingly, before encoding them in the AMD's CPUID cache descriptors too (i.e., 80000006 and 8000001d). Signed-off-by: Dario Faggioli --- Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost --- 0 files changed diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 17aff19561..4949d6b907 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4490,6 +4490,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, (L2_DTLB_4K_ENTRIES << 16) | \ (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ (L2_ITLB_4K_ENTRIES); + if (cpu->l2_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l2_cache, + cpu->l2_cache_size); + if (cpu->enable_l3_cache && cpu->l3_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l3_cache, + cpu->l3_cache_size); encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, cpu->enable_l3_cache ? env->cache_info_amd.l3_cache : NULL, @@ -4546,10 +4552,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + if (cpu->l2_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l2_cache, + cpu->l2_cache_size * MiB); encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ + if (cpu->enable_l3_cache && cpu->l3_cache_size > 0) + set_custom_cache_size(env->cache_info_amd.l3_cache, + cpu->l3_cache_size * MiB); encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, eax, ebx, ecx, edx); break;