From patchwork Tue Feb 9 18:14:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12078767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81832C433DB for ; Tue, 9 Feb 2021 18:13:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2340164E3F for ; Tue, 9 Feb 2021 18:13:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2340164E3F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8CE4D6E0F3; Tue, 9 Feb 2021 18:13:23 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id D4C456E0F3 for ; Tue, 9 Feb 2021 18:13:21 +0000 (UTC) IronPort-SDR: ozPICk6Vyc5vDA4oZotId7d9G8oiHsnwUOWPrnK6NBuaVT9iiTlTI+zArnvN6pu+AfVa80V9Nz o/NCZ3dIC5sg== X-IronPort-AV: E=McAfee;i="6000,8403,9890"; a="201014103" X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="201014103" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:21 -0800 IronPort-SDR: k17xPZCRfAofdlRVsiQY6xVdLFdpe2ZtOEUaPSz58zy4vTMSYy+umGlUVOEAh0I2lug6gcnciI 35LPanXJLd8A== X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="396324631" Received: from rmahmood-mobl1.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.190.123]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:19 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 9 Feb 2021 10:14:36 -0800 Message-Id: <20210209181439.215104-1-jose.souza@intel.com> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/display: Rename for_each_intel_encoder.*_can_psr to for_each_intel_encoder.*_with_psr X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" for_each_intel_encoder.*_"can_psr" sounds strange, in my opinion "with_psr" is better. Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display.h | 4 ++-- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 6 +++--- drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++------ drivers/gpu/drm/i915/i915_irq.c | 4 ++-- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index e3757ecabbf7..c60a58ba60ee 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -418,7 +418,7 @@ enum phy_fia { for_each_if((encoder_mask) & \ drm_encoder_mask(&intel_encoder->base)) -#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \ +#define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \ list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \ intel_encoder_can_psr(intel_encoder)) @@ -427,7 +427,7 @@ enum phy_fia { for_each_intel_encoder(dev, intel_encoder) \ for_each_if(intel_encoder_is_dp(intel_encoder)) -#define for_each_intel_encoder_can_psr(dev, intel_encoder) \ +#define for_each_intel_encoder_with_psr(dev, intel_encoder) \ for_each_intel_encoder((dev), (intel_encoder)) \ for_each_if(intel_encoder_can_psr(intel_encoder)) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index d6e4a9237bda..7ce11d851163 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -437,7 +437,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) return -ENODEV; /* Find the first EDP which supports PSR */ - for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) { + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { intel_dp = enc_to_intel_dp(encoder); break; } @@ -459,7 +459,7 @@ i915_edp_psr_debug_set(void *data, u64 val) if (!HAS_PSR(dev_priv)) return ret; - for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) { + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val); @@ -484,7 +484,7 @@ i915_edp_psr_debug_get(void *data, u64 *val) if (!HAS_PSR(dev_priv)) return -ENODEV; - for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) { + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); // TODO: split to each transcoder's PSR debug state diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index bf214d0e2dec..1d3903612fcb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1232,8 +1232,8 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st !crtc_state->enable_psr2_sel_fetch) return; - for_each_intel_encoder_mask_can_psr(&dev_priv->drm, encoder, - crtc_state->uapi.encoder_mask) { + for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, + crtc_state->uapi.encoder_mask) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (!intel_dp->psr.enabled) @@ -1515,8 +1515,8 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state) if (!new_crtc_state->has_psr) return; - for_each_intel_encoder_mask_can_psr(&dev_priv->drm, encoder, - new_crtc_state->uapi.encoder_mask) { + for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, + new_crtc_state->uapi.encoder_mask) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u32 psr_status; @@ -1730,7 +1730,7 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv, if (origin == ORIGIN_FLIP) return; - for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) { + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { unsigned int pipe_frontbuffer_bits = frontbuffer_bits; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -1802,7 +1802,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, { struct intel_encoder *encoder; - for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) { + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { unsigned int pipe_frontbuffer_bits = frontbuffer_bits; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 98145a7f28a4..8f6b60661a4d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2096,7 +2096,7 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, if (de_iir & DE_EDP_PSR_INT_HSW) { struct intel_encoder *encoder; - for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) { + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u32 psr_iir = intel_uncore_read(&dev_priv->uncore, @@ -2323,7 +2323,7 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) u32 psr_iir; i915_reg_t iir_reg; - for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) { + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (INTEL_GEN(dev_priv) >= 12) From patchwork Tue Feb 9 18:14:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12078769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD2E2C433E0 for ; Tue, 9 Feb 2021 18:13:27 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 55D0C64EC9 for ; Tue, 9 Feb 2021 18:13:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 55D0C64EC9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CEF066EB8B; Tue, 9 Feb 2021 18:13:26 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 208B96E0F3 for ; Tue, 9 Feb 2021 18:13:23 +0000 (UTC) IronPort-SDR: DXokVzZHVFjPJ+7DZedqMrxz4CUcAwMwxGoSgiRwONy0A5mT8ix2DWknKlsye/mA+wwHjKRXU1 h34Dhd01nktg== X-IronPort-AV: E=McAfee;i="6000,8403,9890"; a="201014107" X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="201014107" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:22 -0800 IronPort-SDR: I5/9uAeU8d01b1MTVFxMQ554Dc2c2WM1ZL+n6T2LdBgW4G+RS8kqDvdkqjvD9QRuLp2RUdI/5y 94saE96d7bmA== X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="396324660" Received: from rmahmood-mobl1.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.190.123]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:21 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 9 Feb 2021 10:14:37 -0800 Message-Id: <20210209181439.215104-2-jose.souza@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209181439.215104-1-jose.souza@intel.com> References: <20210209181439.215104-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/display: Only write to register in intel_psr2_program_trans_man_trk_ctl() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" There is no support for two pipes one transcoder for PSR and if we had that the current code should not use cpu_transcoder. Also I can't see a scenario where crtc_state->enable_psr2_sel_fetch is set and PSR is not enabled and if by a bug it happens PSR HW will just ignore any value in set in PSR2_MAN_TRK_CTL. So dropping all the rest and keeping the same behavior that we have with intel_psr2_program_plane_sel_fetch(). Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1d3903612fcb..8ad9fcff3a12 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1226,23 +1226,13 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - struct intel_encoder *encoder; if (!HAS_PSR2_SEL_FETCH(dev_priv) || !crtc_state->enable_psr2_sel_fetch) return; - for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, - crtc_state->uapi.encoder_mask) { - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - - if (!intel_dp->psr.enabled) - continue; - - intel_de_write(dev_priv, - PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), - crtc_state->psr2_man_track_ctl); - } + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder), + crtc_state->psr2_man_track_ctl); } static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, From patchwork Tue Feb 9 18:14:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12078771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AF60C433DB for ; Tue, 9 Feb 2021 18:13:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9D26564E3F for ; Tue, 9 Feb 2021 18:13:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9D26564E3F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 28F646EB91; Tue, 9 Feb 2021 18:13:28 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 847056EB92 for ; Tue, 9 Feb 2021 18:13:27 +0000 (UTC) IronPort-SDR: 26ok/s3NJ/A6RWCSdBPR5wIK1/KV3de9Wunz10ir2ve9t1mHat/NbrR/ztLyzw5VRIjFqtYO2L KRb2XPPGrSWg== X-IronPort-AV: E=McAfee;i="6000,8403,9890"; a="201014108" X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="201014108" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:25 -0800 IronPort-SDR: oUOsSKnbl4h3l3+hKcnqlPrR2iW3kBsG7CSkI43yB2CxfbcXpC/Bnv4y2E545TgBUWnPbte1R0 2gjGxE+1eTvA== X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="396324686" Received: from rmahmood-mobl1.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.190.123]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:23 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 9 Feb 2021 10:14:38 -0800 Message-Id: <20210209181439.215104-3-jose.souza@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209181439.215104-1-jose.souza@intel.com> References: <20210209181439.215104-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/display: Remove some redundancy around CAN_PSR() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" If source_support is set the platform supports PSR so no need to check it again at every CAN_PSR(). Also removing the intel_dp_is_edp() calls, if sink_support is set the sink connected is for sure a eDP panel. Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_display_types.h | 5 ++--- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ebaa9d0ed376..4a46c4e9b0ac 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1793,9 +1793,8 @@ dp_to_i915(struct intel_dp *intel_dp) return to_i915(dp_to_dig_port(intel_dp)->base.base.dev); } -#define CAN_PSR(intel_dp) (HAS_PSR(dp_to_i915(intel_dp)) && \ - (intel_dp)->psr.sink_support && \ - (intel_dp)->psr.source_support) +#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ + (intel_dp)->psr.source_support) static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 4f89e0de5dde..0a0cc61344c4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2358,7 +2358,7 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, return false; } - if (CAN_PSR(intel_dp) && intel_dp_is_edp(intel_dp)) { + if (CAN_PSR(intel_dp)) { drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n"); crtc_state->uapi.mode_changed = true; return false; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8ad9fcff3a12..e0111b470570 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1962,7 +1962,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | DP_PSR_LINK_CRC_ERROR; - if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp)) + if (!CAN_PSR(intel_dp)) return; mutex_lock(&psr->lock); @@ -2012,7 +2012,7 @@ bool intel_psr_enabled(struct intel_dp *intel_dp) { bool ret; - if (!CAN_PSR(intel_dp) || !intel_dp_is_edp(intel_dp)) + if (!CAN_PSR(intel_dp)) return false; mutex_lock(&intel_dp->psr.lock); From patchwork Tue Feb 9 18:14:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12078773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EEB8C433E0 for ; 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a="201014110" X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="201014110" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:27 -0800 IronPort-SDR: p6U4SN4OuS5zR0MNn+paCTJ1eSBtyyqAEDnMIVfq8XzQbAU+pdvuU4F2rameZcTQCMX+P48TaO ubBSE8safSag== X-IronPort-AV: E=Sophos;i="5.81,165,1610438400"; d="scan'208";a="396324723" Received: from rmahmood-mobl1.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.190.123]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 10:13:25 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Tue, 9 Feb 2021 10:14:39 -0800 Message-Id: <20210209181439.215104-4-jose.souza@intel.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209181439.215104-1-jose.souza@intel.com> References: <20210209181439.215104-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/display: Set source_support even if panel do not support PSR X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This will set the right value of source_support when the port encoder/port supports PSR but sink don't. This change will also be needed in future for panel replay as psr struct needs to be initialized even if disconnected or current sink don't support PSR. Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index e0111b470570..6b3e2120161e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1837,9 +1837,6 @@ void intel_psr_init(struct intel_dp *intel_dp) if (!HAS_PSR(dev_priv)) return; - if (!intel_dp->psr.sink_support) - return; - /* * HSW spec explicitly says PSR is tied to port A. * BDW+ platforms have a instance of PSR registers per transcoder but