From patchwork Thu Feb 11 05:22:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12082293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8052C433DB for ; Thu, 11 Feb 2021 05:24:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 83BBC64E7C for ; Thu, 11 Feb 2021 05:24:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229512AbhBKFYA (ORCPT ); Thu, 11 Feb 2021 00:24:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229585AbhBKFXz (ORCPT ); Thu, 11 Feb 2021 00:23:55 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E290FC061788 for ; Wed, 10 Feb 2021 21:22:34 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id cl8so2778782pjb.0 for ; Wed, 10 Feb 2021 21:22:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aYhUIVZutNA2/DQTvTyK77zrU/arYQJ7jJF49VHfkCY=; b=r4mHvsGoZpB5DMubHMYTxmD1dmTAvgR9loBhGV68jfCSYU27ybvZ7EpKwZQIoOYOiH udvnTpjvUPlf6jVlaeP8myBglx+UzjHDEvgxuvqgCck09iaZpIq7eOkjk292M0l1yizL MBxRa8sYNzV7AygsLImPBIcIbmdIIdD7tn8fE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aYhUIVZutNA2/DQTvTyK77zrU/arYQJ7jJF49VHfkCY=; b=b2hlTd2MRIMoIS0ddI1ro7Fwr/ZHTX3vXZu9VHKrfN7fSAs5qxWcYgvil1wb2Xwh9C 7Rrqrk+iJ3pTVtGPlahAwGf4T5rYZReNjUHuSCkEIMVkoVNupTPxZsaU+fvX6cnL1g+N nnRAKMvRsB+j3tnMrnbk6PqZemIqPhHEX9iqDFCObSbN8vHVSHjfxknx6ptoHiLGp+67 IJApvzFyOqHyIbrzlaT2H6GHR5OtMqrmb1tISC+XoU6ODnqg3FdVpIs/YUHKoBEbOzRY RKQ2KTSVFIaLWcLxXbATWMD6CrSqxs89Ux7ISdC4rxNYfsDcBK5zfMvcAQRTHAXHtcx0 oVgQ== X-Gm-Message-State: AOAM532s2ozZPhZbcmn9P/RPbHiY2d+b70zF6xocBFr2tBFcmGLaiMTM /Tq430rBDf2/GQymOra/0RNlDmkqfLgxT3jV X-Google-Smtp-Source: ABdhPJx8H+6qwzrCS6BOEeFVn/RIWDSDyrwQHo84KFhcRbLlxzCUq1Yj8tIPobXq/XKRyLHHk/sT3w== X-Received: by 2002:a17:90a:bf10:: with SMTP id c16mr2339540pjs.101.1613020954311; Wed, 10 Feb 2021 21:22:34 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id o21sm3493511pjp.42.2021.02.10.21.22.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 21:22:34 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org Cc: w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer , Rob Herring Subject: [PATCH v2 1/7] dt-bindings: clk: mstar msc313 mpll binding header Date: Thu, 11 Feb 2021 14:22:00 +0900 Message-Id: <20210211052206.2955988-2-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210211052206.2955988-1-daniel@0x0f.com> References: <20210211052206.2955988-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Simple header to document the relationship between the MPLL outputs and which divider they come from. Output 0 is missing because it should not be consumed. Signed-off-by: Daniel Palmer Acked-by: Rob Herring --- MAINTAINERS | 1 + include/dt-bindings/clock/mstar-msc313-mpll.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 include/dt-bindings/clock/mstar-msc313-mpll.h diff --git a/MAINTAINERS b/MAINTAINERS index 64c7169db617..0622ff96ca2a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2149,6 +2149,7 @@ F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ F: drivers/gpio/gpio-msc313.c +F: include/dt-bindings/clock/mstar-* F: include/dt-bindings/gpio/msc313-gpio.h ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT diff --git a/include/dt-bindings/clock/mstar-msc313-mpll.h b/include/dt-bindings/clock/mstar-msc313-mpll.h new file mode 100644 index 000000000000..1b30b02317b6 --- /dev/null +++ b/include/dt-bindings/clock/mstar-msc313-mpll.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Output definitions for the MStar/SigmaStar MPLL + * + * Copyright (C) 2020 Daniel Palmer + */ + +#ifndef _DT_BINDINGS_CLOCK_MSTAR_MSC313_MPLL_H +#define _DT_BINDINGS_CLOCK_MSTAR_MSC313_MPLL_H + +#define MSTAR_MSC313_MPLL_DIV2 1 +#define MSTAR_MSC313_MPLL_DIV3 2 +#define MSTAR_MSC313_MPLL_DIV4 3 +#define MSTAR_MSC313_MPLL_DIV5 4 +#define MSTAR_MSC313_MPLL_DIV6 5 +#define MSTAR_MSC313_MPLL_DIV7 6 +#define MSTAR_MSC313_MPLL_DIV10 7 + +#endif From patchwork Thu Feb 11 05:22:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12082295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF550C433E9 for ; Thu, 11 Feb 2021 05:24:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C81F764DE7 for ; Thu, 11 Feb 2021 05:24:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229585AbhBKFYB (ORCPT ); Thu, 11 Feb 2021 00:24:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229692AbhBKFX4 (ORCPT ); Thu, 11 Feb 2021 00:23:56 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19913C06178C for ; Wed, 10 Feb 2021 21:22:37 -0800 (PST) Received: by mail-pl1-x635.google.com with SMTP id b8so2721209plh.12 for ; Wed, 10 Feb 2021 21:22:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AogpeLuC6h2kbFRYh8jcxM2VMpLXaY9SBeWFYBbrCSA=; b=qemjCONMGzAQ0NwTu3cqoW70NuUDn+rAE++LbZMHgRYAkzC3ZjriXPCHEL1nsC+e8k XlkeRggIgE9Y1wJcFeFWB0SXButixlGaBGIRn/qgK3XKgWtEUgaJBtOfSKHKOkRpnAy9 HJJrybQubhkyq8srL5lq26fpkNB4K8I88ydcA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AogpeLuC6h2kbFRYh8jcxM2VMpLXaY9SBeWFYBbrCSA=; b=UCgUXFcRD8GXyGDX/NEh0ocQH8z5ByKu/HAGUukKVpCEijEHp52EvpCSEyGChLdeF5 fBUQEOJgRkRW4Ha38/q6nQS0qo44fRpASJNRetZx7JUe24sJEiQqFTJkjZhllZL0YW8e EpfMl+RrOfwinvNKCo1lFwYSVPQzjFOJS0beHH+7kaieS1TTEn+h9CER8oyRu3iqAInu FjHlvqjxKqrsEh61EjznmODFS4pwrhpmqwyzeuuqQpcnbjIvQfpQoRI7hWdTTzA8T8It wO4v+hzulmyTVUOJNES6R3GE265B18G5P8TYe48Qql9/OuQpyKg01cGP+os9uMFP8ALN QDwA== X-Gm-Message-State: AOAM530/RFbHavZcvodIckKAIdot2ojCTzjmBPlnwFKylgMxwWxZnwnS EMHmcjlKeY+HfW3yamuj/vYcV/QJ3OjOthcl X-Google-Smtp-Source: ABdhPJy2wFjME1q+iuw0xrlRvsS0mzOVToh4DLZZpe6O9KBDNwverFfIK2xGmM4pNCocfDDhCQ9WNQ== X-Received: by 2002:a17:90a:bf0c:: with SMTP id c12mr2446478pjs.36.1613020956478; Wed, 10 Feb 2021 21:22:36 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id o21sm3493511pjp.42.2021.02.10.21.22.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 21:22:36 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org Cc: w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH v2 2/7] dt-bindings: clk: mstar msc313 mpll binding description Date: Thu, 11 Feb 2021 14:22:01 +0900 Message-Id: <20210211052206.2955988-3-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210211052206.2955988-1-daniel@0x0f.com> References: <20210211052206.2955988-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a binding description for the MStar/SigmaStar MPLL clock block. Signed-off-by: Daniel Palmer --- .../bindings/clock/mstar,msc313-mpll.yaml | 46 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml new file mode 100644 index 000000000000..0df5d75d4ebc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/Sigmastar MSC313 MPLL + +maintainers: + - Daniel Palmer + +description: | + The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that + takes the external xtal input and multiplies it to create a high + frequency clock and divides that down into a number of clocks that + peripherals use. + +properties: + compatible: + const: mstar,msc313-mpll + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + mpll@206000 { + compatible = "mstar,msc313-mpll"; + reg = <0x206000 0x200>; + #clock-cells = <1>; + clocks = <&xtal>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 0622ff96ca2a..d004436c8860 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2145,6 +2145,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar/* +F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ From patchwork Thu Feb 11 05:22:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12082297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E44EC433DB for ; Thu, 11 Feb 2021 05:24:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5E5CE64E30 for ; Thu, 11 Feb 2021 05:24:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229692AbhBKFYE (ORCPT ); Thu, 11 Feb 2021 00:24:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229699AbhBKFX4 (ORCPT ); Thu, 11 Feb 2021 00:23:56 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58C4DC061797 for ; Wed, 10 Feb 2021 21:22:39 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id b8so2721251plh.12 for ; Wed, 10 Feb 2021 21:22:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yf/rno8iZl7FiboO52D+Z5FCjHSUrFGjrs6kb9VfxZc=; b=QQaYk92R9MSar5LbEY4Jz089WlCH6zJeIBpW8S733JOJGnjcFWJrEGr0M/A8U9M/A1 dEDNAK4kp66DRXzpc1gzgQDmyeR7Hf0RraVqbWZloY45Qi2EbgsDtk/T4hUxN0G2teON /mWjK76kl02w6Yq5LcTtqGFIP4nc9SC7AOAz4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yf/rno8iZl7FiboO52D+Z5FCjHSUrFGjrs6kb9VfxZc=; b=MlxWwNnmWbhuYKuG6atwOgWWGrS8sy1u8Q61aGg71f5URwin4tJ+9ULSZnYuvcQQGe QelE3bZ2Skj1gLjfitVSgvMeehQKLnAdRULu1ScruM3j/m47VXnvSIJud5308QV7S0NQ oRAkaOUNpV9fRE1u0W1bxEdrr/hUif0RaS8zsa+1zt6b/g7fRZwM4ByD24velv+yKmd5 MRMX5ZVAL7RljRa+/J79eJwen6FKxTBrJDrMTU+4UCjRdxajS2kqjp7d8ZX9Ec+pOllG X4F0xhvWMT6EtG95uYgYxkbB3H0gxMu+nIh6BBOa/gpDV2lBf972PAXdMUU/7EswR3KK Bviw== X-Gm-Message-State: AOAM533yGzyyE8WQwDZgK+4uXC3t9zi15ynptepS+T1ErnPyS+1en2a9 nu3P6GHmcnoPJDI4p/4XKFcgHd6M3OgCqrFd X-Google-Smtp-Source: ABdhPJyECE81mEOyMfrxozkhKJ8viUwa7YTWL+FWSQNlzFlE08xfRgbmMzRYgQT3Za4w3olp7HaKcg== X-Received: by 2002:a17:90a:b38b:: with SMTP id e11mr2441170pjr.214.1613020958643; Wed, 10 Feb 2021 21:22:38 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id o21sm3493511pjp.42.2021.02.10.21.22.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 21:22:38 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org Cc: w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH v2 3/7] clk: fixed: add devm helper for clk_hw_register_fixed_factor() Date: Thu, 11 Feb 2021 14:22:02 +0900 Message-Id: <20210211052206.2955988-4-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210211052206.2955988-1-daniel@0x0f.com> References: <20210211052206.2955988-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add a devm helper for clk_hw_register_fixed_factor() so that drivers that internally register fixed factor clocks for things like dividers don't need to manually unregister them on remove or if probe fails. Signed-off-by: Daniel Palmer --- drivers/clk/clk-fixed-factor.c | 39 ++++++++++++++++++++++++++++------ include/linux/clk-provider.h | 4 +++- 2 files changed, 36 insertions(+), 7 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 910e6e74ae90..4f7bf3929d6d 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -64,10 +64,16 @@ const struct clk_ops clk_fixed_factor_ops = { }; EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); +static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void *res) +{ + clk_hw_unregister_fixed_factor(&((struct clk_fixed_factor *)res)->hw); +} + static struct clk_hw * __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, int index, - unsigned long flags, unsigned int mult, unsigned int div) + unsigned long flags, unsigned int mult, unsigned int div, + bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; @@ -75,7 +81,15 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, struct clk_hw *hw; int ret; - fix = kmalloc(sizeof(*fix), GFP_KERNEL); + /* You can't use devm without a dev */ + if (devm && !dev) + return ERR_PTR(-EINVAL); + + if (devm) + fix = devres_alloc(devm_clk_hw_register_fixed_factor_release, + sizeof(*fix), GFP_KERNEL); + else + fix = kmalloc(sizeof(*fix), GFP_KERNEL); if (!fix) return ERR_PTR(-ENOMEM); @@ -99,9 +113,13 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, else ret = of_clk_hw_register(np, hw); if (ret) { - kfree(fix); + if (devm) + devres_free(fix); + else + kfree(fix); hw = ERR_PTR(ret); - } + } else if (devm) + devres_add(dev, fix); return hw; } @@ -111,7 +129,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1, - flags, mult, div); + flags, mult, div, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); @@ -153,6 +171,15 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw) } EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor); +struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div) +{ + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1, + flags, mult, div, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); + #ifdef CONFIG_OF static const struct of_device_id set_rate_parent_matches[] = { { .compatible = "allwinner,sun4i-a10-pll3-2x-clk" }, @@ -185,7 +212,7 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) flags |= CLK_SET_RATE_PARENT; hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0, - flags, mult, div); + flags, mult, div, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index e4316890661a..58f6fe866ae9 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -941,7 +941,9 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); - +struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + unsigned int mult, unsigned int div); /** * struct clk_fractional_divider - adjustable fractional divider clock * From patchwork Thu Feb 11 05:22:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12082299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C532BC4332B for ; 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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id o21sm3493511pjp.42.2021.02.10.21.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 21:22:40 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org Cc: w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH v2 4/7] clk: mstar: MStar/SigmaStar MPLL driver Date: Thu, 11 Feb 2021 14:22:03 +0900 Message-Id: <20210211052206.2955988-5-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210211052206.2955988-1-daniel@0x0f.com> References: <20210211052206.2955988-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This adds a basic driver for the MPLL block found in MStar/SigmaStar ARMv7 SoCs. Currently this driver is only good for calculating the rates of it's outputs and the actual configuration must be done before the kernel boots. Usually this is done even before u-boot starts. This driver targets the MPLL block found in the MSC313/MSC313E but there is no documentation this chip so the register descriptions for the another MStar chip the MST786 were used as they seem to match. Signed-off-by: Daniel Palmer --- MAINTAINERS | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/mstar/Kconfig | 5 + drivers/clk/mstar/Makefile | 6 ++ drivers/clk/mstar/clk-msc313-mpll.c | 155 ++++++++++++++++++++++++++++ 6 files changed, 169 insertions(+) create mode 100644 drivers/clk/mstar/Kconfig create mode 100644 drivers/clk/mstar/Makefile create mode 100644 drivers/clk/mstar/clk-msc313-mpll.c diff --git a/MAINTAINERS b/MAINTAINERS index d004436c8860..d8414dbfebec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2149,6 +2149,7 @@ F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ +F: drivers/clk/mstar/ F: drivers/gpio/gpio-msc313.c F: include/dt-bindings/clock/mstar-* F: include/dt-bindings/gpio/msc313-gpio.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 85856cff506c..a29c15444d0e 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -379,6 +379,7 @@ source "drivers/clk/ingenic/Kconfig" source "drivers/clk/keystone/Kconfig" source "drivers/clk/mediatek/Kconfig" source "drivers/clk/meson/Kconfig" +source "drivers/clk/mstar/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/renesas/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index dbdc590e7de3..7fed7e5944cd 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_MACH_PIC32) += microchip/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif +obj-$(CONFIG_ARCH_MSTARV7) += mstar/ obj-y += mvebu/ obj-$(CONFIG_ARCH_MXS) += mxs/ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ diff --git a/drivers/clk/mstar/Kconfig b/drivers/clk/mstar/Kconfig new file mode 100644 index 000000000000..23765edde3af --- /dev/null +++ b/drivers/clk/mstar/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only +config MSTAR_MSC313_MPLL + bool + select REGMAP + select REGMAP_MMIO diff --git a/drivers/clk/mstar/Makefile b/drivers/clk/mstar/Makefile new file mode 100644 index 000000000000..f8dcd25ede1d --- /dev/null +++ b/drivers/clk/mstar/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for mstar specific clk +# + +obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o diff --git a/drivers/clk/mstar/clk-msc313-mpll.c b/drivers/clk/mstar/clk-msc313-mpll.c new file mode 100644 index 000000000000..09f578108eef --- /dev/null +++ b/drivers/clk/mstar/clk-msc313-mpll.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MStar MSC313 MPLL driver + * + * Copyright (C) 2020 Daniel Palmer + */ + +#include +#include +#include +#include + +#define REG_CONFIG1 0x8 +#define REG_CONFIG2 0xc + +static const struct regmap_config msc313_mpll_regmap_config = { + .reg_bits = 16, + .val_bits = 16, + .reg_stride = 4, +}; + +static const struct reg_field config1_loop_div_first = REG_FIELD(REG_CONFIG1, 8, 9); +static const struct reg_field config1_input_div_first = REG_FIELD(REG_CONFIG1, 4, 5); +static const struct reg_field config2_output_div_first = REG_FIELD(REG_CONFIG2, 12, 13); +static const struct reg_field config2_loop_div_second = REG_FIELD(REG_CONFIG2, 0, 7); + +static const unsigned int output_dividers[] = { + 2, 3, 4, 5, 6, 7, 10 +}; + +#define NUMOUTPUTS (ARRAY_SIZE(output_dividers) + 1) + +struct msc313_mpll { + struct clk_hw clk_hw; + struct regmap_field *input_div; + struct regmap_field *loop_div_first; + struct regmap_field *loop_div_second; + struct regmap_field *output_div; + struct clk_hw_onecell_data *clk_data; +}; + +#define to_mpll(_hw) container_of(_hw, struct msc313_mpll, clk_hw) + +static unsigned long msc313_mpll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct msc313_mpll *mpll = to_mpll(hw); + unsigned int input_div, output_div, loop_first, loop_second; + unsigned long output_rate; + + regmap_field_read(mpll->input_div, &input_div); + regmap_field_read(mpll->output_div, &output_div); + regmap_field_read(mpll->loop_div_first, &loop_first); + regmap_field_read(mpll->loop_div_second, &loop_second); + + output_rate = parent_rate / (1 << input_div); + output_rate *= (1 << loop_first) * max(loop_second, 1U); + output_rate /= max(output_div, 1U); + + return output_rate; +} + +static const struct clk_ops msc313_mpll_ops = { + .recalc_rate = msc313_mpll_recalc_rate, +}; + +static const struct clk_parent_data mpll_parent = { + .index = 0, +}; + +static int msc313_mpll_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct msc313_mpll *mpll; + struct clk_init_data clk_init = { }; + struct device *dev = &pdev->dev; + struct regmap *regmap; + char *outputname; + struct clk_hw *divhw; + int ret, i; + + mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL); + if (!mpll) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &msc313_mpll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + mpll->input_div = devm_regmap_field_alloc(dev, regmap, config1_input_div_first); + if (IS_ERR(mpll->input_div)) + return PTR_ERR(mpll->input_div); + mpll->output_div = devm_regmap_field_alloc(dev, regmap, config2_output_div_first); + if (IS_ERR(mpll->output_div)) + return PTR_ERR(mpll->output_div); + mpll->loop_div_first = devm_regmap_field_alloc(dev, regmap, config1_loop_div_first); + if (IS_ERR(mpll->loop_div_first)) + return PTR_ERR(mpll->loop_div_first); + mpll->loop_div_second = devm_regmap_field_alloc(dev, regmap, config2_loop_div_second); + if (IS_ERR(mpll->loop_div_second)) + return PTR_ERR(mpll->loop_div_second); + + mpll->clk_data = devm_kzalloc(dev, struct_size(mpll->clk_data, hws, + ARRAY_SIZE(output_dividers)), GFP_KERNEL); + if (!mpll->clk_data) + return -ENOMEM; + + clk_init.name = dev_name(dev); + clk_init.ops = &msc313_mpll_ops; + clk_init.parent_data = &mpll_parent; + clk_init.num_parents = 1; + mpll->clk_hw.init = &clk_init; + + ret = devm_clk_hw_register(dev, &mpll->clk_hw); + if (ret) + return ret; + + mpll->clk_data->num = NUMOUTPUTS; + mpll->clk_data->hws[0] = &mpll->clk_hw; + + for (i = 0; i < ARRAY_SIZE(output_dividers); i++) { + outputname = devm_kasprintf(dev, GFP_KERNEL, "%s_div_%d", + clk_init.name, output_dividers[i]); + if (!outputname) + return -ENOMEM; + divhw = devm_clk_hw_register_fixed_factor(dev, outputname, + clk_init.name, 0, 1, output_dividers[i]); + if (IS_ERR(divhw)) + return PTR_ERR(divhw); + mpll->clk_data->hws[i + 1] = divhw; + } + + platform_set_drvdata(pdev, mpll); + + return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + mpll->clk_data); +} + +static const struct of_device_id msc313_mpll_of_match[] = { + { .compatible = "mstar,msc313-mpll", }, + {} +}; + +static struct platform_driver msc313_mpll_driver = { + .driver = { + .name = "mstar-msc313-mpll", + .of_match_table = msc313_mpll_of_match, + }, + .probe = msc313_mpll_probe, +}; +builtin_platform_driver(msc313_mpll_driver); From patchwork Thu Feb 11 05:22:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12082301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 168ACC433DB for ; Thu, 11 Feb 2021 05:24:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E655E64E7C for ; Thu, 11 Feb 2021 05:24:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229592AbhBKFYU (ORCPT ); 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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id o21sm3493511pjp.42.2021.02.10.21.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 21:22:42 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org Cc: w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH v2 5/7] ARM: mstar: Select MSTAR_MSC313_MPLL Date: Thu, 11 Feb 2021 14:22:04 +0900 Message-Id: <20210211052206.2955988-6-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210211052206.2955988-1-daniel@0x0f.com> References: <20210211052206.2955988-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org All of the ARCH_MSTARV7 chips have an MPLL as the source for peripheral clocks so select MSTAR_MSC313_MPLL. Signed-off-by: Daniel Palmer --- arch/arm/mach-mstar/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig index 576d1ab293c8..cd300eeedc20 100644 --- a/arch/arm/mach-mstar/Kconfig +++ b/arch/arm/mach-mstar/Kconfig @@ -4,6 +4,7 @@ menuconfig ARCH_MSTARV7 select ARM_GIC select ARM_HEAVY_MB select MST_IRQ + select MSTAR_MSC313_MPLL help Support for newer MStar/Sigmastar SoC families that are based on Armv7 cores like the Cortex A7 and share the same From patchwork Thu Feb 11 05:22:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12082305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5873BC433DB for ; Thu, 11 Feb 2021 05:25:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 342EB64E26 for ; Thu, 11 Feb 2021 05:25:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229544AbhBKFZB (ORCPT ); Thu, 11 Feb 2021 00:25:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229749AbhBKFYq (ORCPT ); Thu, 11 Feb 2021 00:24:46 -0500 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E696C06121F for ; Wed, 10 Feb 2021 21:22:46 -0800 (PST) Received: by mail-pf1-x436.google.com with SMTP id 18so3019705pfz.3 for ; Wed, 10 Feb 2021 21:22:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=drLaSc5ZM86pYsr4qLGvKU8aVv9tTxJbObF+iwNMmEQ=; b=jp6hj6pAZiQPW3brKYdJFQwHu7V/w6I6J6wMmvcoskkhHdvU5VWS3StPS6ZKXC0vDu fRLGvDYkHBrB/12nBLeQjy+uAynaTZfcN+UCbE9hsP8CJP4KrsMTCtWUE1+eCR187F+Q 0lkoF9qUAj3hkLRMVH5+eOY2Zpa2qUcMd7YPU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=drLaSc5ZM86pYsr4qLGvKU8aVv9tTxJbObF+iwNMmEQ=; b=SgHZp95OlGKfnPglBR4Q1M+U3Ti4Z8vUeBE4qVoeX1L7ETMI8WaIHnsfwEsJQIKvg3 49bHSzx9OlyaT3E4K7N5JBZN5RGa+BR0leQl8YJCTl+viDV3a7Q2jd+vjQMUyA5Gmbje QeRAdYI8Fp1VWIXx++v61g2ND4hwAO3RpbqGhjYOxMSDCPxsbdsNAEQUliQokajWRODC 9LSvSMN3MjAf6Zqpmk0euQ1hNdrtLSMM0107RdEi8FyZyOFitPQRom5WVtp1vCBjOBTL Vhv5O0ePDTL4UXTrql3lcnEOfIbohcWz7MrxvteTlFxVXlhpo3UprGwjJclZkUii2RAb JzcA== X-Gm-Message-State: AOAM533ToGwHeNccobGAgD3ZcK6YAKG/i58CiPMIMX7rn6k+Sa2colwb qKsg2qZNUHrX6gCgzz3LWPPJhJX8ZICt50TS X-Google-Smtp-Source: ABdhPJyHpMF49V0rRYm+e1K3qaBAEMF89qgT53q/leQhoUKNZHISqHdbh9vE3U7pIb57dPPHmnMhXw== X-Received: by 2002:a63:215f:: with SMTP id s31mr6408465pgm.146.1613020965624; Wed, 10 Feb 2021 21:22:45 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id o21sm3493511pjp.42.2021.02.10.21.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 21:22:45 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org Cc: w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH v2 6/7] ARM: mstar: Add the external clocks to the base dsti Date: Thu, 11 Feb 2021 14:22:05 +0900 Message-Id: <20210211052206.2955988-7-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210211052206.2955988-1-daniel@0x0f.com> References: <20210211052206.2955988-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org All of the currently known MStar/SigmaStar ARMv7 SoCs have an "xtal" clock input that is usually 24MHz and an "RTC xtal" that is usually 32KHz. The xtal input has to be connected to something so it's enabled by default. The MSC313 and MSC313E do not bring the RTC clock input out to the pins so it's impossible to connect it. The SSC8336 does bring the input out to the pins but it's not always actually connected to something. The RTC node needs to always be present because in the future the nodes for the clock muxes will refer to it even if it's not usable. The RTC node is disabled by default and should be enabled at the board level if the RTC input is wired up. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index b0a21b0b731f..889c3804c251 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -46,6 +46,21 @@ pmu: pmu { interrupt-affinity = <&cpu0>; }; + clocks: clocks { + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + rtc_xtal: rtc_xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + status = "disabled"; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; From patchwork Thu Feb 11 05:22:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12082303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46364C433E6 for ; Thu, 11 Feb 2021 05:25:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 166F364E8B for ; Thu, 11 Feb 2021 05:25:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229559AbhBKFYt (ORCPT ); Thu, 11 Feb 2021 00:24:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbhBKFYk (ORCPT ); Thu, 11 Feb 2021 00:24:40 -0500 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE007C061223 for ; Wed, 10 Feb 2021 21:22:48 -0800 (PST) Received: by mail-pf1-x42b.google.com with SMTP id 189so3006258pfy.6 for ; Wed, 10 Feb 2021 21:22:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vk7Z0AS7ak4J0BwIBs0zSntFuze/upcDQo3SRk3ydVI=; b=m4hEkGAhe/bsNcOv9Y6cZl08ZjTGXhVFHQvUJtbARWhP3WYfyhNlc9HVPtW0kFkBLt 6Fq+zWLqWe8hlBhKhY68VS5cA+5RjXodulpr2PmzOb1NmT3Q4pfkqUFgq685zVyNEhz2 PNG1xv3+zvMSVcujr9L6wd7ahhwYtmyqROBTg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vk7Z0AS7ak4J0BwIBs0zSntFuze/upcDQo3SRk3ydVI=; b=b7JG0EgHN9xg9HpiiuDFZLTYbhz99zw9rIQf5ecgS5HDpv0fjwygjDYo4KVXvibZEN vDxL+HEHJdRbBI7a+kAduM0IQ/CMjG1ffVYkQ6ZmmTZK/MTiUkvVocA9NZBDTOYYrCX2 68r4uKeCP97ad/rbMbUlVxI9th+9EEKl8Lr28Dhf1THtyR4N0dlUv8nt0Kd1GJbAkfgL t4Fvzd8pZn5hUGWIIB0EqXUftHc2Z0F/bJW3qYZ5bousVj8vl3K79dUsM8wV5NsR9gqD Vmje6HYhIMvGdtA16FRDT5QQF7Rt3sjaWUppH9ig+s3zvpL+8KpY61z6JsZ79ilBnokI EmBg== X-Gm-Message-State: AOAM533+gwM4Ml5jT6V9UBFRta18K0AAaSWr6VkpxHX7/9dSCFe7vFQp JTeuQ3dGuzz2/CTmzJ8ecoQdgXLwtUwFMCt/ X-Google-Smtp-Source: ABdhPJyISaJ8cwyL7Zx0SCuhZTeWSCJmZ3TmVwLz+shRCM5N9O/vaXtiCDAHszb9as31QHnl+NVk7A== X-Received: by 2002:a63:c741:: with SMTP id v1mr6379922pgg.316.1613020968122; Wed, 10 Feb 2021 21:22:48 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id o21sm3493511pjp.42.2021.02.10.21.22.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 21:22:47 -0800 (PST) From: Daniel Palmer To: linux-clk@vger.kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org Cc: w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH v2 7/7] ARM: mstar: Add mpll to base dtsi Date: Thu, 11 Feb 2021 14:22:06 +0900 Message-Id: <20210211052206.2955988-8-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210211052206.2955988-1-daniel@0x0f.com> References: <20210211052206.2955988-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org All of the currently known MStar/SigmaStar ARMv7 SoCs have at least one MPLL and it seems to always be at the same place so add it to the base dtsi. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 889c3804c251..075d583d6f40 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { #address-cells = <1>; @@ -124,6 +125,13 @@ l3bridge: l3bridge@204400 { reg = <0x204400 0x200>; }; + mpll: mpll@206000 { + compatible = "mstar,msc313-mpll"; + #clock-cells = <1>; + reg = <0x206000 0x200>; + clocks = <&xtal>; + }; + gpio: gpio@207800 { #gpio-cells = <2>; reg = <0x207800 0x200>;