From patchwork Thu Feb 11 11:50:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 12082951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64A02C433E0 for ; Thu, 11 Feb 2021 11:50:49 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0FAEC64E87 for ; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lAAUe-0001c1-0q; Thu, 11 Feb 2021 11:50:44 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lAAUE-0001RF-EJ; Thu, 11 Feb 2021 11:50:20 +0000 Received: from localhost.localdomain (unknown [IPv6:2a01:e0a:4cb:a870:94f7:2542:9eb3:b5ba]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id C44F11F45970; Thu, 11 Feb 2021 11:50:13 +0000 (GMT) From: Benjamin Gaignard To: p.zabel@pengutronix.de, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, ezequiel@collabora.com, mchehab@kernel.org, gregkh@linuxfoundation.org Subject: [PATCH 1/4] dt-bindings: reset: IMX8MQ VPU reset Date: Thu, 11 Feb 2021 12:50:00 +0100 Message-Id: <20210211115003.249367-2-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210211115003.249367-1-benjamin.gaignard@collabora.com> References: <20210211115003.249367-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210211_065018_615575_660CFCDA X-CRM114-Status: GOOD ( 15.77 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org, benjamin.gaignard@collabora.com, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-imx@nxp.com, kernel@pengutronix.de, kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Document bindings for IMX8MQ VPU reset hardware block Signed-off-by: Benjamin Gaignard --- .../bindings/reset/fsl,imx8mq-vpu-reset.yaml | 54 +++++++++++++++++++ include/dt-bindings/reset/imx8mq-vpu-reset.h | 16 ++++++ 2 files changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml create mode 100644 include/dt-bindings/reset/imx8mq-vpu-reset.h diff --git a/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml new file mode 100644 index 000000000000..00020421c0e3 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/fsl,imx8mq-vpu-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MQ VPU Reset Controller + +maintainers: + - Benjamin Gaignard + +description: | + The VPU reset controller is used to reset the video processor + unit peripherals. Device nodes that need access to reset lines should + specify them as a reset phandle in their corresponding node as + specified in reset.txt. + + For list of all valid reset indices see + for i.MX8MQ. + +properties: + compatible: + items: + - const: fsl,imx8mq-vpu-reset + - const: syscon + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + vpu-reset@38320000 { + compatible = "fsl,imx8mq-vpu-reset", "syscon"; + reg = <0x38320000 0x10000>; + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/reset/imx8mq-vpu-reset.h b/include/dt-bindings/reset/imx8mq-vpu-reset.h new file mode 100644 index 000000000000..efcbe18177fe --- /dev/null +++ b/include/dt-bindings/reset/imx8mq-vpu-reset.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, Collabora + * + * i.MX7 System Reset Controller (SRC) driver + * + * Author: Benjamin Gaignard + */ + +#ifndef DT_BINDINGS_VPU_RESET_IMX8MQ +#define DT_BINDINGS_VPU_RESET_IMX8MQ + +#define IMX8MQ_RESET_VPU_RESET_G1 0 +#define IMX8MQ_RESET_VPU_RESET_G2 1 + +#endif From patchwork Thu Feb 11 11:50:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 12082945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91FB7C433E0 for ; Thu, 11 Feb 2021 11:50:36 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C2B864E38 for ; Thu, 11 Feb 2021 11:50:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3C2B864E38 Authentication-Results: mail.kernel.org; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lAAUR-0001XG-QI; Thu, 11 Feb 2021 11:50:31 +0000 Received: from bhuna.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e3e3]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lAAUE-0001RJ-0q; Thu, 11 Feb 2021 11:50:19 +0000 Received: from localhost.localdomain (unknown [IPv6:2a01:e0a:4cb:a870:94f7:2542:9eb3:b5ba]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 591CD1F45971; Thu, 11 Feb 2021 11:50:16 +0000 (GMT) From: Benjamin Gaignard To: p.zabel@pengutronix.de, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, ezequiel@collabora.com, mchehab@kernel.org, gregkh@linuxfoundation.org Subject: [PATCH 2/4] reset: Add reset driver for IMX8MQ VPU block Date: Thu, 11 Feb 2021 12:50:01 +0100 Message-Id: <20210211115003.249367-3-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210211115003.249367-1-benjamin.gaignard@collabora.com> References: <20210211115003.249367-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210211_065018_320130_D43FF3DA X-CRM114-Status: GOOD ( 21.33 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org, benjamin.gaignard@collabora.com, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-imx@nxp.com, kernel@pengutronix.de, kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org IMX8MQ SoC got a dedicated hardware block to reset the video processor units (G1 and G2). Signed-off-by: Benjamin Gaignard --- drivers/reset/Kconfig | 8 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-imx8mq-vpu.c | 169 +++++++++++++++++++++++++++++++ 3 files changed, 178 insertions(+) create mode 100644 drivers/reset/reset-imx8mq-vpu.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 71ab75a46491..fa95380b271a 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -80,6 +80,14 @@ config RESET_IMX7 help This enables the reset controller driver for i.MX7 SoCs. +config RESET_VPU_IMX8MQ + tristate "i.MX8MQ VPU Reset Driver" + depends on HAS_IOMEM + depends on (ARM64 && ARCH_MXC) || COMPILE_TEST + select MFD_SYSCON + help + This enables the VPU reset controller driver for i.MX8MQ SoCs. + config RESET_INTEL_GW bool "Intel Reset Controller Driver" depends on OF && HAS_IOMEM diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 1054123fd187..6007e0cdfc05 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o +obj-$(CONFIG_RESET_VPU_IMX8MQ) += reset-imx8mq-vpu.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o diff --git a/drivers/reset/reset-imx8mq-vpu.c b/drivers/reset/reset-imx8mq-vpu.c new file mode 100644 index 000000000000..14c589f19266 --- /dev/null +++ b/drivers/reset/reset-imx8mq-vpu.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, Collabora + * + * i.MX8MQ VPU Reset Controller driver + * + * Author: Benjamin Gaignard + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CTRL_SOFT_RESET 0x00 +#define RESET_G1 ((u32)BIT(1)) +#define RESET_G2 ((u32)BIT(0)) + +#define CTRL_ENABLE 0x04 +#define ENABLE_G1 BIT(1) +#define ENABLE_G2 BIT(0) + +#define CTRL_G1_DEC_FUSE 0x08 +#define CTRL_G1_PP_FUSE 0x0c +#define CTRL_G2_DEC_FUSE 0x10 + +struct imx8mq_vpu_reset { + struct reset_controller_dev rcdev; + struct regmap *regmap; + struct clk_bulk_data *clocks; + int num_clocks; + struct device *dev; +}; + +static inline struct imx8mq_vpu_reset *to_imx8mq_vpu_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct imx8mq_vpu_reset, rcdev); +} + +static int imx8mq_vpu_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx8mq_vpu_reset *reset = to_imx8mq_vpu_reset(rcdev); + int ret = -EINVAL; + + ret = clk_bulk_prepare_enable(reset->num_clocks, reset->clocks); + if (ret) { + dev_err(reset->dev, "Failed to prepare clocks\n"); + return ret; + } + + switch (id) { + case IMX8MQ_RESET_VPU_RESET_G1: + ret = regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G1, ~RESET_G1); + ret |= regmap_update_bits(reset->regmap, CTRL_ENABLE, ENABLE_G1, ENABLE_G1); + break; + case IMX8MQ_RESET_VPU_RESET_G2: + ret = regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G2, ~RESET_G2); + ret |= regmap_update_bits(reset->regmap, CTRL_ENABLE, ENABLE_G2, ENABLE_G2); + break; + } + + /* Set values of the fuse registers */ + ret |= regmap_write(reset->regmap, CTRL_G1_DEC_FUSE, 0xffffffff); + ret |= regmap_write(reset->regmap, CTRL_G1_PP_FUSE, 0xffffffff); + ret |= regmap_write(reset->regmap, CTRL_G2_DEC_FUSE, 0xffffffff); + + clk_bulk_disable_unprepare(reset->num_clocks, reset->clocks); + + return ret; +} + +static int imx8mq_vpu_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct imx8mq_vpu_reset *reset = to_imx8mq_vpu_reset(rcdev); + int ret; + + ret = clk_bulk_prepare_enable(reset->num_clocks, reset->clocks); + if (ret) { + dev_err(reset->dev, "Failed to prepare clocks\n"); + return ret; + } + + switch (id) { + case IMX8MQ_RESET_VPU_RESET_G1: + return regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G1, RESET_G1); + case IMX8MQ_RESET_VPU_RESET_G2: + return regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G2, RESET_G2); + } + + clk_bulk_disable_unprepare(reset->num_clocks, reset->clocks); + + return -EINVAL; +} + +static int imx8mq_vpu_reset_dev(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = imx8mq_vpu_reset_assert(rcdev, id); + if (ret) + return ret; + + udelay(2); + + return imx8mq_vpu_reset_deassert(rcdev, id); +} + +static const struct reset_control_ops imx8mq_vpu_reset_ops = { + .reset = imx8mq_vpu_reset_dev, + .assert = imx8mq_vpu_reset_assert, + .deassert = imx8mq_vpu_reset_deassert, +}; + +static int imx8mq_vpu_reset_probe(struct platform_device *pdev) +{ + struct imx8mq_vpu_reset *reset; + struct device *dev = &pdev->dev; + struct regmap_config config = { .name = "vpu-reset" }; + + reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + reset->regmap = device_node_to_regmap(dev->of_node); + if (IS_ERR(reset->regmap)) { + dev_err(dev, "Unable to get imx8mq-vpu-reset regmap"); + return PTR_ERR(reset->regmap); + } + regmap_attach_dev(dev, reset->regmap, &config); + + reset->num_clocks = devm_clk_bulk_get_all(dev, &reset->clocks); + if (!reset->num_clocks) + return -EINVAL; + + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.nr_resets = 2; + reset->rcdev.ops = &imx8mq_vpu_reset_ops; + reset->rcdev.of_node = dev->of_node; + reset->dev = dev; + + return devm_reset_controller_register(dev, &reset->rcdev); +} + +static const struct of_device_id imx8mq_vpu_reset_dt_ids[] = { + { .compatible = "fsl,imx8mq-vpu-reset",}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mq_vpu_reset_dt_ids); + +static struct platform_driver imx8mq_vpu_reset_driver = { + .probe = imx8mq_vpu_reset_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = imx8mq_vpu_reset_dt_ids, + }, +}; +module_platform_driver(imx8mq_vpu_reset_driver); + +MODULE_AUTHOR("Benjamin Gaignard "); +MODULE_DESCRIPTION("NXP i.MX8MQ VPU reset driver"); +MODULE_LICENSE("GPL v2"); From patchwork Thu Feb 11 11:50:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 12082949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63013C433DB for ; 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Thu, 11 Feb 2021 11:50:17 +0000 (GMT) From: Benjamin Gaignard To: p.zabel@pengutronix.de, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, ezequiel@collabora.com, mchehab@kernel.org, gregkh@linuxfoundation.org Subject: [PATCH 3/4] media: hantro: Use reset driver Date: Thu, 11 Feb 2021 12:50:02 +0100 Message-Id: <20210211115003.249367-4-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210211115003.249367-1-benjamin.gaignard@collabora.com> References: <20210211115003.249367-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210211_065019_333341_011AA47C X-CRM114-Status: GOOD ( 16.59 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org, benjamin.gaignard@collabora.com, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-imx@nxp.com, kernel@pengutronix.de, kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Rather use a reset like feature inside the driver use the reset controller API to get the same result. Signed-off-by: Benjamin Gaignard --- drivers/staging/media/hantro/Kconfig | 1 + drivers/staging/media/hantro/imx8m_vpu_hw.c | 61 ++++----------------- 2 files changed, 12 insertions(+), 50 deletions(-) diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig index 5b6cf9f62b1a..dd1d4dde2658 100644 --- a/drivers/staging/media/hantro/Kconfig +++ b/drivers/staging/media/hantro/Kconfig @@ -20,6 +20,7 @@ config VIDEO_HANTRO_IMX8M bool "Hantro VPU i.MX8M support" depends on VIDEO_HANTRO depends on ARCH_MXC || COMPILE_TEST + select RESET_VPU_IMX8MQ default y help Enable support for i.MX8M SoCs. diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index c222de075ef4..d5b4312b9391 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -7,49 +7,12 @@ #include #include +#include #include "hantro.h" #include "hantro_jpeg.h" #include "hantro_g1_regs.h" -#define CTRL_SOFT_RESET 0x00 -#define RESET_G1 BIT(1) -#define RESET_G2 BIT(0) - -#define CTRL_CLOCK_ENABLE 0x04 -#define CLOCK_G1 BIT(1) -#define CLOCK_G2 BIT(0) - -#define CTRL_G1_DEC_FUSE 0x08 -#define CTRL_G1_PP_FUSE 0x0c -#define CTRL_G2_DEC_FUSE 0x10 - -static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) -{ - u32 val; - - /* Assert */ - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); - val &= ~reset_bits; - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); - - udelay(2); - - /* Release */ - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); - val |= reset_bits; - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); -} - -static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) -{ - u32 val; - - val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); - val |= clock_bits; - writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); -} - static int imx8mq_runtime_resume(struct hantro_dev *vpu) { int ret; @@ -60,13 +23,10 @@ static int imx8mq_runtime_resume(struct hantro_dev *vpu) return ret; } - imx8m_soft_reset(vpu, RESET_G1 | RESET_G2); - imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2); + ret = device_reset(vpu->dev); + if (ret) + dev_err(vpu->dev, "Failed to reset Hantro VPU\n"); - /* Set values of the fuse registers */ - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE); - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE); - writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE); clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks); @@ -151,16 +111,17 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id) static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) { vpu->dec_base = vpu->reg_bases[0]; - vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; return 0; } -static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) +static void imx8mq_vpu_reset(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev; + int ret = device_reset(vpu->dev); - imx8m_soft_reset(vpu, RESET_G1); + if (ret) + dev_err(vpu->dev, "Failed to reset Hantro VPU\n"); } /* @@ -170,19 +131,19 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { [HANTRO_MODE_MPEG2_DEC] = { .run = hantro_g1_mpeg2_dec_run, - .reset = imx8m_vpu_g1_reset, + .reset = imx8mq_vpu_reset, .init = hantro_mpeg2_dec_init, .exit = hantro_mpeg2_dec_exit, }, [HANTRO_MODE_VP8_DEC] = { .run = hantro_g1_vp8_dec_run, - .reset = imx8m_vpu_g1_reset, + .reset = imx8mq_vpu_reset, .init = hantro_vp8_dec_init, .exit = hantro_vp8_dec_exit, }, [HANTRO_MODE_H264_DEC] = { .run = hantro_g1_h264_dec_run, - .reset = imx8m_vpu_g1_reset, + .reset = imx8mq_vpu_reset, .init = hantro_h264_dec_init, .exit = hantro_h264_dec_exit, }, From patchwork Thu Feb 11 11:50:03 2021 Content-Type: text/plain; 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Signed-off-by: Benjamin Gaignard --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 31 ++++++++++++++++++----- 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index a841a023e8e0..7d4863d47112 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "dt-bindings/input/input.h" #include @@ -1267,19 +1268,36 @@ usb3_phy1: usb-phy@382f0040 { status = "disabled"; }; + vpu_reset: vpu-reset@38320000 { + compatible = "fsl,imx8mq-vpu-reset", "syscon"; + reg = <0x38320000 0x10000>; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, + <&clk IMX8MQ_CLK_VPU_G2>, + <&clk IMX8MQ_CLK_VPU_BUS>, + <&clk IMX8MQ_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_VPU_PLL>; + assigned-clock-rates = <600000000>, <600000000>, + <800000000>, <0>; + #reset-cells = <1>; + }; + vpu: video-codec@38300000 { compatible = "nxp,imx8mq-vpu"; reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; + <0x38310000 0x10000>; + reg-names = "g1", "g2"; interrupts = , ; interrupt-names = "g1", "g2"; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>, @@ -1290,6 +1308,7 @@ vpu: video-codec@38300000 { <&clk IMX8MQ_VPU_PLL>; assigned-clock-rates = <600000000>, <600000000>, <800000000>, <0>; + resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G1>; power-domains = <&pgc_vpu>; };