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[66.131.184.68]) by smtp.gmail.com with ESMTPSA id u7sm10928811qta.75.2021.02.15.08.27.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 08:27:02 -0800 (PST) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Jordan Crouse , Kalyan Thota , Eric Anholt , Tanmay Shah , Drew Davenport , Jeykumar Sankaran , Rajendra Nayak , tongtiangen , Qinglang Miao , dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), freedreno@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 1/2] drm/msm: add compatibles for sm8150/sm8250 display Date: Mon, 15 Feb 2021 11:26:04 -0500 Message-Id: <20210215162607.21360-2-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210215162607.21360-1-jonathan@marek.ca> References: <20210215162607.21360-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The driver already has support for sm8150/sm8250, but the compatibles were never added. Also inverse the non-mdp4 condition in add_display_components() to avoid having to check every new compatible in the condition. Signed-off-by: Jonathan Marek Acked-by: Rob Herring --- Documentation/devicetree/bindings/display/msm/dpu.txt | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++ drivers/gpu/drm/msm/msm_drv.c | 6 +++--- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt index 551ae26f60da..5763f43200a0 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu.txt +++ b/Documentation/devicetree/bindings/display/msm/dpu.txt @@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC. MDSS: Required properties: -- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" +- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss", "qcom,sm8150-mdss", "qcom,sm8250-mdss" - reg: physical base address and length of contoller's registers. - reg-names: register region names. The following region is required: * "mdss" @@ -41,7 +41,7 @@ Optional properties: MDP: Required properties: -- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" +- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu", "qcom,sm8150-dpu", "qcom,sm8250-dpu" - reg: physical base address and length of controller's registers. - reg-names : register region names. The following region is required: * "mdp" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 5a8e3e1fc48c..fff12a4c8bfc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1219,6 +1219,8 @@ static const struct dev_pm_ops dpu_pm_ops = { static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sdm845-dpu", }, { .compatible = "qcom,sc7180-dpu", }, + { .compatible = "qcom,sm8150-dpu", }, + { .compatible = "qcom,sm8250-dpu", }, {} }; MODULE_DEVICE_TABLE(of, dpu_dt_match); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 94525ac76d4e..928f13d4bfbc 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -1185,9 +1185,7 @@ static int add_display_components(struct device *dev, * Populate the children devices, find the MDP5/DPU node, and then add * the interfaces to our components list. */ - if (of_device_is_compatible(dev->of_node, "qcom,mdss") || - of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") || - of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) { + if (!of_device_is_compatible(dev->of_node, "qcom,mdp4")) { ret = of_platform_populate(dev->of_node, NULL, NULL, dev); if (ret) { DRM_DEV_ERROR(dev, "failed to populate children devices\n"); @@ -1320,6 +1318,8 @@ static const struct of_device_id dt_match[] = { { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU }, { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU }, + { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU }, + { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU }, {} }; MODULE_DEVICE_TABLE(of, dt_match); From patchwork Mon Feb 15 16:26:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 12088987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75D5DC4332D for ; Mon, 15 Feb 2021 16:30:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C0F264E8E for ; Mon, 15 Feb 2021 16:30:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231289AbhBOQ3w (ORCPT ); Mon, 15 Feb 2021 11:29:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231777AbhBOQ1p (ORCPT ); Mon, 15 Feb 2021 11:27:45 -0500 Received: from mail-qt1-x830.google.com (mail-qt1-x830.google.com [IPv6:2607:f8b0:4864:20::830]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFA18C061794 for ; Mon, 15 Feb 2021 08:27:04 -0800 (PST) Received: by mail-qt1-x830.google.com with SMTP id c1so5200810qtc.1 for ; Mon, 15 Feb 2021 08:27:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L2b11X7RX6S9uuGP/RiVj8dxHh//FmXWH5wSG8YTYW4=; b=MuJgvEB0ZpIC9h67r8fVYYq/jQlxeFLFcjO30PFkl06L2uTt1L38nnXaPOqtyRhYWe 6fzUPoQoa8NPKaeP8mT8JD5TlGePOUN/ExN1FZk5wyUhu9LzquVFp9A2WHo+KOYvmthq AAWe0z1jcpEjQ78MibVQdGpNhxbIPbb5GONQbC+aJaplQtcl2AKJho3Ea5SWwnomLD59 6by+LgGx0NleG0hdxEGFy1d7GU3+yRVt6sJuI3hdzj1Sw8liz6z8nGk0Qj89r208yduS zrMkYEbOM1vQlCtCKP/PBK7exMpWgoyLs8/06RrXSc+cO7WYgePAym00dRbwEXLuPR9i ZlmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L2b11X7RX6S9uuGP/RiVj8dxHh//FmXWH5wSG8YTYW4=; b=pyFbGiAfGXx4StmBR8gGZZr7h50llzJvYqxA9KrSrf6jzIOPan+p2sdVp+SBfk7GB/ HkCff3N0xmQyl+H1+oHjem6R9XYtttrIj9n+5Pnb1xCB6XhWHnRw/GNEjpQIGZ3aDU2c 4pJe76Qmp45W1vbxfPYw1P7rtx+S2UPG23ilHdf6THQSstPT8ykLLDYI6yAs/bIQ3RTm cJh6uiLldv5ykZx7jlrFnA7Gtd4GswlkLf3fQGXr8lFW70Jrr1/fmWuiTujKdv1lk30g HidfnwRlQ/20//wMx+InG/wq+vk3FxBEETZ/ow5pThaaMpPZ1JqKMVzUBCBlkg7oOAz8 xCVg== X-Gm-Message-State: AOAM530ZPYAfrjYaY5/WEPtqoqYCaQC16ZR7AEAFd9yfeR6TcdoAVZdU aO4LQxKzwaCRf4rQ9hkua7BL7/3M0V5LfRpC X-Google-Smtp-Source: ABdhPJyyAN5o6cHtOzDq559SJRuK26oNIP7uZjHkmGmB3ZKRW92mYDz7qjvzMkJdv/1CRxH+qebACg== X-Received: by 2002:ac8:3693:: with SMTP id a19mr8916544qtc.54.1613406423689; Mon, 15 Feb 2021 08:27:03 -0800 (PST) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id u7sm10928811qta.75.2021.02.15.08.27.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 08:27:03 -0800 (PST) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: Andy Gross , Bjorn Andersson , Rob Herring , Dmitry Baryshkov , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 2/2] arm64: dts: qcom: sm8250: fix display nodes Date: Mon, 15 Feb 2021 11:26:05 -0500 Message-Id: <20210215162607.21360-3-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210215162607.21360-1-jonathan@marek.ca> References: <20210215162607.21360-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Apply these fixes to the newly added sm8250 display ndoes - Use sm8250 compatibles instead of sdm845 compatibles - Remove "notused" interconnect (which apparently was blindly copied from my old patches) - Use dispcc node example from dt-bindings, removing clocks which aren't documented or used by the driver and fixing the region size. Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes") Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 31 +++++++--------------------- 1 file changed, 8 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 947e1accae3a..693ac533f9b6 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2323,14 +2323,13 @@ usb_2_dwc3: dwc3@a800000 { }; mdss: mdss@ae00000 { - compatible = "qcom,sdm845-mdss"; + compatible = "qcom,sm8250-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; - interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>, - <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "notused", "mdp0-mem", "mdp1-mem"; + interconnect-names = "mdp0-mem", "mdp1-mem"; power-domains = <&dispcc MDSS_GDSC>; @@ -2356,7 +2355,7 @@ mdss: mdss@ae00000 { ranges; mdss_mdp: mdp@ae01000 { - compatible = "qcom,sdm845-dpu"; + compatible = "qcom,sm8250-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; @@ -2580,7 +2579,7 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; - reg = <0 0x0af00000 0 0x20000>; + reg = <0 0x0af00000 0 0x10000>; mmcx-supply = <&mmcx_reg>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, @@ -2588,28 +2587,14 @@ dispcc: clock-controller@af00000 { <&dsi1_phy 0>, <&dsi1_phy 1>, <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <&sleep_clk>; + <0>; clock-names = "bi_tcxo", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_byteclk", "dsi1_phy_pll_out_dsiclk", - "dp_link_clk_divsel_ten", - "dp_vco_divided_clk_src_mux", - "dptx1_phy_pll_link_clk", - "dptx1_phy_pll_vco_div_clk", - "dptx2_phy_pll_link_clk", - "dptx2_phy_pll_vco_div_clk", - "edp_phy_pll_link_clk", - "edp_phy_pll_vco_div_clk", - "sleep_clk"; + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;