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Fri, 19 Feb 2021 02:04:20 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 19 Feb 2021 01:54:18 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 19 Feb 2021 17:54:16 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 19 Feb 2021 17:54:15 +0800 From: Yongqiang Niu To: CK Hu , Matthias Brugger Subject: [PATCH v1] drm/mediatek: move page flip handle into cmdq cb Date: Fri, 19 Feb 2021 17:54:12 +0800 Message-ID: <1613728452-24871-2-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1613728452-24871-1-git-send-email-yongqiang.niu@mediatek.com> References: <1613728452-24871-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210219_050423_938630_54B19438 X-CRM114-Status: GOOD ( 14.46 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Philipp Zabel , Chun-Kuang Hu , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , Project_Global_Chrome_Upstream_Group@mediatek.com, Rob Herring , linux-mediatek@lists.infradead.org, Daniel Vetter , Hsin-Yi Wang , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org move page flip handle into cmdq cb irq callback will before cmdq flush ddp register into hardware, that will cause the display frame page flip event before it realy display out time Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index bdd37ea..bece327 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -72,6 +72,13 @@ struct mtk_crtc_state { unsigned int pending_vrefresh; }; +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +struct mtk_cmdq_cb_data { + struct cmdq_pkt *cmdq_handle; + struct mtk_drm_crtc *mtk_crtc; +}; +#endif + static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) { return container_of(c, struct mtk_drm_crtc, base); @@ -96,7 +103,6 @@ static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) { - drm_crtc_handle_vblank(&mtk_crtc->base); if (mtk_crtc->pending_needs_vblank) { mtk_drm_crtc_finish_page_flip(mtk_crtc); mtk_crtc->pending_needs_vblank = false; @@ -241,7 +247,19 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, #if IS_REACHABLE(CONFIG_MTK_CMDQ) static void ddp_cmdq_cb(struct cmdq_cb_data data) { - cmdq_pkt_destroy(data.data); + struct mtk_cmdq_cb_data *cb_data = data.data; + + if (cb_data) { + struct mtk_drm_crtc *mtk_crtc = cb_data->mtk_crtc; + + if (mtk_crtc) + mtk_drm_finish_page_flip(mtk_crtc); + + if (cb_data->cmdq_handle) + cmdq_pkt_destroy(cb_data->cmdq_handle); + + kfree(cb_data); + } } #endif @@ -481,13 +499,20 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) } #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (mtk_crtc->cmdq_client) { + struct mtk_cmdq_cb_data *cb_data; + mbox_flush(mtk_crtc->cmdq_client->chan, 2000); cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); mtk_crtc_ddp_config(crtc, cmdq_handle); cmdq_pkt_finalize(cmdq_handle); - cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); + + cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL); + cb_data->cmdq_handle = cmdq_handle; + cb_data->mtk_crtc = mtk_crtc; + + cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cb_data); } #endif mutex_unlock(&mtk_crtc->hw_lock); @@ -674,7 +699,7 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) #endif mtk_crtc_ddp_config(crtc, NULL); - mtk_drm_finish_page_flip(mtk_crtc); + drm_crtc_handle_vblank(&mtk_crtc->base); } static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,