From patchwork Thu Nov 15 16:47:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Kaneko X-Patchwork-Id: 10684707 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6DF214E2 for ; Thu, 15 Nov 2018 16:47:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 949382CBA5 for ; Thu, 15 Nov 2018 16:47:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 861932CBE3; Thu, 15 Nov 2018 16:47:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B7C1F2CBA5 for ; Thu, 15 Nov 2018 16:47:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387833AbeKPC4Z (ORCPT ); Thu, 15 Nov 2018 21:56:25 -0500 Received: from mail-pg1-f196.google.com ([209.85.215.196]:41095 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726334AbeKPC4Z (ORCPT ); Thu, 15 Nov 2018 21:56:25 -0500 Received: by mail-pg1-f196.google.com with SMTP id 70so9256426pgh.8 for ; Thu, 15 Nov 2018 08:47:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=W82Iajos9hcmTt2AxwaM/2l7tOnESTbEN320i73dYRU=; b=CZ2YnHMJbLW3kSJxAbxGeQo/8xC0CJajSYdwHjQD6dYrnpY2FlDV9fs0mX0KI1/8Xu m/vKIWP4aRXumeCDfanSsGKMKC7G/SNRQEJbpDjdt4GMGwO20+PfOv88dv0xPrl6/aN5 FqPSJaef74KJVTv+2SJoMouKE8dWByb1NQxWM93/rAEuRljQW6+vKZe6wI0e7iIfvZzM MxM2HQVC7ASWPhsZ2hh1fb37aUt7mL0tvuvy2Zu3ZbnFnUr3ha1KPLhVlV7It3sXniwa UxCK449wkFJ/Wxyx8A5J9cC1Qy2tKeiaCwPcdKB4hnzamBHcI1pA6XvUT6AFN1j9+xFd yn+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=W82Iajos9hcmTt2AxwaM/2l7tOnESTbEN320i73dYRU=; b=gOWCmnTNTXvxcI9xx2Gy0df7tbumVS8RwbqJgGEn2I89F/que5W6jziGFMdf5vlAZc 5T/K/OeEZCp+gkfRjTsed/OXw8dUEN6/xjoHaA0AnBwATawIEOqxdjk0vOEunKESz3Kd vNk9LHrMuNz3HVTdFO+j1zhNXFqmwJ3uZTnfDP5K2O95Fejrl5mfMQpYzv2McFj/qeiV EH/ek5fBfovMz8K14ZUJjRykFgM8y+2V2EVXiuyoMy8iz0vj3Psa7EqcUfXdLs1ASXiO oX3WjvUOVu5UScXX4phQI/CSV1FWCKVY6GsAl3NF+92HY2WAPOdAtwyQtTG5+yMcyJVe 3RXQ== X-Gm-Message-State: AGRZ1gKjqkMOPdb63zSQR6N8pZccndfosUXuMePshHfmMQ7TMHOVhm04 qiI9Fc1iact8mg1IP2/TouTX4pit X-Google-Smtp-Source: AJdET5eMYtUUJqlnbWIRvDwKWAKG7MKhgumF3hI3CPT91TAyvFLpRfHZnwBJTo6cOLbDV2AJqIXlJw== X-Received: by 2002:a62:81c1:: with SMTP id t184mr166588pfd.246.1542300469584; Thu, 15 Nov 2018 08:47:49 -0800 (PST) Received: from localhost.localdomain (KD118155013174.ppp-bb.dion.ne.jp. [118.155.13.174]) by smtp.gmail.com with ESMTPSA id b27sm18494784pfh.113.2018.11.15.08.47.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Nov 2018 08:47:48 -0800 (PST) From: Yoshihiro Kaneko To: linux-renesas-soc@vger.kernel.org Cc: Laurent Pinchart , Geert Uytterhoeven , Simon Horman , Magnus Damm Subject: [PATCH/RFT v2] pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions Date: Fri, 16 Nov 2018 01:47:07 +0900 Message-Id: <1542300427-3718-1-git-send-email-ykaneko0929@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Reviewed-by: Geert Uytterhoeven --- This patch is based on the sh-pfc branch of Geert Uytterhoeven's renesas-drivers tree. v2 [Yoshihiro Kaneko] * As suggested by Geert Uytterhoeven - Fix the definition of the hscif3_data_d_pins - Update the size of the sh_pfc_pin_group.common and the sh_pfc_function.common drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 370 +++++++++++++++++++++++++++++++++- 1 file changed, 368 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c index 5d6a13f..6868753 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c @@ -1626,6 +1626,290 @@ enum { DU_DISP_MARK, }; +/* - HSCIF0 --------------------------------------------------*/ +static const unsigned int hscif0_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), +}; + +static const unsigned int hscif0_data_a_mux[] = { + HRX0_A_MARK, HTX0_A_MARK, +}; + +static const unsigned int hscif0_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 7), +}; + +static const unsigned int hscif0_clk_a_mux[] = { + HSCK0_A_MARK, +}; + +static const unsigned int hscif0_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), +}; + +static const unsigned int hscif0_ctrl_a_mux[] = { + HRTS0_N_A_MARK, HCTS0_N_A_MARK, +}; + +static const unsigned int hscif0_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; + +static const unsigned int hscif0_data_b_mux[] = { + HRX0_B_MARK, HTX0_B_MARK, +}; + +static const unsigned int hscif0_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 13), +}; + +static const unsigned int hscif0_clk_b_mux[] = { + HSCK0_B_MARK, +}; + +/* - HSCIF1 ------------------------------------------------- */ +static const unsigned int hscif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; + +static const unsigned int hscif1_data_a_mux[] = { + HRX1_A_MARK, HTX1_A_MARK, +}; + +static const unsigned int hscif1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; + +static const unsigned int hscif1_clk_a_mux[] = { + HSCK1_A_MARK, +}; + +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), +}; + +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; + +static const unsigned int hscif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(3, 0), +}; + +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, +}; + +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), +}; + +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, +}; + +/* - HSCIF2 ------------------------------------------------- */ +static const unsigned int hscif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), +}; + +static const unsigned int hscif2_data_a_mux[] = { + HRX2_A_MARK, HTX2_A_MARK, +}; + +static const unsigned int hscif2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 14), +}; + +static const unsigned int hscif2_clk_a_mux[] = { + HSCK2_A_MARK, +}; + +static const unsigned int hscif2_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15), +}; + +static const unsigned int hscif2_ctrl_a_mux[] = { + HRTS2_N_A_MARK, HCTS2_N_A_MARK, +}; + +static const unsigned int hscif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; + +static const unsigned int hscif2_data_b_mux[] = { + HRX2_B_MARK, HTX2_B_MARK, +}; + +/* - HSCIF3 ------------------------------------------------*/ +static const unsigned int hscif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; + +static const unsigned int hscif3_data_a_mux[] = { + HRX3_A_MARK, HTX3_A_MARK, +}; + +static const unsigned int hscif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), +}; + +static const unsigned int hscif3_data_b_mux[] = { + HRX3_B_MARK, HTX3_B_MARK, +}; + +static const unsigned int hscif3_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(0, 4), +}; + +static const unsigned int hscif3_clk_b_mux[] = { + HSCK3_B_MARK, +}; + +static const unsigned int hscif3_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9), +}; + +static const unsigned int hscif3_data_c_mux[] = { + HRX3_C_MARK, HTX3_C_MARK, +}; + +static const unsigned int hscif3_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 11), +}; + +static const unsigned int hscif3_clk_c_mux[] = { + HSCK3_C_MARK, +}; + +static const unsigned int hscif3_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12), +}; + +static const unsigned int hscif3_ctrl_c_mux[] = { + HRTS3_N_C_MARK, HCTS3_N_C_MARK, +}; + +static const unsigned int hscif3_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3), +}; + +static const unsigned int hscif3_data_d_mux[] = { + HRX3_D_MARK, HTX3_D_MARK, +}; + +static const unsigned int hscif3_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; + +static const unsigned int hscif3_data_e_mux[] = { + HRX3_E_MARK, HTX3_E_MARK, +}; + +static const unsigned int hscif3_ctrl_e_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8), +}; + +static const unsigned int hscif3_ctrl_e_mux[] = { + HRTS3_N_E_MARK, HCTS3_N_E_MARK, +}; + +/* - HSCIF4 -------------------------------------------------- */ +static const unsigned int hscif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), +}; + +static const unsigned int hscif4_data_a_mux[] = { + HRX4_A_MARK, HTX4_A_MARK, +}; + +static const unsigned int hscif4_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 0), +}; + +static const unsigned int hscif4_clk_a_mux[] = { + HSCK4_A_MARK, +}; + +static const unsigned int hscif4_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1), +}; + +static const unsigned int hscif4_ctrl_a_mux[] = { + HRTS4_N_A_MARK, HCTS4_N_A_MARK, +}; + +static const unsigned int hscif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), +}; + +static const unsigned int hscif4_data_b_mux[] = { + HRX4_B_MARK, HTX4_B_MARK, +}; + +static const unsigned int hscif4_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(2, 6), +}; + +static const unsigned int hscif4_clk_b_mux[] = { + HSCK4_B_MARK, +}; + +static const unsigned int hscif4_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; + +static const unsigned int hscif4_data_c_mux[] = { + HRX4_C_MARK, HTX4_C_MARK, +}; + +static const unsigned int hscif4_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), +}; + +static const unsigned int hscif4_data_d_mux[] = { + HRX4_D_MARK, HTX4_D_MARK, +}; + +static const unsigned int hscif4_data_e_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), +}; + +static const unsigned int hscif4_data_e_mux[] = { + HRX4_E_MARK, HTX4_E_MARK, +}; + /* - I2C -------------------------------------------------------------------- */ static const unsigned int i2c1_a_pins[] = { /* SCL, SDA */ @@ -3191,7 +3475,7 @@ enum { }; static const struct { - struct sh_pfc_pin_group common[207]; + struct sh_pfc_pin_group common[238]; struct sh_pfc_pin_group automotive[0]; } pinmux_groups = { .common = { @@ -3229,6 +3513,37 @@ enum { SH_PFC_PIN_GROUP(du_disp_cde), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(hscif0_data_a), + SH_PFC_PIN_GROUP(hscif0_clk_a), + SH_PFC_PIN_GROUP(hscif0_ctrl_a), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_clk_b), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_a), + SH_PFC_PIN_GROUP(hscif2_clk_a), + SH_PFC_PIN_GROUP(hscif2_ctrl_a), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_clk_b), + SH_PFC_PIN_GROUP(hscif3_data_c), + SH_PFC_PIN_GROUP(hscif3_clk_c), + SH_PFC_PIN_GROUP(hscif3_ctrl_c), + SH_PFC_PIN_GROUP(hscif3_data_d), + SH_PFC_PIN_GROUP(hscif3_data_e), + SH_PFC_PIN_GROUP(hscif3_ctrl_e), + SH_PFC_PIN_GROUP(hscif4_data_a), + SH_PFC_PIN_GROUP(hscif4_clk_a), + SH_PFC_PIN_GROUP(hscif4_ctrl_a), + SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(hscif4_clk_b), + SH_PFC_PIN_GROUP(hscif4_data_c), + SH_PFC_PIN_GROUP(hscif4_data_d), + SH_PFC_PIN_GROUP(hscif4_data_e), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c1_c), @@ -3448,6 +3763,52 @@ enum { "du_disp", }; +static const char * const hscif0_groups[] = { + "hscif0_data_a", + "hscif0_clk_a", + "hscif0_ctrl_a", + "hscif0_data_b", + "hscif0_clk_b", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_clk_a", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data_a", + "hscif2_clk_a", + "hscif2_ctrl_a", + "hscif2_data_b", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data_a", + "hscif3_data_b", + "hscif3_clk_b", + "hscif3_data_c", + "hscif3_clk_c", + "hscif3_ctrl_c", + "hscif3_data_d", + "hscif3_data_e", + "hscif3_ctrl_e", +}; + +static const char * const hscif4_groups[] = { + "hscif4_data_a", + "hscif4_clk_a", + "hscif4_ctrl_a", + "hscif4_data_b", + "hscif4_clk_b", + "hscif4_data_c", + "hscif4_data_d", + "hscif4_data_e", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -3721,13 +4082,18 @@ enum { }; static const struct { - struct sh_pfc_function common[36]; + struct sh_pfc_function common[41]; struct sh_pfc_function automotive[0]; } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif4), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c4),