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Wed, 3 Mar 2021 23:09:39 -0800 Envelope-to: michal.simek@xilinx.com, rajan.vaja@xilinx.com, manish.narani@xilinx.com, amit.sunil.dhamne@xilinx.com, nava.manne@xilinx.com, mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, chinnikishore369@gmail.com Received: from [10.140.6.60] (port=51424 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lHi79-0003nC-4t; Wed, 03 Mar 2021 23:09:39 -0800 From: Nava kishore Manne To: , , , , , , , , , , , , , , , CC: Nava kishore Manne Subject: [PATCH v3 1/3] drivers: firmware: Add PDI load API support Date: Thu, 4 Mar 2021 12:32:22 +0530 Message-ID: <20210304070224.22346-2-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210304070224.22346-1-nava.manne@xilinx.com> References: <20210304070224.22346-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5219ebc0-d279-4d5a-18cc-08d8dedc7b07 X-MS-TrafficTypeDiagnostic: SA0PR02MB7130: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:586; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2021 07:09:40.9749 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5219ebc0-d279-4d5a-18cc-08d8dedc7b07 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT047.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR02MB7130 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch adds load PDI API support to enable full/partial PDI loading from linux. Programmable Device Image (PDI) is combination of headers, images and bitstream files to be loaded. Signed-off-by: Nava kishore Manne --- Changes for v2: -Updated API Doc and commit msg. No functional changes. Changes for v3: -Added PDI_SRC_DDR macro in the firmware.h file. drivers/firmware/xilinx/zynqmp.c | 17 +++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 10 ++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 7eb9958662dd..9ee02655db89 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -897,6 +897,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, } EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement); +/** + * zynqmp_pm_load_pdi - Load and process PDI + * @src: Source device where PDI is located + * @address: PDI src address + * + * This function provides support to load PDI from linux + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_load_pdi(const u32 src, const u64 address) +{ + return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src, + lower_32_bits(address), + upper_32_bits(address), 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi); + /** * zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using * AES-GCM core. diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 2a0da841c942..3eba9d5c7640 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -52,6 +52,10 @@ #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U +/* Loader commands */ +#define PM_LOAD_PDI 0x701 +#define PDI_SRC_DDR 0xF + /* * Firmware FPGA Manager flags * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration @@ -354,6 +358,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value); int zynqmp_pm_read_pggs(u32 index, u32 *value); int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); int zynqmp_pm_set_boot_health_status(u32 value); +int zynqmp_pm_load_pdi(const u32 src, const u64 address); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { @@ -538,6 +543,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32 value) { return -ENODEV; } + +static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ From patchwork Thu Mar 4 07:02:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12115583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E65FDC433E6 for ; Thu, 4 Mar 2021 07:12:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B66B364F11 for ; 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Wed, 03 Mar 2021 23:09:44 -0800 From: Nava kishore Manne To: , , , , , , , , , , , , , , , CC: Appana Durga Kedareswara rao , "Nava kishore Manne" Subject: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga manager Date: Thu, 4 Mar 2021 12:32:23 +0530 Message-ID: <20210304070224.22346-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210304070224.22346-1-nava.manne@xilinx.com> References: <20210304070224.22346-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8e27d9b5-8449-415c-4e1e-08d8dedc869c X-MS-TrafficTypeDiagnostic: SN6PR02MB5280: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:2449; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QCjTS437AAtsCAg7bAI+u6deZHMrS94ht2yJQ1TX78QJzGArigRNRUBNWNWqpR+Clt5hYZSDNMMuHjYRNq4a9mS1yhSLZs8l7XZe2M8flIJJ1HzjSLwOOwhuvIYtoMxFadJLlQBMXLVi1qVByERHE4JFYOpzUxQfMLfXPDYs2jKHZD5wWz/3dVQGtxTIDbePlRQ5rl7uAdor9d1VW2OHTacSnRkUl182RWJB8FxG3Qbj+aovBFfgPHC5BsFGVTqRGt/yyFo6PXiexuVksahsZ5AvdMGiPb/rNVz4OCfHMLfnpud6NH3BPcQ4Ih7qxDA2QokirnULRxfkOI4FSwKaPlw30MSQL5Pn8eduAqkiRgAjxhyEAHGx/mmaHlanbhQnHMWDgi+hHnWjtW+2E/xsa4dqBuYT1AIQu7Vsv4uOG2sabJib1bg2YGVS9i50LjXrCJ7oKZ+2S2shraNzKECqr9aDVb7lqtonfpdF9EO3bimvdYDQ8XRALrqbFpwT7aVOi2hWdRKbPO0FjRHFlNE504fJHWmRz8adyQleRpAREaFv0hGqvsDeAa46aUfKN31lQwSpBcOncjUqsF8/D/ZBtRhjIipJ/Vk97c36bMl7CllPs/f9gJjU5thujXWzIvTBzHtrUsA7m71R0e86JK2pbKE5x45ErIajDoZVpjjmg7RZGP06qfO+E+cj5qLVFM1PGHCW858pSkJeYhpUdb+cSm/PbameiEsSu56WVmgmneycP4XQOUQXRjlSoSXs81BOLnk4c+A9HKCJJ/gT337qk3FLxyLsvRZXbnmcwBGZVWHW71iEeTdyqj4IPUK5Sm/a X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(356005)(7636003)(1076003)(36756003)(426003)(7696005)(336012)(70206006)(5660300002)(8936002)(54906003)(7416002)(6666004)(70586007)(9786002)(47076005)(4326008)(966005)(107886003)(110136005)(36906005)(36860700001)(921005)(186003)(498600001)(8676002)(2906002)(26005)(2616005)(82310400003)(102446001)(83996005)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2021 07:10:00.4067 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e27d9b5-8449-415c-4e1e-08d8dedc869c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT060.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5280 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Appana Durga Kedareswara rao This patch adds binding doc for versal fpga manager driver. Signed-off-by: Nava kishore Manne Signed-off-by: Appana Durga Kedareswara rao --- Changes for v2: -Fixed file format and syntax issues. Changes for v3: -Removed unwated extra spaces. .../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml new file mode 100644 index 000000000000..fec6144766fe --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal FPGA driver. + +maintainers: + - Nava kishore Manne + +description: | + Device Tree Versal FPGA bindings for the Versal SoC, controlled + using firmware interface. + +properties: + compatible: + items: + - enum: + - xlnx,versal-fpga + +required: + - compatible + +additionalProperties: false + +examples: + - | + versal_fpga: fpga { + compatible = "xlnx,versal-fpga"; + }; + +... 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Wed, 3 Mar 2021 23:09:49 -0800 Envelope-to: michal.simek@xilinx.com, rajan.vaja@xilinx.com, manish.narani@xilinx.com, amit.sunil.dhamne@xilinx.com, nava.manne@xilinx.com, appana.durga.rao@xilinx.com, mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org, gregkh@linuxfoundation.org, arnd@arndb.de, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, chinnikishore369@gmail.com Received: from [10.140.6.60] (port=51424 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lHi7I-0003nC-LY; Wed, 03 Mar 2021 23:09:49 -0800 From: Nava kishore Manne To: , , , , , , , , , , , , , , , CC: Nava kishore Manne , Appana Durga Kedareswara rao Subject: [PATCH v3 3/3] fpga: versal-fpga: Add versal fpga manager driver Date: Thu, 4 Mar 2021 12:32:24 +0530 Message-ID: <20210304070224.22346-4-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210304070224.22346-1-nava.manne@xilinx.com> References: <20210304070224.22346-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d8a1215b-91f8-4ec1-27c1-08d8dedc8f53 X-MS-TrafficTypeDiagnostic: SA2PR02MB7786: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2021 07:10:15.0198 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8a1215b-91f8-4ec1-27c1-08d8dedc8f53 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT007.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR02MB7786 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Add support for Xilinx Versal FPGA manager. PDI source type can be DDR, OCM, QSPI flash etc.. But driver allocates memory always from DDR, Since driver supports only DDR source type. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Nava kishore Manne --- Changes for v2: -Updated the Fpga Mgr registrations call's to 5.11 -Fixed some minor coding issues as suggested by Moritz. Changes for v3: -Rewritten the Versal fpga Kconfig contents. drivers/fpga/Kconfig | 9 +++ drivers/fpga/Makefile | 1 + drivers/fpga/versal-fpga.c | 117 +++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) create mode 100644 drivers/fpga/versal-fpga.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index bf85b9a65ec2..c1603c7e1518 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -223,4 +223,13 @@ config FPGA_MGR_ZYNQMP_FPGA to configure the programmable logic(PL) through PS on ZynqMP SoC. +config FPGA_MGR_VERSAL_FPGA + tristate "Xilinx Versal FPGA" + depends on ARCH_ZYNQMP || COMPILE_TEST + help + Select this option to enable FPGA manager driver support for + Xilinx Versal SoC. This driver uses the firmware interface to + configure the programmable logic(PL). + + To compile this as a module, choose M here. endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index d8e21dfc6778..40c9adb6a644 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c new file mode 100644 index 000000000000..5744e44f981d --- /dev/null +++ b/drivers/fpga/versal-fpga.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2021 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * struct versal_fpga_priv - Private data structure + * @dev: Device data structure + */ +struct versal_fpga_priv { + struct device *dev; +}; + +static int versal_fpga_ops_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t size) +{ + return 0; +} + +static int versal_fpga_ops_write(struct fpga_manager *mgr, + const char *buf, size_t size) +{ + struct versal_fpga_priv *priv; + dma_addr_t dma_addr = 0; + char *kbuf; + int ret; + + priv = mgr->priv; + + kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + memcpy(kbuf, buf, size); + + wmb(); /* ensure all writes are done before initiate FW call */ + + ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr); + + dma_free_coherent(priv->dev, size, kbuf, dma_addr); + + return ret; +} + +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + return 0; +} + +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr) +{ + return FPGA_MGR_STATE_UNKNOWN; +} + +static const struct fpga_manager_ops versal_fpga_ops = { + .state = versal_fpga_ops_state, + .write_init = versal_fpga_ops_write_init, + .write = versal_fpga_ops_write, + .write_complete = versal_fpga_ops_write_complete, +}; + +static int versal_fpga_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct versal_fpga_priv *priv; + struct fpga_manager *mgr; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret < 0) { + dev_err(dev, "no usable DMA configuration\n"); + return ret; + } + + mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager", + &versal_fpga_ops, priv); + if (!mgr) + return -ENOMEM; + + return devm_fpga_mgr_register(dev, mgr); +} + +static const struct of_device_id versal_fpga_of_match[] = { + { .compatible = "xlnx,versal-fpga", }, + {}, +}; +MODULE_DEVICE_TABLE(of, versal_fpga_of_match); + +static struct platform_driver versal_fpga_driver = { + .probe = versal_fpga_probe, + .driver = { + .name = "versal_fpga_manager", + .of_match_table = of_match_ptr(versal_fpga_of_match), + }, +}; +module_platform_driver(versal_fpga_driver); + +MODULE_AUTHOR("Nava kishore Manne "); +MODULE_AUTHOR("Appana Durga Kedareswara rao "); +MODULE_DESCRIPTION("Xilinx Versal FPGA Manager"); +MODULE_LICENSE("GPL");