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dmarc=none action=none header.from=nxp.com; Received: from DB8PR04MB6795.eurprd04.prod.outlook.com (2603:10a6:10:fa::15) by DBBPR04MB6249.eurprd04.prod.outlook.com (2603:10a6:10:c6::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3890.23; Thu, 4 Mar 2021 11:40:06 +0000 Received: from DB8PR04MB6795.eurprd04.prod.outlook.com ([fe80::7d13:2d65:d6f7:b978]) by DB8PR04MB6795.eurprd04.prod.outlook.com ([fe80::7d13:2d65:d6f7:b978%4]) with mapi id 15.20.3890.029; Thu, 4 Mar 2021 11:40:06 +0000 From: Joakim Zhang To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com Cc: kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V1] arm64: dts: imx8mp: fix FEC can't work when attached to generic phy driver Date: Thu, 4 Mar 2021 19:40:13 +0800 Message-Id: <20210304114013.18494-1-qiangqing.zhang@nxp.com> X-Mailer: git-send-email 2.17.1 X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: HK2PR02CA0143.apcprd02.prod.outlook.com (2603:1096:202:16::27) To DB8PR04MB6795.eurprd04.prod.outlook.com (2603:10a6:10:fa::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by HK2PR02CA0143.apcprd02.prod.outlook.com (2603:1096:202:16::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3912.17 via Frontend Transport; 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The root cause should be FEC controller attached to generic phy driver, as Realtek phy driver is built as module in the defconfig file (CONFIG_REALTEK_PHY=m), so it is unavailable. If provide "reset-gpios" property, it will reset phy when probed, and no way to re-config phy since we use the generic phy dirver, which leads FEC can't work. There are two ways to let FEC work: 1. If you want to use generic phy dirver, please delete "reset-gpios" property, keep power-on strapping pins configurations. 2. If you want to use Realtek phy driver, please buildin driver (CONFIG_REALTEK_PHY=y), and had better add another two reset properties: reset-assert-us = <20000>; reset-deassert-us = <150000>; According to RTL8211 serials PHY datasheet, for a complete PHY reset, reset pin must be asserted low for at least 10ms for internal regulator. Wait for at least 72ms (for internal circuits settling time) before accessing the PHY register. This patch selects method 1, since users may waste time to find out FEC failure, in most cases, they just want to use networking to debug other modules. Fixs: commit 9e847693c6f34 ("arm64: dts: freescale: Add i.MX8MP EVK board support") Signed-off-by: Joakim Zhang --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 7db4273cc88b..4f5c2fb33eda 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -97,7 +97,6 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; eee-broken-1000t; - reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; }; }; };