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[2003:dc:d717:a100:6d21:4a3b:238:44e6]) by smtp.googlemail.com with ESMTPSA id z192-v6sm16610273wmc.37.2018.11.16.12.53.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Nov 2018 12:53:33 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, narmstrong@baylibre.com, jbrunet@baylibre.com Subject: [PATCH 1/3] dt-bindings: clock: meson8b: export the CPU post dividers Date: Fri, 16 Nov 2018 21:53:01 +0100 Message-Id: <20181116205303.6354-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181116205303.6354-1-martin.blumenstingl@googlemail.com> References: <20181116205303.6354-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181116_125346_370556_30C18028 X-CRM114-Status: UNSURE ( 9.03 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sboyd@kernel.org, mturquette@baylibre.com, linux-kernel@vger.kernel.org, Martin Blumenstingl , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP There are four CPU clock post dividers: - ABP - PERIPH (used as input for the ARM global timer and ARM TWD timer) - AXI - L2 DRAM Export these so we can use them in .dts files. Signed-off-by: Martin Blumenstingl --- include/dt-bindings/clock/meson8b-clkc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index a60f47b49231..5fe2923382d0 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -103,5 +103,9 @@ #define CLKID_MPLL1 94 #define CLKID_MPLL2 95 #define CLKID_NAND_CLK 112 +#define CLKID_ABP 124 +#define CLKID_PERIPH 126 +#define CLKID_AXI 128 +#define CLKID_L2_DRAM 130 #endif /* __MESON8B_CLKC_H */ From patchwork Fri Nov 16 20:53:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 10687033 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D3B413BB for ; Fri, 16 Nov 2018 20:54:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0E2F22D84E for ; Fri, 16 Nov 2018 20:54:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 021432D855; Fri, 16 Nov 2018 20:54:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_LOW autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 99FBC2D850 for ; Fri, 16 Nov 2018 20:54:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dJgsKrQ2I6HpUeqHkaFA7G6TRK9Jkv879mlBrhDRjUI=; b=L4IemN5zszE8Wq zNthaO/dGRWciYR9F5XS8Q/BB0UL9jpn8y7XV9PhPFstUPru4948t1Ds9BOrSLr/MQrZPnl4QzisO sEAiy3m/pb/uSvXsug7GbTrQqKsFnmZJo7PZqpyEekSRl6eoyJ1O7/Ae/67WOZajkk1EmrIQx7mcH AOaFSWAPne/RptIRr1hf8G95vm4188RXSC+wO0w7S/ZRunVW2qDrnABDW3xvhFOdWIrxdJTyqKxau x4MbJLeoAReomgF71XMXv7xRwIIzbmIk9XkDZvA4EVrlyE4LA6ztVw7BNnletoQQ+UPvW2/BOL8qr dIrhJ79WyeaqGyGN20Ng==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gNl82-0007iS-Hj; Fri, 16 Nov 2018 20:54:14 +0000 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gNl7a-0007BY-Au; Fri, 16 Nov 2018 20:53:48 +0000 Received: by mail-wm1-x341.google.com with SMTP id w7-v6so23278633wmc.1; Fri, 16 Nov 2018 12:53:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Izxh6fMVFA/0xS9HV67hZayJ5aOEqsM4QOvWs81PQVU=; b=gsJZQ1egd9+5PkkoGRPjP0LHWw0lAYfyRN+yaJLyTKOtRCg4NDBmzCQUYoEqi7NYH2 it+c6K81Gyz/7G2g3vgaE1i173cX7xGxJ3C4gxChqMa7bVQ+a623EhJtBvUGAQ/PI1QW Hn7bSyWkQjg0fv3XorWcbgc5CRHw2OjbMDEKCnBpWZ1YzB0Ai4M6wyGQHWMeQktudMEj BCh0omlWnDRpcsY6i9Ntb1IwPpyVigNK13AT/x0pJTB1LEuTWx2mJ9korhV5+ynq0mBI Hba4VqV/xXe0LgFfB/b5SCw2NSFICgud2e5FdedBX/3L+Ngdh7gP0RHjwrYTaSTlZpUS lZCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Izxh6fMVFA/0xS9HV67hZayJ5aOEqsM4QOvWs81PQVU=; b=SnGBPN5Pd81my2Tegm0Ba0hRNghxHHyyTOFyj6Y9QGCPvjGN9G6iGlHqBgJDijZRR/ r1gnSXWMKYKqD8861GqCyKuz8qa9v7RxDvYb6sCDgbwrzty9BYMzTGN0ZK8GiokuWVhh 24ayOvTI/KCnv1ZnGszUaSxigXQWPVMg8jTTNPsRUk+K+cd6CJWBa3n2qdpIhwrQy49O ko5nOgy+3wHe63hHIPgZMWd1yUZYN/vyc/FpbYTLzgvCEptSPnpRdu7RE7NH2iPrmamc PXU63oC9hgjGvVGLpy++vp1uZWxMVGkf1c2DoVoUxkO8q4wiThR8H0N8B9cnkKwM5yfH sqpg== X-Gm-Message-State: AGRZ1gJPGeLdTj7ibY8RGZXL645/SYCrSSqpZIDY2mhisKYXFBYQH4jN 05jScjdwzPrduGeM8bF1KA9c20VF X-Google-Smtp-Source: AJdET5cqHu6LyqUnrTbDjCbIoLjE3dF5OytwpD9HmF16C+2MUrpVtRzGSQ1GiH7o+Rr3vI6l9A17wg== X-Received: by 2002:a1c:730b:: with SMTP id d11-v6mr3584054wmb.107.1542401615615; Fri, 16 Nov 2018 12:53:35 -0800 (PST) Received: from blackbox.darklights.net (p200300DCD717A1006D214A3B023844E6.dip0.t-ipconnect.de. [2003:dc:d717:a100:6d21:4a3b:238:44e6]) by smtp.googlemail.com with ESMTPSA id z192-v6sm16610273wmc.37.2018.11.16.12.53.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Nov 2018 12:53:34 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, narmstrong@baylibre.com, jbrunet@baylibre.com Subject: [PATCH 2/3] clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 Date: Fri, 16 Nov 2018 21:53:02 +0100 Message-Id: <20181116205303.6354-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181116205303.6354-1-martin.blumenstingl@googlemail.com> References: <20181116205303.6354-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181116_125346_370751_4CE6D6EF X-CRM114-Status: GOOD ( 14.52 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sboyd@kernel.org, mturquette@baylibre.com, linux-kernel@vger.kernel.org, Martin Blumenstingl , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The "cpu_div2" and "cpu_div3" take "cpu_in" as input and divide that by 2 or 3. The clock controller can also generate various CPU clock post-dividers (2, 3, 4, 5, 6, 7, 8) which are derived from "cpu_clk". When adding support for these post-dividers our clock naming could be misleading as we have "cpu_div2" as well as "cpu_clk_div2". Rename the existing "cpu_in" dividers so the name of the divider's parent is part of the divider clock's name. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 20 ++++++++++---------- drivers/clk/meson/meson8b.h | 4 ++-- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index b3bdc7e05441..010dccc86b5d 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -560,11 +560,11 @@ static struct clk_regmap meson8b_cpu_in_sel = { }, }; -static struct clk_fixed_factor meson8b_cpu_div2 = { +static struct clk_fixed_factor meson8b_cpu_in_div2 = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ - .name = "cpu_div2", + .name = "cpu_in_div2", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "cpu_in_sel" }, .num_parents = 1, @@ -572,11 +572,11 @@ static struct clk_fixed_factor meson8b_cpu_div2 = { }, }; -static struct clk_fixed_factor meson8b_cpu_div3 = { +static struct clk_fixed_factor meson8b_cpu_in_div3 = { .mult = 1, .div = 3, .hw.init = &(struct clk_init_data){ - .name = "cpu_div3", + .name = "cpu_in_div3", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "cpu_in_sel" }, .num_parents = 1, @@ -626,12 +626,12 @@ static struct clk_regmap meson8b_cpu_scale_out_sel = { .ops = &clk_regmap_mux_ops, /* * NOTE: We are skipping the parent with value 0x2 (which is - * "cpu_div3") because it results in a duty cycle of 33% which - * makes the system unstable and can result in a lockup of the - * whole system. + * "cpu_in_div3") because it results in a duty cycle of 33% + * which makes the system unstable and can result in a lockup + * of the whole system. */ .parent_names = (const char *[]) { "cpu_in_sel", - "cpu_div2", + "cpu_in_div2", "cpu_scale_div" }, .num_parents = 3, .flags = CLK_SET_RATE_PARENT, @@ -889,8 +889,8 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, - [CLKID_CPU_DIV2] = &meson8b_cpu_div2.hw, - [CLKID_CPU_DIV3] = &meson8b_cpu_div3.hw, + [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, + [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 1c6fb180e6a2..9cba34c6cb92 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -63,8 +63,8 @@ #define CLKID_MPLL1_DIV 97 #define CLKID_MPLL2_DIV 98 #define CLKID_CPU_IN_SEL 99 -#define CLKID_CPU_DIV2 100 -#define CLKID_CPU_DIV3 101 +#define CLKID_CPU_IN_DIV2 100 +#define CLKID_CPU_IN_DIV3 101 #define CLKID_CPU_SCALE_DIV 102 #define CLKID_CPU_SCALE_OUT_SEL 103 #define CLKID_MPLL_PREDIV 104 From patchwork Fri Nov 16 20:53:03 2018 Content-Type: text/plain; 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[2003:dc:d717:a100:6d21:4a3b:238:44e6]) by smtp.googlemail.com with ESMTPSA id z192-v6sm16610273wmc.37.2018.11.16.12.53.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Nov 2018 12:53:36 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, narmstrong@baylibre.com, jbrunet@baylibre.com Subject: [PATCH 3/3] clk: meson: meson8b: add the CPU clock post divider clocks Date: Fri, 16 Nov 2018 21:53:03 +0100 Message-Id: <20181116205303.6354-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181116205303.6354-1-martin.blumenstingl@googlemail.com> References: <20181116205303.6354-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181116_125348_795692_C1338FA6 X-CRM114-Status: GOOD ( 13.44 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sboyd@kernel.org, mturquette@baylibre.com, linux-kernel@vger.kernel.org, Martin Blumenstingl , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP There are four CPU clock post dividers: - ABP - PERIPH (used for the ARM global timer and ARM TWD timer) - AXI - L2 DRAM Each of these clocks consists of two clocks: - a mux to select between "cpu_clk" divided by 2, 3, 4, 5, 6, 7 or 8 - a "_clk_dis" gate (the public S805 datasheet states that this should be set to 1 to disable the clock. the default value is 0. there is also a hint that these are "just in case" bits which is why I set these clocks to CLK_IS_CRITICAL). Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 248 ++++++++++++++++++++++++++++++++++++ drivers/clk/meson/meson8b.h | 13 +- 2 files changed, 260 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 010dccc86b5d..1b192f823bf8 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -704,6 +704,231 @@ static struct clk_regmap meson8b_nand_clk_gate = { }, }; +static struct clk_fixed_factor meson8b_cpu_clk_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div2", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div3 = { + .mult = 1, + .div = 3, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div3", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div4 = { + .mult = 1, + .div = 4, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div4", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div5 = { + .mult = 1, + .div = 5, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div5", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div6 = { + .mult = 1, + .div = 6, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div6", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div7 = { + .mult = 1, + .div = 7, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div7", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div8 = { + .mult = 1, + .div = 8, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div8", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static u32 mux_table_abp[] = { 1, 2, 3, 4, 5, 6, 7 }; +static struct clk_regmap meson8b_abp_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 3, + .table = mux_table_abp, + }, + .hw.init = &(struct clk_init_data){ + .name = "abp_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_abp_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 16, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "abp_clk_dis", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "abp_clk_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL), + }, +}; + +static struct clk_regmap meson8b_periph_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "periph_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_periph_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 17, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "periph_clk_dis", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "periph_clk_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL), + }, +}; + +static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 }; +static struct clk_regmap meson8b_axi_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 9, + .table = mux_table_axi, + }, + .hw.init = &(struct clk_init_data){ + .name = "axi_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_axi_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 18, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "axi_clk_dis", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "axi_clk_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL), + }, +}; + +static struct clk_regmap meson8b_l2_dram_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 12, + }, + .hw.init = &(struct clk_init_data){ + .name = "l2_dram_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_l2_dram_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 19, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "l2_dram_clk_dis", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "l2_dram_clk_sel" }, + .num_parents = 1, + .flags = (CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL), + }, +}; + /* Everything Else (EE) domain gates */ static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); @@ -905,6 +1130,21 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, [CLKID_PLL_VID_DCO] = &meson8b_vid_pll_dco.hw, [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, + [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, + [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, + [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, + [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, + [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, + [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, + [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, + [CLKID_ABP_SEL] = &meson8b_abp_clk_sel.hw, + [CLKID_ABP] = &meson8b_abp_clk_gate.hw, + [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, + [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, + [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, + [CLKID_AXI] = &meson8b_axi_clk_gate.hw, + [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, + [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -1016,6 +1256,14 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_fixed_pll_dco, &meson8b_vid_pll_dco, &meson8b_sys_pll_dco, + &meson8b_abp_clk_sel, + &meson8b_abp_clk_gate, + &meson8b_periph_clk_sel, + &meson8b_periph_clk_gate, + &meson8b_axi_clk_sel, + &meson8b_axi_clk_gate, + &meson8b_l2_dram_clk_sel, + &meson8b_l2_dram_clk_gate, }; static const struct meson8b_clk_reset_line { diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 9cba34c6cb92..0abb331162ab 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -78,8 +78,19 @@ #define CLKID_PLL_FIXED_DCO 113 #define CLKID_PLL_VID_DCO 114 #define CLKID_PLL_SYS_DCO 115 +#define CLKID_CPU_CLK_DIV2 116 +#define CLKID_CPU_CLK_DIV3 117 +#define CLKID_CPU_CLK_DIV4 118 +#define CLKID_CPU_CLK_DIV5 119 +#define CLKID_CPU_CLK_DIV6 120 +#define CLKID_CPU_CLK_DIV7 121 +#define CLKID_CPU_CLK_DIV8 122 +#define CLKID_ABP_SEL 123 +#define CLKID_PERIPH_SEL 125 +#define CLKID_AXI_SEL 127 +#define CLKID_L2_DRAM_SEL 129 -#define CLK_NR_CLKS 116 +#define CLK_NR_CLKS 131 /* * include the CLKID and RESETID that have