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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id v3sm8394307pff.217.2021.03.07.19.58.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Mar 2021 19:58:31 -0800 (PST) From: Vincent Chen To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: Frank.Zhao@starfivetech.com, atish.patra@wdc.com, anup.patel@wdc.com, guoren@kernel.org, alankao@andestech.com, paul.walmsley@sifive.com, Vincent Chen Subject: [RFC patch 1/4] riscv: Add 3 SBI wrapper functions to get cpu manufacturer information Date: Mon, 8 Mar 2021 11:58:14 +0800 Message-Id: <1615175897-23509-2-git-send-email-vincent.chen@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1615175897-23509-1-git-send-email-vincent.chen@sifive.com> References: <1615175897-23509-1-git-send-email-vincent.chen@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_035833_527875_FD32D4E4 X-CRM114-Status: UNSURE ( 9.47 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add 3 wrapper functions to get vendor id, architecture id and implement id from M-mode Signed-off-by: Vincent Chen --- arch/riscv/include/asm/sbi.h | 3 +++ arch/riscv/kernel/sbi.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 99895d9c3bdd..94a7f664caf4 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -97,6 +97,9 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, void sbi_console_putchar(int ch); int sbi_console_getchar(void); +long sbi_get_vendorid(void); +long sbi_get_archid(void); +long sbi_get_impid(void); void sbi_set_timer(uint64_t stime_value); void sbi_shutdown(void); void sbi_clear_ipi(void); diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index f4a7db3d309e..33e3a9d6efab 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -547,6 +547,21 @@ static inline long sbi_get_firmware_version(void) return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION); } +long sbi_get_vendorid(void) +{ + return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID); +} + +long sbi_get_archid(void) +{ + return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID); +} + +long sbi_get_impid(void) +{ + return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID); +} + static void sbi_send_cpumask_ipi(const struct cpumask *target) { struct cpumask hartid_mask; From patchwork Mon Mar 8 03:58:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Chen X-Patchwork-Id: 12121381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6171AC433E0 for ; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id v3sm8394307pff.217.2021.03.07.19.58.32 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Mar 2021 19:58:33 -0800 (PST) From: Vincent Chen To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: Frank.Zhao@starfivetech.com, atish.patra@wdc.com, anup.patel@wdc.com, guoren@kernel.org, alankao@andestech.com, paul.walmsley@sifive.com, Vincent Chen Subject: [RFC patch 2/4] riscv: Get CPU manufacturer information Date: Mon, 8 Mar 2021 11:58:15 +0800 Message-Id: <1615175897-23509-3-git-send-email-vincent.chen@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1615175897-23509-1-git-send-email-vincent.chen@sifive.com> References: <1615175897-23509-1-git-send-email-vincent.chen@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_035835_994211_E9A21BD8 X-CRM114-Status: GOOD ( 13.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Issue 3 SBI calls to get the vendor ID, architecture ID and implementation ID early in boot so we only need to take the SBI call overhead once. Signed-off-by: Vincent Chen Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/csr.h | 3 +++ arch/riscv/include/asm/hwcap.h | 6 ++++++ arch/riscv/include/asm/processor.h | 2 ++ arch/riscv/include/asm/soc.h | 1 + arch/riscv/kernel/cpufeature.c | 17 +++++++++++++++++ arch/riscv/kernel/setup.c | 2 ++ arch/riscv/kernel/soc.c | 1 + 7 files changed, 32 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index caadfc1d7487..87ac65696871 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -115,6 +115,9 @@ #define CSR_MIP 0x344 #define CSR_PMPCFG0 0x3a0 #define CSR_PMPADDR0 0x3b0 +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 #ifdef CONFIG_RISCV_M_MODE diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5ce50468aff1..b7409487c9d2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -44,6 +44,12 @@ bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit); #define riscv_isa_extension_available(isa_bitmap, ext) \ __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext) +struct cpu_manufacturer_info_t { + unsigned long vendor_id; + unsigned long arch_id; + unsigned long imp_id; +}; + #endif #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 3a240037bde2..4e11a9621d14 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -72,6 +72,8 @@ int riscv_of_parent_hartid(struct device_node *node); extern void riscv_fill_hwcap(void); +void riscv_fill_cpu_manufacturer_info(void); + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/asm/soc.h b/arch/riscv/include/asm/soc.h index f494066051a2..03dee6db404c 100644 --- a/arch/riscv/include/asm/soc.h +++ b/arch/riscv/include/asm/soc.h @@ -10,6 +10,7 @@ #include #include #include +#include #define SOC_EARLY_INIT_DECLARE(name, compat, fn) \ static const struct of_device_id __soc_early_init__##name \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index ac202f44a670..389162ee19ea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include unsigned long elf_hwcap __read_mostly; @@ -22,6 +24,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; bool has_fpu __read_mostly; #endif +struct cpu_manufacturer_info_t cpu_mfr_info; + /** * riscv_isa_extension_base() - Get base extension word * @@ -149,3 +153,16 @@ void riscv_fill_hwcap(void) has_fpu = true; #endif } + +void riscv_fill_cpu_manufacturer_info(void) +{ +#ifndef CONFIG_RISCV_M_MODE + cpu_mfr_info.vendor_id = sbi_get_vendorid(); + cpu_mfr_info.arch_id = sbi_get_archid(); + cpu_mfr_info.imp_id = sbi_get_impid(); +#else + cpu_mfr_info.vendor_id = csr_read(CSR_MVENDORID); + cpu_mfr_info.arch_id = csr_read(CSR_MARCHID); + cpu_mfr_info.imp_id = csr_read(CSR_MIMPID); +#endif +} diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index e85bacff1b50..03621ce9092c 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -278,6 +278,8 @@ void __init setup_arch(char **cmdline_p) #endif riscv_fill_hwcap(); + + riscv_fill_cpu_manufacturer_info(); } static int __init topology_init(void) diff --git a/arch/riscv/kernel/soc.c b/arch/riscv/kernel/soc.c index a0516172a33c..58f6fd91743a 100644 --- a/arch/riscv/kernel/soc.c +++ b/arch/riscv/kernel/soc.c @@ -6,6 +6,7 @@ #include #include #include +#include /* * This is called extremly early, before parse_dtb(), to allow initializing From patchwork Mon Mar 8 03:58:16 2021 Content-Type: text/plain; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id v3sm8394307pff.217.2021.03.07.19.58.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Mar 2021 19:58:36 -0800 (PST) From: Vincent Chen To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: Frank.Zhao@starfivetech.com, atish.patra@wdc.com, anup.patel@wdc.com, guoren@kernel.org, alankao@andestech.com, paul.walmsley@sifive.com, Vincent Chen Subject: [RFC patch 3/4] riscv: Introduce alternative mechanism to apply errata solution Date: Mon, 8 Mar 2021 11:58:16 +0800 Message-Id: <1615175897-23509-4-git-send-email-vincent.chen@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1615175897-23509-1-git-send-email-vincent.chen@sifive.com> References: <1615175897-23509-1-git-send-email-vincent.chen@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_035838_789886_339BDF8C X-CRM114-Status: GOOD ( 31.14 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Introduce the "alternative" mechanism from ARM64 and x86 to apply the CPU vendors' errata solution at runtime. The main purpose of this patch is to provide a framework. Therefore, the implementation is quite basic for now so that some scenarios could not use this schemei, such as patching code to a module, relocating the patching code and heterogeneous CPU topology. Users could use the macro ALTERNATIVE to apply an errata to the existing code flow. In the macro ALTERNATIVE, users need to specify the manufacturer information(vendorid, archid, and impid) for this errata. Therefore, kernel will know this errata is suitable for which CPU core. During the booting procedure, kernel will select the errata required by the CPU core and then patch it. It means that the kernel only applies the errata to the specified CPU core. In this case the vendor's errata does not affect each other at runtime. The above patching procedure only occurs during the booting phase, so we only take the overhead of the "alternative" mechanism once. This "alternative" mechanism is enabled by default to ensure that all required errata will be applied. However, users can disable this feature by the Kconfig "CONFIG_RISCV_ERRATA_ALTERNATIVE". Signed-off-by: Vincent Chen --- arch/riscv/Kconfig | 1 + arch/riscv/Kconfig.erratas | 12 +++ arch/riscv/Makefile | 1 + arch/riscv/errata/Makefile | 1 + arch/riscv/errata/alternative.c | 69 +++++++++++++++++ arch/riscv/include/asm/alternative-macros.h | 110 ++++++++++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 44 +++++++++++ arch/riscv/include/asm/asm.h | 1 + arch/riscv/include/asm/errata_list.h | 8 ++ arch/riscv/include/asm/sections.h | 2 + arch/riscv/include/asm/vendorid_list.h | 6 ++ arch/riscv/kernel/smpboot.c | 4 + arch/riscv/kernel/vmlinux.lds.S | 14 ++++ 13 files changed, 273 insertions(+) create mode 100644 arch/riscv/Kconfig.erratas create mode 100644 arch/riscv/errata/Makefile create mode 100644 arch/riscv/errata/alternative.c create mode 100644 arch/riscv/include/asm/alternative-macros.h create mode 100644 arch/riscv/include/asm/alternative.h create mode 100644 arch/riscv/include/asm/errata_list.h create mode 100644 arch/riscv/include/asm/vendorid_list.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a998babc1237..2e26251fe1f2 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -204,6 +204,7 @@ config LOCKDEP_SUPPORT def_bool y source "arch/riscv/Kconfig.socs" +source "arch/riscv/Kconfig.erratas" menu "Platform type" diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas new file mode 100644 index 000000000000..4d0bafc536df --- /dev/null +++ b/arch/riscv/Kconfig.erratas @@ -0,0 +1,12 @@ +menu "CPU errata selection" + +config RISCV_ERRATA_ALTERNATIVE + bool "RISC-V alternative scheme" + default y + help + This Kconfig allows the kernel to automatically patch the + errata required by the execution platform at run time. The + code patching is performed once in the boot stages. It means + that the overhead from this mechanism is just taken once. + +endmenu diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 1368d943f1f3..1f5c03082976 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -87,6 +87,7 @@ KBUILD_IMAGE := $(boot)/Image.gz head-y := arch/riscv/kernel/head.o core-y += arch/riscv/ +core-$(CONFIG_RISCV_ERRATA_ALTERNATIVE) += arch/riscv/errata/ libs-y += arch/riscv/lib/ libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile new file mode 100644 index 000000000000..43e6d5424367 --- /dev/null +++ b/arch/riscv/errata/Makefile @@ -0,0 +1 @@ +obj-y += alternative.o diff --git a/arch/riscv/errata/alternative.c b/arch/riscv/errata/alternative.c new file mode 100644 index 000000000000..052affdce6eb --- /dev/null +++ b/arch/riscv/errata/alternative.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * alternative runtime patching + * inspired by the ARM64 and x86 version + * + * Copyright (C) 2021 Sifive. + */ + +#include +#include +#include +#include +#include +#include + +struct alt_region { + struct alt_entry *begin; + struct alt_entry *end; +}; + +static bool (*errata_checkfunc)(struct alt_entry *alt); +typedef int (*patch_func_t)(void *addr, const void *insn, size_t size); + +static void __apply_alternatives(void *alt_region, void *alt_patch_func) +{ + struct alt_entry *alt; + struct alt_region *region = alt_region; + + for (alt = region->begin; alt < region->end; alt++) { + if (!errata_checkfunc(alt)) + continue; + ((patch_func_t)alt_patch_func)(alt->old_ptr, alt->alt_ptr, alt->alt_len); + } +} + +static void __init init_alternative(void) +{ + struct errata_checkfunc_id *ptr; + + for (ptr = (struct errata_checkfunc_id *)__alt_checkfunc_table; + ptr < (struct errata_checkfunc_id *)__alt_checkfunc_table_end; + ptr++) { + if (cpu_mfr_info.vendor_id == ptr->vendor_id) + errata_checkfunc = ptr->func; + } +} + +/* + * This is called very early in the boot process (directly after we run + * a feature detect on the boot CPU). No need to worry about other CPUs + * here. + */ +void __init apply_boot_alternatives(void) +{ + struct alt_region region; + + /* If called on non-boot cpu things could go wrong */ + WARN_ON(smp_processor_id() != 0); + + init_alternative(); + + if (!errata_checkfunc) + return; + + region.begin = (struct alt_entry *)__alt_start; + region.end = (struct alt_entry *)__alt_end; + __apply_alternatives(®ion, patch_text_nosync); +} + diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h new file mode 100644 index 000000000000..7b6f0c94b1fb --- /dev/null +++ b/arch/riscv/include/asm/alternative-macros.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_ALTERNATIVE_MACROS_H +#define __ASM_ALTERNATIVE_MACROS_H + +#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE + +#ifndef __ASSEMBLY__ + +#include +#include + +#define ALT_ENTRY(oldptr, altptr, vendor_id, errata_id, altlen) \ + RISCV_PTR " " oldptr "\n" \ + RISCV_PTR " " altptr "\n" \ + REG_ASM " " vendor_id "\n" \ + REG_ASM " " altlen "\n" \ + ".word " errata_id "\n" + +#define __ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, enable) \ + "886 :\n" \ + oldinsn "\n" \ + ".if " __stringify(enable) " == 1\n" \ + "887 :\n" \ + ".pushsection .alternative, \"a\"\n" \ + ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \ + ".popsection\n" \ + ".subsection 1\n" \ + "888 :\n" \ + altinsn "\n" \ + "889 :\n" \ + ".previous\n" \ + ".org . - (887b - 886b) + (889b - 888b)\n" \ + ".org . - (889b - 888b) + (887b - 886b)\n" \ + ".endif\n" + +#define _ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) \ + __ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, IS_ENABLED(CONFIG_k)) + +#else /* __ASSEMBLY__ */ + +.macro ALT_ENTRY oldptr altptr vendor_id errata_id alt_len + RISCV_PTR \oldptr + RISCV_PTR \altptr + REG_ASM \vendor_id + REG_ASM \alt_len + .word \errata_id +.endm + +.macro __ALTERNATIVE_CFG insn1 insn2 vendor_id errata_id enable = 1 +886 : + \insn1 + .if \enable +887 : + .pushsection .alternative, "a" + ALT_ENTRY 886b, 888f, \vendor_id, \errata_id, 889f - 888f + .popsection + .subsection 1 +888 : + \insn2 +889 : + .previous + .org . - (889b - 888b) + (887b - 886b) + .org . - (887b - 886b) + (889b - 888b) + .endif +.endm + +#define _ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) \ + __ALTERNATIVE_CFG oldinsn, altinsn, vendor_id, errata_id, IS_ENABLED(CONFIG_k) + +#endif /* !__ASSEMBLY__ */ + +#else /* !CONFIG_RISCV_ERRATA_ALTERNATIVE*/ +#ifndef __ASSEMBLY__ + +#define __ALTERNATIVE_CFG(oldinsn) \ + oldinsn "\n" + +#define _ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) \ + __ALTERNATIVE_CFG(oldinsn) + +#else /* __ASSEMBLY__ */ + +.macro __ALTERNATIVE_CFG insn1 + \insn1 +.endm + +#define _ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) \ + __ALTERNATIVE_CFG oldinsn + +#endif /* !__ASSEMBLY__ */ +#endif /* CONFIG_RISCV_ERRATA_ALTERNATIVE */ + +/* + * Usage: + * ALTERNATIVE(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) + * in the assembly code. Otherwise, + * asm(ALTERNATIVE(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k)); + * + * oldinsn: The old instruction which will be replaced. + * altinsn: The replacement instruction. + * vendor_id: The CPU vendor ID. + * errata_id: The errata ID. + * CONFIG_k: The Kconfig of this errata. The instructions replacement can + * be disabled by this Kconfig. When Kconfig is disabled, the + * oldinsn will always be executed. + */ +#define ALTERNATIVE(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) \ + _ALTERNATIVE_CFG(oldinsn, altinsn, vendor_id, errata_id, CONFIG_k) + +#endif diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h new file mode 100644 index 000000000000..98a0ea331a27 --- /dev/null +++ b/arch/riscv/include/asm/alternative.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Sifive. + */ + +#ifndef __ASM_ALTERNATIVE_H +#define __ASM_ALTERNATIVE_H + +#define ERRATA_STRING_LENGTH_MAX 32 + +#include + +#ifndef __ASSEMBLY__ + +#include +#include +#include +#include + +void __init apply_boot_alternatives(void); + +struct alt_entry { + void *old_ptr; /* address of original instruciton or data */ + void *alt_ptr; /* address of replacement instruction or data */ + unsigned long vendor_id; /* cpu vendor id */ + unsigned long alt_len; /* The replacement size */ + unsigned int errata_id; /* The errata id */ +} __packed; + +struct errata_checkfunc_id { + unsigned long vendor_id; + bool (*func)(struct alt_entry *alt); +}; + +extern struct cpu_manufacturer_info_t cpu_mfr_info; + +#define REGISTER_ERRATA_CHECKFUNC(checkfunc, vendorid) \ + static const struct errata_checkfunc_id _errata_check_##vendorid \ + __used __section(".alt_checkfunc_table") \ + __aligned(__alignof__(struct errata_checkfunc_id)) = \ + { .vendor_id = vendorid, \ + .func = checkfunc } +#endif +#endif diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index 9c992a88d858..e20646aa97e5 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -23,6 +23,7 @@ #define REG_L __REG_SEL(ld, lw) #define REG_S __REG_SEL(sd, sw) #define REG_SC __REG_SEL(sc.d, sc.w) +#define REG_ASM __REG_SEL(.dword, .word) #define SZREG __REG_SEL(8, 4) #define LGREG __REG_SEL(3, 2) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h new file mode 100644 index 000000000000..5e5a1fcd90ba --- /dev/null +++ b/arch/riscv/include/asm/errata_list.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Sifive. + */ + +#ifdef CONFIG_SOC_SIFIVE +#define ERRATA_NUMBER 0 +#endif diff --git a/arch/riscv/include/asm/sections.h b/arch/riscv/include/asm/sections.h index 1595c5b60cfd..d13160f46d4e 100644 --- a/arch/riscv/include/asm/sections.h +++ b/arch/riscv/include/asm/sections.h @@ -11,5 +11,7 @@ extern char _start[]; extern char _start_kernel[]; extern char __init_data_begin[], __init_data_end[]; extern char __init_text_begin[], __init_text_end[]; +extern char __alt_checkfunc_table[], __alt_checkfunc_table_end[]; +extern char __alt_start[], __alt_end[]; #endif /* __ASM_SECTIONS_H */ diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h new file mode 100644 index 000000000000..1f3be47decb6 --- /dev/null +++ b/arch/riscv/include/asm/vendorid_list.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 SiFive + */ + +#define SIFIVE_VENDOR_ID 0x489 diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 5e276c25646f..9a408e2942ac 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "head.h" @@ -40,6 +41,9 @@ static DECLARE_COMPLETION(cpu_running); void __init smp_prepare_boot_cpu(void) { init_cpu_topology(); +#ifdef CONFIG_RISCV_ERRATA_ALTERNATIVE + apply_boot_alternatives(); +#endif } void __init smp_prepare_cpus(unsigned int max_cpus) diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S index de03cb22d0e9..6503dfca65b0 100644 --- a/arch/riscv/kernel/vmlinux.lds.S +++ b/arch/riscv/kernel/vmlinux.lds.S @@ -90,6 +90,20 @@ SECTIONS } __init_data_end = .; + + . = ALIGN(8); + .alt_checkfunc_table : { + __alt_checkfunc_table = .; + *(.alt_checkfunc_table) + __alt_checkfunc_table_end = .; + } + + . = ALIGN(8); + .alternative : { + __alt_start = .; + *(.alternative) + __alt_end = .; + } __init_end = .; /* Start of data section */ From patchwork Mon Mar 8 03:58:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Chen X-Patchwork-Id: 12121385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DEF9C433E6 for ; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id v3sm8394307pff.217.2021.03.07.19.58.37 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Mar 2021 19:58:38 -0800 (PST) From: Vincent Chen To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: Frank.Zhao@starfivetech.com, atish.patra@wdc.com, anup.patel@wdc.com, guoren@kernel.org, alankao@andestech.com, paul.walmsley@sifive.com, Vincent Chen Subject: [RFC patch 4/4] riscv: sifive: apply errata "cip-453" patch Date: Mon, 8 Mar 2021 11:58:17 +0800 Message-Id: <1615175897-23509-5-git-send-email-vincent.chen@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1615175897-23509-1-git-send-email-vincent.chen@sifive.com> References: <1615175897-23509-1-git-send-email-vincent.chen@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_035847_170605_636F5CF6 X-CRM114-Status: GOOD ( 23.93 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add sign extension to the $badaddr before addressing the instruction page fault and instruction access fault to workaround the issue "cip-453". To avoid affecting the existing code sequence, this patch will creates two trampolines to add sign extension to the $badaddr. By the "alternative" mechanism, these two trampolines will replace the original exception handler of instruction page fault and instruction access fault in the excp_vect_table. In this case, only the specific SiFive CPU core jumps to the do_page_fault and do_trap_insn_fault through these two trampolines. Other CPUs are not affected. Signed-off-by: Vincent Chen --- arch/riscv/Kconfig.erratas | 20 +++++++++++ arch/riscv/Kconfig.socs | 1 + arch/riscv/errata/Makefile | 1 + arch/riscv/errata/sifive/Makefile | 2 ++ arch/riscv/errata/sifive/errata.c | 56 +++++++++++++++++++++++++++++++ arch/riscv/errata/sifive/errata_cip_453.S | 34 +++++++++++++++++++ arch/riscv/include/asm/errata_list.h | 3 +- arch/riscv/kernel/entry.S | 12 +++++-- 8 files changed, 126 insertions(+), 3 deletions(-) create mode 100644 arch/riscv/errata/sifive/Makefile create mode 100644 arch/riscv/errata/sifive/errata.c create mode 100644 arch/riscv/errata/sifive/errata_cip_453.S diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas index 4d0bafc536df..907fa6b13ee2 100644 --- a/arch/riscv/Kconfig.erratas +++ b/arch/riscv/Kconfig.erratas @@ -9,4 +9,24 @@ config RISCV_ERRATA_ALTERNATIVE code patching is performed once in the boot stages. It means that the overhead from this mechanism is just taken once. +config ERRATA_SIFIVE + bool "SiFive errata" + help + All SiFive errata Kconfig depend on this Kconfig. Please say "Y" + here if your platform uses SiFive CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + +config ERRATA_SIFIVE_CIP_453 + bool "Apply SiFive errata CIP-453" + depends on ERRATA_SIFIVE + depends on RISCV_ERRATA_ALTERNATIVE + default y + help + This will apply the SiFive CIP-453 errata to add sign extension + to the $badaddr when exception type is instruction page fault + and instruction access fault. + + If you don't know what to do here, say "Y". + endmenu diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 7efcece8896c..b9eda857fc87 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -7,6 +7,7 @@ config SOC_SIFIVE select CLK_SIFIVE select CLK_SIFIVE_PRCI select SIFIVE_PLIC + select ERRATA_SIFIVE help This enables support for SiFive SoC platform hardware. diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index 43e6d5424367..b8f8740a3e44 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -1 +1,2 @@ obj-y += alternative.o +obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ diff --git a/arch/riscv/errata/sifive/Makefile b/arch/riscv/errata/sifive/Makefile new file mode 100644 index 000000000000..b7f4cd7ee185 --- /dev/null +++ b/arch/riscv/errata/sifive/Makefile @@ -0,0 +1,2 @@ +obj-y += altern_ops.o +obj-y += errata_cip_453.o diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c new file mode 100644 index 000000000000..0b0a9af42a55 --- /dev/null +++ b/arch/riscv/errata/sifive/errata.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Sifive. + */ + +#include +#include +#include +#include +#include +#include + +#define MAX_ERRATA_IMPID 5 +struct errata_info_t { + char name[ERRATA_STRING_LENGTH_MAX]; + unsigned long arch_id; + unsigned long imp_id[MAX_ERRATA_IMPID]; +} errata_info; + +struct errata_info_t sifive_errata_list[ERRATA_NUMBER] = { + { + .name = "cip-453", + .arch_id = 0x8000000000000007, + .imp_id = { + 0x20181004, 0x00200504 + }, + }, +}; + +static inline bool __init cpu_info_cmp(struct errata_info_t *errata, struct alt_entry *alt) +{ + int i; + + if (errata->arch_id != cpu_mfr_info.arch_id) + return false; + + for (i = 0; i < MAX_ERRATA_IMPID && errata->imp_id[i]; i++) + if (errata->imp_id[i] == cpu_mfr_info.imp_id) + return true; + + return false; +} + +static bool __init sifive_errata_check(struct alt_entry *alt) +{ + if (cpu_mfr_info.vendor_id != alt->vendor_id) + return false; + + if (likely(alt->errata_id < ERRATA_NUMBER)) + return cpu_info_cmp(&sifive_errata_list[alt->errata_id], alt); + + WARN_ON(1); + return false; +} + +REGISTER_ERRATA_CHECKFUNC(sifive_errata_check, SIFIVE_VENDOR_ID); diff --git a/arch/riscv/errata/sifive/errata_cip_453.S b/arch/riscv/errata/sifive/errata_cip_453.S new file mode 100644 index 000000000000..34d0fe26172e --- /dev/null +++ b/arch/riscv/errata/sifive/errata_cip_453.S @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 SiFive + */ + +#include +#include +#include +#include + +.macro ADD_SIGN_EXT pt_reg badaddr tmp_reg + REG_L \badaddr, PT_BADADDR(\pt_reg) + li \tmp_reg,1 + slli \tmp_reg,\tmp_reg,0x26 + and \tmp_reg,\tmp_reg,\badaddr + beqz \tmp_reg, 1f + li \tmp_reg,-1 + slli \tmp_reg,\tmp_reg,0x27 + or \badaddr,\tmp_reg,\badaddr + REG_S \badaddr, PT_BADADDR(\pt_reg) +1: +.endm + +ENTRY(do_page_fault_trampoline) + ADD_SIGN_EXT a0, t0, t1 + la t0, do_page_fault + jr t0 +END(do_page_fault_trampoline) + +ENTRY(do_trap_insn_fault_trampoline) + ADD_SIGN_EXT a0, t0, t1 + la t0, do_trap_insn_fault + jr t0 +END(do_trap_insn_fault_trampoline) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 5e5a1fcd90ba..d3752c8eff1f 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -4,5 +4,6 @@ */ #ifdef CONFIG_SOC_SIFIVE -#define ERRATA_NUMBER 0 +#define ERRATA_CIP_453 0 +#define ERRATA_NUMBER 1 #endif diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 744f3209c48d..821e86ee67e4 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -12,6 +12,9 @@ #include #include #include +#include +#include +#include #if !IS_ENABLED(CONFIG_PREEMPTION) .set resume_kernel, restore_all @@ -450,7 +453,9 @@ ENDPROC(__switch_to) /* Exception vector table */ ENTRY(excp_vect_table) RISCV_PTR do_trap_insn_misaligned - RISCV_PTR do_trap_insn_fault + ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), + __stringify(RISCV_PTR do_trap_insn_fault_trampoline), + SIFIVE_VENDOR_ID, ERRATA_CIP_453, CONFIG_ERRATA_SIFIVE_CIP_453) RISCV_PTR do_trap_insn_illegal RISCV_PTR do_trap_break RISCV_PTR do_trap_load_misaligned @@ -461,7 +466,10 @@ ENTRY(excp_vect_table) RISCV_PTR do_trap_ecall_s RISCV_PTR do_trap_unknown RISCV_PTR do_trap_ecall_m - RISCV_PTR do_page_fault /* instruction page fault */ + /* instruciton page fault */ + ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), + __stringify(RISCV_PTR do_page_fault_trampoline), + SIFIVE_VENDOR_ID, ERRATA_CIP_453, CONFIG_ERRATA_SIFIVE_CIP_453) RISCV_PTR do_page_fault /* load page fault */ RISCV_PTR do_trap_unknown RISCV_PTR do_page_fault /* store page fault */