From patchwork Mon Mar 8 12:20:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12122087 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0B07C433E6 for ; Mon, 8 Mar 2021 12:21:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B48A651D1 for ; Mon, 8 Mar 2021 12:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230327AbhCHMUv (ORCPT ); Mon, 8 Mar 2021 07:20:51 -0500 Received: from mga09.intel.com ([134.134.136.24]:50394 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229972AbhCHMUl (ORCPT ); Mon, 8 Mar 2021 07:20:41 -0500 IronPort-SDR: 8HjKfgxdzP3Tr08fLF6Rl+vseFPkMiroFdozuYZidZ2t6Y3/A3C4UxeO03VjoxCstxvOZqMXHF UjGPjUOMHmSA== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="188123974" X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="188123974" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2021 04:20:41 -0800 IronPort-SDR: S46f8z3XISa1+fZmCo/UklecqlcJS3knmaT5YZJUn5sLqfhHdmQbHJsSW3dnoSBq7mynelwxRA RXjZUEQB/1pw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="376069664" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga007.fm.intel.com with ESMTP; 08 Mar 2021 04:20:37 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id ED38067; Mon, 8 Mar 2021 14:20:37 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Lee Jones , Andy Shevchenko , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jean Delvare , Peter Tyser , hdegoede@redhat.com, henning.schild@siemens.com Subject: [PATCH v1 1/7] PCI: Introduce pci_bus_*() printing macros when device is not available Date: Mon, 8 Mar 2021 14:20:14 +0200 Message-Id: <20210308122020.57071-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> References: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In some cases PCI device structure is not available and we want to print information based on the bus and devfn parameters. For this cases introduce pci_bus_*() printing macros and replace in existing users. Signed-off-by: Andy Shevchenko Reviewed-by: Jean Delvare --- drivers/pci/probe.c | 12 +++--------- include/linux/pci.h | 9 +++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 953f15abc850..7d67be52d8e5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2268,16 +2268,12 @@ static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, */ while (pci_bus_crs_vendor_id(*l)) { if (delay > timeout) { - pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", - pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); + pci_bus_warn(bus, devfn, "not ready after %dms; giving up\n", delay - 1); return false; } if (delay >= 1000) - pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", - pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); + pci_bus_info(bus, devfn, "not ready after %dms; waiting\n", delay - 1); msleep(delay); delay *= 2; @@ -2287,9 +2283,7 @@ static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, } if (delay >= 1000) - pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", - pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); + pci_bus_info(bus, devfn, "ready after %dms\n", delay - 1); return true; } diff --git a/include/linux/pci.h b/include/linux/pci.h index 86c799c97b77..c557d4a8476f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2463,4 +2463,13 @@ void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); WARN_ONCE(condition, "%s %s: " fmt, \ dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) +#define pci_bus_printk(level, bus, devfn, fmt, arg...) \ + printk(level "pci %04x:%02x:%02x.%d: " fmt, \ + pci_domain_nr(bus), bus->number, \ + PCI_SLOT(devfn), PCI_FUNC(devfn), ##arg) + +#define pci_bus_err(bus, devfn, fmt, arg...) pci_bus_printk(KERN_ERR, bus, devfn, fmt, ##arg) +#define pci_bus_warn(bus, devfn, fmt, arg...) pci_bus_printk(KERN_WARNING, bus, devfn, fmt, ##arg) +#define pci_bus_info(bus, devfn, fmt, arg...) pci_bus_printk(KERN_INFO, bus, devfn, fmt, ##arg) + #endif /* LINUX_PCI_H */ From patchwork Mon Mar 8 12:20:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12122085 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE8AAC433E0 for ; Mon, 8 Mar 2021 12:21:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 57349651CC for ; Mon, 8 Mar 2021 12:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230416AbhCHMUv (ORCPT ); Mon, 8 Mar 2021 07:20:51 -0500 Received: from mga07.intel.com ([134.134.136.100]:3478 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230198AbhCHMUm (ORCPT ); Mon, 8 Mar 2021 07:20:42 -0500 IronPort-SDR: qFL0bywx0W5lHuV5IRJ/M1upYBRPOpAgZMsa05cCW9zshqI/lwbUPMdFMhns/uakh93CwPb1y9 RL5M57D3tOcg== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="252044291" X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="252044291" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2021 04:20:41 -0800 IronPort-SDR: qEYXtnubt1FHTC7Hp+Uhs8umBOyGmRTh1J+lpCtRg0qDE6fNk33L6Z47yR2ofbQB0GRgYvXp6W WXVMw6LNE1rQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="369401484" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga003.jf.intel.com with ESMTP; 08 Mar 2021 04:20:37 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 04DC01EC; Mon, 8 Mar 2021 14:20:37 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Lee Jones , Andy Shevchenko , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jean Delvare , Peter Tyser , hdegoede@redhat.com, henning.schild@siemens.com Subject: [PATCH v1 2/7] PCI: Convert __pci_read_base() to __pci_bus_read_base() Date: Mon, 8 Mar 2021 14:20:15 +0200 Message-Id: <20210308122020.57071-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> References: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some drivers would like to read PCI BAR of the devices which has been not or can't be enumerated. In particular such mechanism is required to read PCI BAR of hidden devices behind Primary to Sideband (P2SB) bridge. Refactor __pci_read_base() to provide __pci_bus_read_base() and represent the former one as static inline helper. Signed-off-by: Andy Shevchenko --- drivers/pci/pci.h | 13 ++++++++- drivers/pci/probe.c | 69 +++++++++++++++++++++++---------------------- 2 files changed, 48 insertions(+), 34 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index ef7c4661314f..58a0e9f7a530 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -258,8 +258,19 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); int pci_setup_device(struct pci_dev *dev); + +int __pci_bus_read_base(struct pci_bus *bus, unsigned int devfn, + enum pci_bar_type type, + struct resource *res, unsigned int reg, + bool mmio_always_on); +static inline int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, - struct resource *res, unsigned int reg); + struct resource *res, unsigned int reg) +{ + res->name = pci_name(dev); + return __pci_bus_read_base(dev->bus, dev->devfn, type, res, reg, dev->mmio_always_on); +} + void pci_configure_ari(struct pci_dev *dev); void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 7d67be52d8e5..8cf139724a42 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -129,7 +129,7 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask) return size; } -static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) +static inline unsigned long decode_bar(u32 bar) { u32 mem_type; unsigned long flags; @@ -165,16 +165,21 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) /** - * __pci_read_base - Read a PCI BAR - * @dev: the PCI device + * __pci_bus_read_base - Read a PCI BAR + * @bus: the PCI bus + * @devfn: the PCI device and function * @type: type of the BAR * @res: resource buffer to be filled in * @pos: BAR position in the config space + * @mmio_always_on: disallow turning off IO/MEM decoding during BAR sizing * * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. + * In case of error resulting @res->flags is 0. */ -int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, - struct resource *res, unsigned int pos) +int __pci_bus_read_base(struct pci_bus *bus, unsigned int devfn, + enum pci_bar_type type, + struct resource *res, unsigned int pos, + bool mmio_always_on) { u32 l = 0, sz = 0, mask; u64 l64, sz64, mask64; @@ -184,20 +189,18 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, mask = type ? PCI_ROM_ADDRESS_MASK : ~0; /* No printks while decoding is disabled! */ - if (!dev->mmio_always_on) { - pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); + if (!mmio_always_on) { + pci_bus_read_config_word(bus, devfn, PCI_COMMAND, &orig_cmd); if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { - pci_write_config_word(dev, PCI_COMMAND, + pci_bus_write_config_word(bus, devfn, PCI_COMMAND, orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); } } - res->name = pci_name(dev); - - pci_read_config_dword(dev, pos, &l); - pci_write_config_dword(dev, pos, l | mask); - pci_read_config_dword(dev, pos, &sz); - pci_write_config_dword(dev, pos, l); + pci_bus_read_config_dword(bus, devfn, pos, &l); + pci_bus_write_config_dword(bus, devfn, pos, l | mask); + pci_bus_read_config_dword(bus, devfn, pos, &sz); + pci_bus_write_config_dword(bus, devfn, pos, l); /* * All bits set in sz means the device isn't working properly. @@ -216,7 +219,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, l = 0; if (type == pci_bar_unknown) { - res->flags = decode_bar(dev, l); + res->flags = decode_bar(l); res->flags |= IORESOURCE_SIZEALIGN; if (res->flags & IORESOURCE_IO) { l64 = l & PCI_BASE_ADDRESS_IO_MASK; @@ -236,26 +239,25 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, } if (res->flags & IORESOURCE_MEM_64) { - pci_read_config_dword(dev, pos + 4, &l); - pci_write_config_dword(dev, pos + 4, ~0); - pci_read_config_dword(dev, pos + 4, &sz); - pci_write_config_dword(dev, pos + 4, l); + pci_bus_read_config_dword(bus, devfn, pos + 4, &l); + pci_bus_write_config_dword(bus, devfn, pos + 4, ~0); + pci_bus_read_config_dword(bus, devfn, pos + 4, &sz); + pci_bus_write_config_dword(bus, devfn, pos + 4, l); l64 |= ((u64)l << 32); sz64 |= ((u64)sz << 32); mask64 |= ((u64)~0 << 32); } - if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) - pci_write_config_word(dev, PCI_COMMAND, orig_cmd); + if (!mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) + pci_bus_write_config_word(bus, devfn, PCI_COMMAND, orig_cmd); if (!sz64) goto fail; sz64 = pci_size(l64, sz64, mask64); if (!sz64) { - pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", - pos); + pci_bus_info(bus, devfn, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", pos); goto fail; } @@ -265,8 +267,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; res->start = 0; res->end = 0; - pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", - pos, (unsigned long long)sz64); + pci_bus_err(bus, devfn, + "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", + pos, (unsigned long long)sz64); goto out; } @@ -275,8 +278,9 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags |= IORESOURCE_UNSET; res->start = 0; res->end = sz64 - 1; - pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", - pos, (unsigned long long)l64); + pci_bus_info(bus, devfn, + "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", + pos, (unsigned long long)l64); goto out; } } @@ -284,8 +288,8 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, region.start = l64; region.end = l64 + sz64 - 1; - pcibios_bus_to_resource(dev->bus, res, ®ion); - pcibios_resource_to_bus(dev->bus, &inverted_region, res); + pcibios_bus_to_resource(bus, res, ®ion); + pcibios_resource_to_bus(bus, &inverted_region, res); /* * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is @@ -302,18 +306,17 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags |= IORESOURCE_UNSET; res->start = 0; res->end = region.end - region.start; - pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", - pos, (unsigned long long)region.start); + pci_bus_info(bus, devfn, "reg 0x%x: initial BAR value %#010llx invalid\n", + pos, (unsigned long long)region.start); } goto out; - fail: res->flags = 0; out: if (res->flags) - pci_info(dev, "reg 0x%x: %pR\n", pos, res); + pci_bus_info(bus, devfn, "reg 0x%x: %pR\n", pos, res); return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; } From patchwork Mon Mar 8 12:20:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12122089 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DF96C4332E for ; Mon, 8 Mar 2021 12:21:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E133651C9 for ; Mon, 8 Mar 2021 12:21:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229972AbhCHMUw (ORCPT ); Mon, 8 Mar 2021 07:20:52 -0500 Received: from mga07.intel.com ([134.134.136.100]:3478 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230169AbhCHMUm (ORCPT ); Mon, 8 Mar 2021 07:20:42 -0500 IronPort-SDR: Qef8E12BSHAwArql24qevcPZ5OU8KhgJ01nVnY1Y3/0SC3IgYWJOMSnkSvPfJ/1YHlAKC5MxCP jtudN8iOZbTA== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="252044285" X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="252044285" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2021 04:20:41 -0800 IronPort-SDR: 2q3WNouO93QO5ykGzfaw+a9Vr4WuKb3dTbqIHNKitQOgq+WsN9clIO/C3nSrxGwM3eaL2KRaye uf82+az6QKpw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="369401482" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga003.jf.intel.com with ESMTP; 08 Mar 2021 04:20:37 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 11573263; Mon, 8 Mar 2021 14:20:38 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Lee Jones , Andy Shevchenko , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jean Delvare , Peter Tyser , hdegoede@redhat.com, henning.schild@siemens.com Subject: [PATCH v1 3/7] PCI: New Primary to Sideband (P2SB) bridge support library Date: Mon, 8 Mar 2021 14:20:16 +0200 Message-Id: <20210308122020.57071-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> References: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jonathan Yong There is already one and at least one more user is coming which requires an access to Primary to Sideband bridge (P2SB) in order to get IO or MMIO bar hidden by BIOS. Create a library to access P2SB for x86 devices. Signed-off-by: Jonathan Yong Co-developed-by: Andy Shevchenko Signed-off-by: Andy Shevchenko --- drivers/pci/Kconfig | 8 ++++ drivers/pci/Makefile | 1 + drivers/pci/pci-p2sb.c | 83 ++++++++++++++++++++++++++++++++++++++++ include/linux/pci-p2sb.h | 28 ++++++++++++++ 4 files changed, 120 insertions(+) create mode 100644 drivers/pci/pci-p2sb.c create mode 100644 include/linux/pci-p2sb.h diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 0c473d75e625..740e5b30d6fd 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -252,6 +252,14 @@ config PCIE_BUS_PEER2PEER endchoice +config PCI_P2SB + bool "Primary to Sideband (P2SB) bridge access support" + depends on PCI && X86 + help + The Primary to Sideband bridge is an interface to some PCI + devices connected through it. In particular, SPI NOR + controller in Intel Apollo Lake SoC is one of such devices. + source "drivers/pci/hotplug/Kconfig" source "drivers/pci/controller/Kconfig" source "drivers/pci/endpoint/Kconfig" diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index d62c4ac4ae1b..eee8d5dda7d9 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PCI_IOV) += iov.o obj-$(CONFIG_PCI_BRIDGE_EMUL) += pci-bridge-emul.o obj-$(CONFIG_PCI_LABEL) += pci-label.o obj-$(CONFIG_X86_INTEL_MID) += pci-mid.o +obj-$(CONFIG_PCI_P2SB) += pci-p2sb.o obj-$(CONFIG_PCI_SYSCALL) += syscall.o obj-$(CONFIG_PCI_STUB) += pci-stub.o obj-$(CONFIG_PCI_PF_STUB) += pci-pf-stub.o diff --git a/drivers/pci/pci-p2sb.c b/drivers/pci/pci-p2sb.c new file mode 100644 index 000000000000..68d7dad48cdb --- /dev/null +++ b/drivers/pci/pci-p2sb.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Primary to Sideband bridge (P2SB) access support + * + * Copyright (c) 2017, 2021 Intel Corporation. + * + * Authors: Andy Shevchenko + * Jonathan Yong + */ + +#include +#include +#include + +#include +#include + +#include "pci.h" + +#define P2SBC_HIDE_BYTE 0xe1 +#define P2SBC_HIDE_BIT BIT(0) + +static const struct x86_cpu_id p2sb_cpu_ids[] = { + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, PCI_DEVFN(13, 0)), + {} +}; + +static int pci_p2sb_devfn(unsigned int *devfn) +{ + const struct x86_cpu_id *id; + + id = x86_match_cpu(p2sb_cpu_ids); + if (!id) + return -ENODEV; + + *devfn = (unsigned int)id->driver_data; + return 0; +} + +/** + * pci_p2sb_bar - Get Primary to Sideband bridge (P2SB) device BAR + * @pdev: PCI device to get a PCI bus to communicate with + * @devfn: PCI slot and function to communicate with + * @mem: memory resource to be filled in + * + * The BIOS prevents the P2SB device from being enumerated by the PCI + * subsystem, so we need to unhide and hide it back to lookup the BAR. + * + * Caller must provide a valid pointer to @mem. + * + * Locking is handled by pci_rescan_remove_lock mutex. + * + * Return: + * 0 on success or appropriate errno value on error. + */ +int pci_p2sb_bar(struct pci_dev *pdev, unsigned int devfn, struct resource *mem) +{ + struct pci_bus *bus = pdev->bus; + unsigned int df; + int ret; + + /* Get devfn for P2SB device itself */ + ret = pci_p2sb_devfn(&df); + if (ret) + return ret; + + pci_lock_rescan_remove(); + + /* Unhide the P2SB device */ + pci_bus_write_config_byte(bus, df, P2SBC_HIDE_BYTE, 0); + + /* Read the first BAR of the device in question */ + __pci_bus_read_base(bus, devfn, pci_bar_unknown, mem, PCI_BASE_ADDRESS_0, true); + + /* Hide the P2SB device */ + pci_bus_write_config_byte(bus, df, P2SBC_HIDE_BYTE, P2SBC_HIDE_BIT); + + pci_unlock_rescan_remove(); + + pci_bus_info(bus, devfn, "BAR: %pR\n", mem); + return 0; +} +EXPORT_SYMBOL_GPL(pci_p2sb_bar); diff --git a/include/linux/pci-p2sb.h b/include/linux/pci-p2sb.h new file mode 100644 index 000000000000..15dd42737c84 --- /dev/null +++ b/include/linux/pci-p2sb.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Primary to Sideband bridge (P2SB) access support + */ + +#ifndef _PCI_P2SB_H +#define _PCI_P2SB_H + +#include + +struct pci_dev; +struct resource; + +#if IS_BUILTIN(CONFIG_PCI_P2SB) + +int pci_p2sb_bar(struct pci_dev *pdev, unsigned int devfn, struct resource *mem); + +#else /* CONFIG_PCI_P2SB is not set */ + +static inline +int pci_p2sb_bar(struct pci_dev *pdev, unsigned int devfn, struct resource *mem) +{ + return -ENODEV; +} + +#endif /* CONFIG_PCI_P2SB */ + +#endif /* _PCI_P2SB_H */ From patchwork Mon Mar 8 12:20:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12122091 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA6F7C43333 for ; Mon, 8 Mar 2021 12:21:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8C976651CF for ; Mon, 8 Mar 2021 12:21:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230480AbhCHMUw (ORCPT ); Mon, 8 Mar 2021 07:20:52 -0500 Received: from mga12.intel.com ([192.55.52.136]:52723 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230184AbhCHMUm (ORCPT ); Mon, 8 Mar 2021 07:20:42 -0500 IronPort-SDR: PZ5EcfDbbkwuNTBHD7gK4UCo2DL3cJK7ZWXRXrV/X7eUwgBdbjmS/ay3nGTG8OxLFIhp1zFzZG C5RrnkMceafA== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="167288037" X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="167288037" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2021 04:20:41 -0800 IronPort-SDR: fSv4514lS+BwTAYRGvBpsn5EFCTYomMuaTpSj1R21DCWGD1sXJ7lzEfdUIRNcnJcPhrvSMUVRR AMt/kuKR0zNQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="588032254" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga005.jf.intel.com with ESMTP; 08 Mar 2021 04:20:37 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 1E405490; Mon, 8 Mar 2021 14:20:38 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Lee Jones , Andy Shevchenko , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jean Delvare , Peter Tyser , hdegoede@redhat.com, henning.schild@siemens.com Subject: [PATCH v1 4/7] mfd: lpc_ich: Factor out lpc_ich_enable_spi_write() Date: Mon, 8 Mar 2021 14:20:17 +0200 Message-Id: <20210308122020.57071-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> References: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Factor out duplicate code to lpc_ich_enable_spi_write() helper function. Signed-off-by: Andy Shevchenko --- drivers/mfd/lpc_ich.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 3bbb29a7e7a5..3a19ed57260e 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -1083,12 +1083,21 @@ static int lpc_ich_init_wdt(struct pci_dev *dev) return ret; } +static void lpc_ich_test_spi_write(struct pci_dev *dev, unsigned int devfn, + struct intel_spi_boardinfo *info) +{ + u32 bcr; + + pci_bus_read_config_dword(dev->bus, devfn, BCR, &bcr); + info->writeable = !!(bcr & BCR_WPD); +} + static int lpc_ich_init_spi(struct pci_dev *dev) { struct lpc_ich_priv *priv = pci_get_drvdata(dev); struct resource *res = &intel_spi_res[0]; struct intel_spi_boardinfo *info; - u32 spi_base, rcba, bcr; + u32 spi_base, rcba; info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); if (!info) @@ -1112,8 +1121,7 @@ static int lpc_ich_init_spi(struct pci_dev *dev) res->start = spi_base + SPIBASE_LPT; res->end = res->start + SPIBASE_LPT_SZ - 1; - pci_read_config_dword(dev, BCR, &bcr); - info->writeable = !!(bcr & BCR_WPD); + lpc_ich_test_spi_write(dev, dev->devfn, info); } break; @@ -1134,8 +1142,7 @@ static int lpc_ich_init_spi(struct pci_dev *dev) res->start = spi_base & 0xfffffff0; res->end = res->start + SPIBASE_APL_SZ - 1; - pci_bus_read_config_dword(bus, spi, BCR, &bcr); - info->writeable = !!(bcr & BCR_WPD); + lpc_ich_test_spi_write(dev, spi, info); } pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1); From patchwork Mon Mar 8 12:20:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12122097 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16F99C433E0 for ; Mon, 8 Mar 2021 12:21:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CED39651DD for ; Mon, 8 Mar 2021 12:21:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231215AbhCHMUy (ORCPT ); Mon, 8 Mar 2021 07:20:54 -0500 Received: from mga07.intel.com ([134.134.136.100]:3493 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230242AbhCHMUs (ORCPT ); Mon, 8 Mar 2021 07:20:48 -0500 IronPort-SDR: zkUiqrQjEn+qsCEUJOSCwPBFYADH3AvbGWl90alNjaCWh9m67sIHP/PnhPKtq+fAoKxeEOgGqD 9gfzXoVSxu/Q== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="252044308" X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="252044308" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2021 04:20:46 -0800 IronPort-SDR: 7A2Xp3zdMiKu2m4t0oKO7pSq1WMAbOBCWTQ3WUNeykqhEmg3sYAOZ+wTPFd3uu1VlYSRbeNBri ZfnE2o8+QO4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="602124729" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga005.fm.intel.com with ESMTP; 08 Mar 2021 04:20:43 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 2B596565; Mon, 8 Mar 2021 14:20:38 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Lee Jones , Andy Shevchenko , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jean Delvare , Peter Tyser , hdegoede@redhat.com, henning.schild@siemens.com Subject: [PATCH v1 5/7] mfd: lpc_ich: Switch to generic pci_p2sb_bar() Date: Mon, 8 Mar 2021 14:20:18 +0200 Message-Id: <20210308122020.57071-6-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> References: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Instead of open coding pci_p2sb_bar() functionality we are going to use generic library for that. There one more user of it is coming. Besides cleaning up it fixes a potential issue if, by some reason, SPI bar is 64-bit. Signed-off-by: Andy Shevchenko --- drivers/mfd/Kconfig | 1 + drivers/mfd/lpc_ich.c | 20 ++++++-------------- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index a03de3f7a8ed..c16bec1852e5 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -553,6 +553,7 @@ config LPC_ICH tristate "Intel ICH LPC" depends on PCI select MFD_CORE + select PCI_P2SB if X86 help The LPC bridge function of the Intel ICH provides support for many functional units. This driver provides needed support for diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 3a19ed57260e..8e9bd6813287 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include #include @@ -69,8 +70,6 @@ #define BCR 0xdc #define BCR_WPD BIT(0) -#define SPIBASE_APL_SZ 4096 - #define GPIOBASE_ICH0 0x58 #define GPIOCTRL_ICH0 0x5C #define GPIOBASE_ICH6 0x48 @@ -1126,26 +1125,19 @@ static int lpc_ich_init_spi(struct pci_dev *dev) break; case INTEL_SPI_BXT: { - unsigned int p2sb = PCI_DEVFN(13, 0); unsigned int spi = PCI_DEVFN(13, 2); - struct pci_bus *bus = dev->bus; + int ret; /* * The P2SB is hidden by BIOS and we need to unhide it in * order to read BAR of the SPI flash device. Once that is * done we hide it again. */ - pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0); - pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0, - &spi_base); - if (spi_base != ~0) { - res->start = spi_base & 0xfffffff0; - res->end = res->start + SPIBASE_APL_SZ - 1; - - lpc_ich_test_spi_write(dev, spi, info); - } + ret = pci_p2sb_bar(dev, spi, res); + if (ret) + return ret; - pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1); + lpc_ich_test_spi_write(dev, spi, info); break; } From patchwork Mon Mar 8 12:20:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12122099 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7D99C4360C for ; Mon, 8 Mar 2021 12:21:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6628A65203 for ; Mon, 8 Mar 2021 12:21:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230525AbhCHMUx (ORCPT ); Mon, 8 Mar 2021 07:20:53 -0500 Received: from mga09.intel.com ([134.134.136.24]:50394 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229899AbhCHMUp (ORCPT ); Mon, 8 Mar 2021 07:20:45 -0500 IronPort-SDR: zIGAmOx867xjMHvY+EbgcAeNLZMsDSbrf32CxupRQpkIjuhZFvIBtwfHisgcn98GWy/mxL1xB0 mu9rla0PyU4w== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="188123992" X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="188123992" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2021 04:20:45 -0800 IronPort-SDR: k+ZwVv0GBZN4dfhCEeyImvenxb0htCvn0NC5N0Egd6QiQ1mhjPY2+kda1cAOaFkbmeWlPbS8I9 eHmuda2rPqHw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="376069693" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga007.fm.intel.com with ESMTP; 08 Mar 2021 04:20:41 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 381D356B; Mon, 8 Mar 2021 14:20:38 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Lee Jones , Andy Shevchenko , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jean Delvare , Peter Tyser , hdegoede@redhat.com, henning.schild@siemens.com Subject: [PATCH v1 6/7] mfd: lpc_ich: Add support for pinctrl in non-ACPI system Date: Mon, 8 Mar 2021 14:20:19 +0200 Message-Id: <20210308122020.57071-7-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> References: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Tan Jui Nee Add support for non-ACPI systems, such as system that uses Advanced Boot Loader (ABL) whereby a platform device has to be created in order to bind with pin control and GPIO. At the moment, Intel Apollo Lake In-Vehicle Infotainment (IVI) system requires a driver to hide and unhide P2SB to lookup P2SB BAR and pass the PCI BAR address to GPIO. Signed-off-by: Tan Jui Nee Signed-off-by: Andy Shevchenko --- drivers/mfd/lpc_ich.c | 100 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 99 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 8e9bd6813287..959247b6987a 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -8,7 +8,8 @@ * Configuration Registers. * * This driver is derived from lpc_sch. - + * + * Copyright (C) 2017, 2021 Intel Corporation * Copyright (c) 2011 Extreme Engineering Solution, Inc. * Author: Aaron Sierra * @@ -43,6 +44,7 @@ #include #include #include +#include #include #include #include @@ -140,6 +142,73 @@ static struct mfd_cell lpc_ich_gpio_cell = { .ignore_resource_conflicts = true, }; +/* Offset data for Apollo Lake GPIO controllers */ +#define APL_GPIO_SOUTHWEST_OFFSET 0xc00000 +#define APL_GPIO_SOUTHWEST_SIZE 0x654 +#define APL_GPIO_NORTHWEST_OFFSET 0xc40000 +#define APL_GPIO_NORTHWEST_SIZE 0x764 +#define APL_GPIO_NORTH_OFFSET 0xc50000 +#define APL_GPIO_NORTH_SIZE 0x76c +#define APL_GPIO_WEST_OFFSET 0xc70000 +#define APL_GPIO_WEST_SIZE 0x674 + +#define APL_GPIO_NR_DEVICES 4 +#define APL_GPIO_IRQ 14 + +static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = { + { + DEFINE_RES_MEM(APL_GPIO_NORTH_OFFSET, APL_GPIO_NORTH_SIZE), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, + { + DEFINE_RES_MEM(APL_GPIO_NORTHWEST_OFFSET, APL_GPIO_NORTHWEST_SIZE), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, + { + DEFINE_RES_MEM(APL_GPIO_WEST_OFFSET, APL_GPIO_WEST_SIZE), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, + { + DEFINE_RES_MEM(APL_GPIO_SOUTHWEST_OFFSET, APL_GPIO_SOUTHWEST_SIZE), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, +}; + +/* The order must be in sync with apl_pinctrl_soc_data */ +static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = { + { + /* North */ + .name = "apollolake-pinctrl", + .id = 0, + .num_resources = ARRAY_SIZE(apl_gpio_resources[0]), + .resources = apl_gpio_resources[0], + .ignore_resource_conflicts = true, + }, + { + /* NorthWest */ + .name = "apollolake-pinctrl", + .id = 1, + .num_resources = ARRAY_SIZE(apl_gpio_resources[1]), + .resources = apl_gpio_resources[1], + .ignore_resource_conflicts = true, + }, + { + /* West */ + .name = "apollolake-pinctrl", + .id = 2, + .num_resources = ARRAY_SIZE(apl_gpio_resources[2]), + .resources = apl_gpio_resources[2], + .ignore_resource_conflicts = true, + }, + { + /* SouthWest */ + .name = "apollolake-pinctrl", + .id = 3, + .num_resources = ARRAY_SIZE(apl_gpio_resources[3]), + .resources = apl_gpio_resources[3], + .ignore_resource_conflicts = true, + }, +}; static struct mfd_cell lpc_ich_spi_cell = { .name = "intel-spi", @@ -1082,6 +1151,29 @@ static int lpc_ich_init_wdt(struct pci_dev *dev) return ret; } +static int lpc_ich_init_pinctrl(struct pci_dev *dev) +{ + struct resource base; + unsigned int i; + int ret; + + ret = pci_p2sb_bar(dev, PCI_DEVFN(13, 0), &base); + if (ret) + return ret; + + for (i = 0; i < ARRAY_SIZE(apl_gpio_devices); i++) { + struct resource *mem = &apl_gpio_resources[i][0]; + + /* Fill MEM resource */ + mem->start += base.start; + mem->end += base.start; + mem->flags = base.flags; + } + + return mfd_add_devices(&dev->dev, 0, apl_gpio_devices, + ARRAY_SIZE(apl_gpio_devices), NULL, 0, NULL); +} + static void lpc_ich_test_spi_write(struct pci_dev *dev, unsigned int devfn, struct intel_spi_boardinfo *info) { @@ -1198,6 +1290,12 @@ static int lpc_ich_probe(struct pci_dev *dev, cell_added = true; } + if (priv->chipset == LPC_APL) { + ret = lpc_ich_init_pinctrl(dev); + if (!ret) + cell_added = true; + } + if (lpc_chipset_info[priv->chipset].spi_type) { ret = lpc_ich_init_spi(dev); if (!ret) From patchwork Mon Mar 8 12:20:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12122095 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84C00C43603 for ; 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d="scan'208";a="447120674" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga001.jf.intel.com with ESMTP; 08 Mar 2021 04:20:42 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 451C25BD; Mon, 8 Mar 2021 14:20:38 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Lee Jones , Andy Shevchenko , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jean Delvare , Peter Tyser , hdegoede@redhat.com, henning.schild@siemens.com Subject: [PATCH v1 7/7] i2c: i801: convert to use common P2SB accessor Date: Mon, 8 Mar 2021 14:20:20 +0200 Message-Id: <20210308122020.57071-8-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> References: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since we have a common P2SB accessor in tree we may use it instead of open coded variants. Replace custom code by pci_p2sb_bar() call. Signed-off-by: Andy Shevchenko --- drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-i801.c | 40 ++++++++--------------------------- drivers/pci/pci-p2sb.c | 6 ++++++ 3 files changed, 16 insertions(+), 31 deletions(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 05ebf7546e3f..ffd3007f888c 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -101,6 +101,7 @@ config I2C_HIX5HD2 config I2C_I801 tristate "Intel 82801 (ICH/PCH)" depends on PCI + select PCI_P2SB if X86 select CHECK_SIGNATURE if X86 && DMI select I2C_SMBUS help diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index 4acee6f9e5a3..23b43de9786a 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c @@ -90,6 +90,7 @@ #include #include #include +#include #include #include #include @@ -136,7 +137,6 @@ #define TCOBASE 0x050 #define TCOCTL 0x054 -#define SBREG_BAR 0x10 #define SBREG_SMBCTRL 0xc6000c #define SBREG_SMBCTRL_DNV 0xcf000c @@ -1524,52 +1524,30 @@ static const struct itco_wdt_platform_data spt_tco_platform_data = { .version = 4, }; -static DEFINE_SPINLOCK(p2sb_spinlock); - static struct platform_device * i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, struct resource *tco_res) { struct resource *res; unsigned int devfn; - u64 base64_addr; - u32 base_addr; - u8 hidden; + int ret; /* * We must access the NO_REBOOT bit over the Primary to Sideband - * bridge (P2SB). The BIOS prevents the P2SB device from being - * enumerated by the PCI subsystem, so we need to unhide/hide it - * to lookup the P2SB BAR. + * bridge (P2SB). */ - spin_lock(&p2sb_spinlock); devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); - /* Unhide the P2SB device, if it is hidden */ - pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); - if (hidden) - pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); - - pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); - base64_addr = base_addr & 0xfffffff0; - - pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); - base64_addr |= (u64)base_addr << 32; - - /* Hide the P2SB device, if it was hidden before */ - if (hidden) - pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); - spin_unlock(&p2sb_spinlock); - res = &tco_res[1]; + ret = pci_p2sb_bar(pci_dev, devfn, res); + if (ret) + return ERR_PTR(ret); + if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) - res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; + res->start += SBREG_SMBCTRL_DNV; else - res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; - - res->end = res->start + 3; - res->flags = IORESOURCE_MEM; + res->start += SBREG_SMBCTRL; return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, tco_res, 2, &spt_tco_platform_data, diff --git a/drivers/pci/pci-p2sb.c b/drivers/pci/pci-p2sb.c index 68d7dad48cdb..7f6bc7d4482a 100644 --- a/drivers/pci/pci-p2sb.c +++ b/drivers/pci/pci-p2sb.c @@ -22,6 +22,12 @@ static const struct x86_cpu_id p2sb_cpu_ids[] = { X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, PCI_DEVFN(13, 0)), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, PCI_DEVFN(31, 1)), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, PCI_DEVFN(31, 1)), + X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, PCI_DEVFN(31, 1)), + X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, PCI_DEVFN(31, 1)), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, PCI_DEVFN(31, 1)), + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, PCI_DEVFN(31, 1)), {} };