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Signed-off-by: Nadeem Athani --- .../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml index 293b8ec318bc..a1d56e0be419 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -27,6 +27,18 @@ properties: msi-parent: true + detect-quiet-min-delay: + description: + LTSSM Detect.Quiet state minimum delay. + 00 : 0us minimum wait time + 01 : 100us minimum wait time + 10 : 1000us minimum wait time + 11 : 2000us minimum wait time + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 + required: - reg - reg-names @@ -48,6 +60,7 @@ examples: linux,pci-domain = <0>; vendor-id = <0x17cd>; device-id = <0x0200>; + detect-quiet-min-delay = <0>; reg = <0x0 0xfb000000 0x0 0x01000000>, <0x0 0x41000000 0x0 0x00001000>; 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As per PCIe specification, all Receivers must meet the Z-RX-DC specification for 2.5 GT/s within 1000us of entering Detect.Quiet LTSSM substate. The LTSSM must stay in this substate until the ZRXDC specification for 2.5 GT/s is met. Signed-off-by: Nadeem Athani --- drivers/pci/controller/cadence/pcie-cadence-host.c | 22 ++++++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 10 ++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 73dcf8cf98fb..056161b3fe65 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -461,6 +461,20 @@ static int cdns_pcie_host_init(struct device *dev, return cdns_pcie_host_init_address_translation(rc); } +static void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie = &rc->pcie; + u32 delay = rc->detect_quiet_min_delay; + u32 ltssm_control_cap; + + ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); + ltssm_control_cap = ((ltssm_control_cap & + ~CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) | + CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay)); + + cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); +} + int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { struct device *dev = rc->pcie.dev; @@ -485,6 +499,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) rc->device_id = 0xffff; of_property_read_u32(np, "device-id", &rc->device_id); + rc->detect_quiet_min_delay = 0; + of_property_read_u32(np, "detect-quiet-min-delay", + &rc->detect_quiet_min_delay); + pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg"); if (IS_ERR(pcie->reg_base)) { dev_err(dev, "missing \"reg\"\n"); @@ -497,6 +515,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) return PTR_ERR(rc->cfg_base); rc->cfg_res = res; + /* Default Detect.Quiet state delay is 0 */ + if (rc->detect_quiet_min_delay) + cdns_pcie_detect_quiet_min_delay_set(rc); + ret = cdns_pcie_start_link(pcie); if (ret) { dev_err(dev, "Failed to start link\n"); diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 254d2570f8c9..f2d3cca2c707 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -189,6 +189,14 @@ /* AXI link down register */ #define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) +/* LTSSM Capabilities register */ +#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ + (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ + CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) + enum cdns_pcie_rp_bar { RP_BAR_UNDEFINED = -1, RP_BAR0, @@ -289,6 +297,7 @@ struct cdns_pcie { * single function at a time * @vendor_id: PCI vendor ID * @device_id: PCI device ID + * @detect_quiet_min_delay: LTSSM Detect Quite state min. delay * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or * available * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 @@ -299,6 +308,7 @@ struct cdns_pcie_rc { void __iomem *cfg_base; u32 vendor_id; u32 device_id; + u32 detect_quiet_min_delay; bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; bool quirk_retrain_flag; };