From patchwork Wed Mar 10 08:33:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 12127281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69947C43381 for ; Wed, 10 Mar 2021 08:36:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3FF7964FDE for ; Wed, 10 Mar 2021 08:36:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232413AbhCJIgM (ORCPT ); Wed, 10 Mar 2021 03:36:12 -0500 Received: from youngberry.canonical.com ([91.189.89.112]:41054 "EHLO youngberry.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230453AbhCJIgJ (ORCPT ); Wed, 10 Mar 2021 03:36:09 -0500 Received: from mail-wr1-f70.google.com ([209.85.221.70]) by youngberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1lJuK7-0003QB-W2 for netdev@vger.kernel.org; Wed, 10 Mar 2021 08:36:08 +0000 Received: by mail-wr1-f70.google.com with SMTP id y5so7656659wrp.2 for ; Wed, 10 Mar 2021 00:36:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7UxAFifTu8sU7gViKdQC961bKcjK3MvZFPTtwzp8Z94=; b=t0mJ0o0O0kKhpYlL6Gtg90NslDzV9PQ8WvIXWhLlQ/IahyNqoA7PaNExPzKrm8RfcC 6rglY6Ndl9aN8Nh1KfCLBsoKJiIXNK1hS0AhtMDimDeOXA8Iiu49Uv9y9Ijv37Innh8y mFChWPv9RLno6Y9LtoTUIz3hF+u3y2chz3qrRpjEGtb64DHTk/bqsPbFVHbGd9b8Xeue fygo9RkQgB34p1/Bxk1wEZMpibitZ9SO4TkxAXMxRA+EJ8zMlsLU7Xd1B8UPB5HcHAy0 7Hdyx3S18eAafDwQjHI117bRtQpiRR5+jT38ibLTSLuKJINkTLj2LwAppIspcx0G0abF 6l+w== X-Gm-Message-State: AOAM532K0n7LO1SHnQWmHeBcPUfyLz5VA+7LUVUHkoGMWA+LBpv1tLuh byg5AT7LbkJnlVrI1HNzjpdChKh4EiNZhL2sxYrXn0FbjeCuCzFxsoegbQdcAcRE58iVCva9J2f Sf52qZsfKxV7duUaIDitiTxqtWFaXk9I1DQ== X-Received: by 2002:a1c:7901:: with SMTP id l1mr2229040wme.114.1615365367740; Wed, 10 Mar 2021 00:36:07 -0800 (PST) X-Google-Smtp-Source: ABdhPJzre2rLibVvflzX2MrQlXqX4OZ1UrJ20LDyRBd9TPGnPB0yloUbIcy/A0jwyJm4iqYiEGZYgQ== X-Received: by 2002:a1c:7901:: with SMTP id l1mr2229010wme.114.1615365367542; Wed, 10 Mar 2021 00:36:07 -0800 (PST) Received: from localhost.localdomain (adsl-84-226-167-205.adslplus.ch. [84.226.167.205]) by smtp.gmail.com with ESMTPSA id m17sm28675495wrx.92.2021.03.10.00.36.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 00:36:07 -0800 (PST) From: Krzysztof Kozlowski List-Id: To: Catalin Marinas , Will Deacon , Dinh Nguyen , Rob Herring , Michael Turquette , Stephen Boyd , Moritz Fischer , Tom Rix , Lee Jones , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-fpga@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, arm@kernel.org, soc@kernel.org, Arnd Bergmann , Olof Johansson Cc: Krzysztof Kozlowski Subject: [RFC v2 1/5] clk: socfpga: allow building N5X clocks with ARCH_N5X Date: Wed, 10 Mar 2021 09:33:23 +0100 Message-Id: <20210310083327.480837-2-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210310083327.480837-1-krzysztof.kozlowski@canonical.com> References: <20210310083327.480837-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-State: RFC The Intel's eASIC N5X (ARCH_N5X) architecture shares a lot with Agilex (ARCH_AGILEX) so it uses the same socfpga_agilex.dtsi, with minor changes. Also the clock drivers are the same. However the clock drivers won't be build without ARCH_AGILEX. One could assume that ARCH_N5X simply depends on ARCH_AGILEX but this was not modeled in Kconfig. In current stage the ARCH_N5X is simply unbootable. Add a separate Kconfig entry for clocks used by both ARCH_N5X and ARCH_AGILEX so the necessary objects will be built if either of them is selected. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/socfpga/Kconfig | 6 ++++++ drivers/clk/socfpga/Makefile | 4 ++-- 4 files changed, 10 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/socfpga/Kconfig diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index a588d56502d4..1d1891b9cad2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -394,6 +394,7 @@ source "drivers/clk/renesas/Kconfig" source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/sifive/Kconfig" +source "drivers/clk/socfpga/Kconfig" source "drivers/clk/sprd/Kconfig" source "drivers/clk/sunxi/Kconfig" source "drivers/clk/sunxi-ng/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index b22ae4f81e0b..12e46b12e587 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -106,6 +106,7 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ obj-$(CONFIG_ARCH_AGILEX) += socfpga/ +obj-$(CONFIG_ARCH_N5X) += socfpga/ obj-$(CONFIG_ARCH_STRATIX10) += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-y += sprd/ diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig new file mode 100644 index 000000000000..cae6fd9fac64 --- /dev/null +++ b/drivers/clk/socfpga/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +config COMMON_CLK_AGILEX + bool + # Intel Agilex / N5X clock controller support + default y if ARCH_AGILEX || ARCH_N5X + depends on ARCH_AGILEX || ARCH_N5X diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index bf736f8d201a..e3614f758184 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -3,5 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o -obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o -obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o +obj-$(CONFIG_COMMON_CLK_AGILEX) += clk-agilex.o +obj-$(CONFIG_COMMON_CLK_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o From patchwork Wed Mar 10 08:33:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 12127289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E23E9C4332D for ; Wed, 10 Mar 2021 08:37:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B1E8864FFD for ; Wed, 10 Mar 2021 08:37:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232405AbhCJIgo (ORCPT ); Wed, 10 Mar 2021 03:36:44 -0500 Received: from youngberry.canonical.com ([91.189.89.112]:41095 "EHLO youngberry.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231897AbhCJIgM (ORCPT ); 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[84.226.167.205]) by smtp.gmail.com with ESMTPSA id m17sm28675495wrx.92.2021.03.10.00.36.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 00:36:08 -0800 (PST) From: Krzysztof Kozlowski List-Id: To: Catalin Marinas , Will Deacon , Dinh Nguyen , Rob Herring , Michael Turquette , Stephen Boyd , Moritz Fischer , Tom Rix , Lee Jones , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-fpga@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, arm@kernel.org, soc@kernel.org, Arnd Bergmann , Olof Johansson Cc: Krzysztof Kozlowski Subject: [RFC v2 2/5] clk: socfpga: build together Stratix 10, Agilex and N5X clock drivers Date: Wed, 10 Mar 2021 09:33:24 +0100 Message-Id: <20210310083327.480837-3-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210310083327.480837-1-krzysztof.kozlowski@canonical.com> References: <20210310083327.480837-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-State: RFC On a multiplatform kernel there is little benefit in splitting each clock driver per platform because space savings are minimal. Such split also complicates the code, especially after adding compile testing. Build all arm64 Intel SoCFPGA clocks together with one entry in Makefile. This also removed duplicated line in the Makefile (selecting common part of clocks per platform). Signed-off-by: Krzysztof Kozlowski --- drivers/clk/socfpga/Kconfig | 8 ++++---- drivers/clk/socfpga/Makefile | 7 +++---- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig index cae6fd9fac64..7d4772faf93d 100644 --- a/drivers/clk/socfpga/Kconfig +++ b/drivers/clk/socfpga/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -config COMMON_CLK_AGILEX +config COMMON_CLK_SOCFPGA64 bool - # Intel Agilex / N5X clock controller support - default y if ARCH_AGILEX || ARCH_N5X - depends on ARCH_AGILEX || ARCH_N5X + # Intel Stratix / Agilex / N5X clock controller support + default y if ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10 + depends on ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10 diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile index e3614f758184..0446240162cf 100644 --- a/drivers/clk/socfpga/Makefile +++ b/drivers/clk/socfpga/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o -obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o -obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o -obj-$(CONFIG_COMMON_CLK_AGILEX) += clk-agilex.o -obj-$(CONFIG_COMMON_CLK_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o +obj-$(CONFIG_COMMON_CLK_SOCFPGA64) += clk-s10.o \ + clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \ + clk-agilex.o From patchwork Wed Mar 10 08:38:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 12127291 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55382C433E6 for ; Wed, 10 Mar 2021 08:39:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 12CDC64FEF for ; Wed, 10 Mar 2021 08:39:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232366AbhCJIjZ (ORCPT ); Wed, 10 Mar 2021 03:39:25 -0500 Received: from youngberry.canonical.com ([91.189.89.112]:41185 "EHLO youngberry.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229643AbhCJIiw (ORCPT ); Wed, 10 Mar 2021 03:38:52 -0500 Received: from mail-wm1-f70.google.com ([209.85.128.70]) by youngberry.canonical.com with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.86_2) (envelope-from ) id 1lJuMl-0003hx-6D for netdev@vger.kernel.org; Wed, 10 Mar 2021 08:38:51 +0000 Received: by mail-wm1-f70.google.com with SMTP id m17so858455wml.3 for ; Wed, 10 Mar 2021 00:38:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sJ+sWBPv8WTfBNPzw5KlNRJFjLSGVwyyKfH3WBvU8l8=; b=Hh770yF0hSXmLngoZGTStYx4jid0JHuKKFFPaC6hffOlOlAg1y9SlMJOubKWLRxm8I hVLW7t3EbMFdssYsZNY9AeO93ui6wCPs9whEJLsKwgrJKxeK/O0JGr61yzmGV65GkNzg OX4Az4IPhdVYalVET4sX1gmMgdvvxLKDls49qvKhWL9QdORKlMpe6bmoCZLPnuIZbfri TcMDZuHH61I8TSAywT6onM5KWL7XyL2lKL7evKBuPcrxL3MECsBPR2t2R2rTjBH/aPnj ASxpNQ7CdBeNlEoi2PfmHcvoiTGj10FNTdWYuD0A5AmCaN5DW88KCy7EfZNp1FszOw/R Wrgw== X-Gm-Message-State: AOAM5320l4jyrxbs5b9fW/EdDCm1lXxPXSfRqcsgaOq4tzLOrA/nqqmB kB6nFeARv/FSBi9bK0zwYBUGe9ZpKs6ehh/zumBgN0ogw0nyxrwd5NKIA2VxXuJ1hJmQkUQ1lwK adfngo4KFa173RFgjOXQOKnshDQDjMNXNMQ== X-Received: by 2002:a05:600c:35cd:: with SMTP id r13mr2199367wmq.186.1615365530695; Wed, 10 Mar 2021 00:38:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJxffKMarXt3WZ+2PQHxVk57BSqlnROHSdAmLc0YNptS3mf1yMHQoutG4Gedc/GO/nV/7BS6Sw== X-Received: by 2002:a05:600c:35cd:: with SMTP id r13mr2199348wmq.186.1615365530484; Wed, 10 Mar 2021 00:38:50 -0800 (PST) Received: from localhost.localdomain (adsl-84-226-167-205.adslplus.ch. [84.226.167.205]) by smtp.gmail.com with ESMTPSA id u20sm32781061wru.6.2021.03.10.00.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 00:38:50 -0800 (PST) From: Krzysztof Kozlowski List-Id: To: Catalin Marinas , Will Deacon , Dinh Nguyen , Rob Herring , Michael Turquette , Stephen Boyd , Moritz Fischer , Tom Rix , Lee Jones , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-fpga@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, arm@kernel.org, soc@kernel.org, Arnd Bergmann , Olof Johansson Cc: Krzysztof Kozlowski Subject: [RFC v2 3/5] arm64: socfpga: rename ARCH_STRATIX10 to ARCH_SOCFPGA64 Date: Wed, 10 Mar 2021 09:38:37 +0100 Message-Id: <20210310083840.481615-1-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210310083327.480837-1-krzysztof.kozlowski@canonical.com> References: <20210310083327.480837-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Prepare for merging Stratix 10, Agilex and N5X into one arm64 architecture by first renaming the ARCH_STRATIX10 into ARCH_SOCFPGA64. The existing ARCH_SOCFPGA (in ARMv7) Kconfig symbol cannot be used because altera_edac driver builds differently between them (with ifdefs). Signed-off-by: Krzysztof Kozlowski Acked-by: Lee Jones --- arch/arm64/Kconfig.platforms | 7 ++++--- arch/arm64/boot/dts/altera/Makefile | 2 +- arch/arm64/configs/defconfig | 2 +- drivers/clk/Makefile | 2 +- drivers/clk/socfpga/Kconfig | 4 ++-- drivers/edac/Kconfig | 2 +- drivers/edac/altera_edac.c | 10 +++++----- drivers/firmware/Kconfig | 2 +- drivers/fpga/Kconfig | 2 +- drivers/mfd/Kconfig | 2 +- drivers/net/ethernet/stmicro/stmmac/Kconfig | 4 ++-- drivers/reset/Kconfig | 2 +- 12 files changed, 21 insertions(+), 20 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index cdfd5fed457f..78bba3633eab 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -254,10 +254,11 @@ config ARCH_SEATTLE help This enables support for AMD Seattle SOC Family -config ARCH_STRATIX10 - bool "Altera's Stratix 10 SoCFPGA Family" +config ARCH_SOCFPGA64 + bool "Intel's SoCFPGA ARMv8 Families" help - This enables support for Altera's Stratix 10 SoCFPGA Family. + This enables support for Intel's SoCFPGA ARMv8 families: + Stratix 10 (ex. Altera), Agilex and eASIC N5X. config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile index 10119c7ab437..b45b92f8b4ec 100644 --- a/arch/arm64/boot/dts/altera/Makefile +++ b/arch/arm64/boot/dts/altera/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb \ +dtb-$(CONFIG_ARCH_SOCFPGA64) += socfpga_stratix10_socdk.dtb \ socfpga_stratix10_socdk_nand.dtb diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d612f633b771..ee742900a150 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -50,7 +50,7 @@ CONFIG_ARCH_RENESAS=y CONFIG_ARCH_ROCKCHIP=y CONFIG_ARCH_S32=y CONFIG_ARCH_SEATTLE=y -CONFIG_ARCH_STRATIX10=y +CONFIG_ARCH_SOCFPGA64=y CONFIG_ARCH_SYNQUACER=y CONFIG_ARCH_TEGRA=y CONFIG_ARCH_SPRD=y diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 12e46b12e587..e34457539edf 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -107,7 +107,7 @@ obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ obj-$(CONFIG_ARCH_AGILEX) += socfpga/ obj-$(CONFIG_ARCH_N5X) += socfpga/ -obj-$(CONFIG_ARCH_STRATIX10) += socfpga/ +obj-$(CONFIG_ARCH_SOCFPGA64) += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_ARCH_STI) += st/ diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig index 7d4772faf93d..8cf3dfdba255 100644 --- a/drivers/clk/socfpga/Kconfig +++ b/drivers/clk/socfpga/Kconfig @@ -2,5 +2,5 @@ config COMMON_CLK_SOCFPGA64 bool # Intel Stratix / Agilex / N5X clock controller support - default y if ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10 - depends on ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10 + default y if ARCH_AGILEX || ARCH_N5X || ARCH_SOCFPGA64 + depends on ARCH_AGILEX || ARCH_N5X || ARCH_SOCFPGA64 diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 27d0c4cdc58d..97fa2056bd47 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -396,7 +396,7 @@ config EDAC_THUNDERX config EDAC_ALTERA bool "Altera SOCFPGA ECC" - depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10) + depends on EDAC=y && (ARCH_SOCFPGA || ARCH_SOCFPGA64) help Support for error detection and correction on the Altera SOCs. This is the global enable for the diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c index e91cf1147a4e..ba11219664ca 100644 --- a/drivers/edac/altera_edac.c +++ b/drivers/edac/altera_edac.c @@ -1502,7 +1502,7 @@ static int altr_portb_setup(struct altr_edac_device_dev *device) dci->dev_name = ecc_name; /* Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly */ -#ifdef CONFIG_ARCH_STRATIX10 +#ifdef CONFIG_ARCH_SOCFPGA64 altdev->sb_irq = irq_of_parse_and_map(np, 1); #else altdev->sb_irq = irq_of_parse_and_map(np, 2); @@ -1521,7 +1521,7 @@ static int altr_portb_setup(struct altr_edac_device_dev *device) goto err_release_group_1; } -#ifdef CONFIG_ARCH_STRATIX10 +#ifdef CONFIG_ARCH_SOCFPGA64 /* Use IRQ to determine SError origin instead of assigning IRQ */ rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq); if (rc) { @@ -1931,7 +1931,7 @@ static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, goto err_release_group1; } -#ifdef CONFIG_ARCH_STRATIX10 +#ifdef CONFIG_ARCH_SOCFPGA64 /* Use IRQ to determine SError origin instead of assigning IRQ */ rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq); if (rc) { @@ -2016,7 +2016,7 @@ static const struct irq_domain_ops a10_eccmgr_ic_ops = { /************** Stratix 10 EDAC Double Bit Error Handler ************/ #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m) -#ifdef CONFIG_ARCH_STRATIX10 +#ifdef CONFIG_ARCH_SOCFPGA64 /* panic routine issues reboot on non-zero panic_timeout */ extern int panic_timeout; @@ -2109,7 +2109,7 @@ static int altr_edac_a10_probe(struct platform_device *pdev) altr_edac_a10_irq_handler, edac); -#ifdef CONFIG_ARCH_STRATIX10 +#ifdef CONFIG_ARCH_SOCFPGA64 { int dberror, err_addr; diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 3f14dffb9669..59660798f05f 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -206,7 +206,7 @@ config FW_CFG_SYSFS_CMDLINE config INTEL_STRATIX10_SERVICE tristate "Intel Stratix10 Service Layer" - depends on (ARCH_STRATIX10 || ARCH_AGILEX) && HAVE_ARM_SMCCC + depends on (ARCH_SOCFPGA64 || ARCH_AGILEX) && HAVE_ARM_SMCCC default n help Intel Stratix10 service layer runs at privileged exception level, diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 5ff9438b7b46..7f7504d1c961 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -60,7 +60,7 @@ config FPGA_MGR_ZYNQ_FPGA config FPGA_MGR_STRATIX10_SOC tristate "Intel Stratix10 SoC FPGA Manager" - depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE) + depends on (ARCH_SOCFPGA64 && INTEL_STRATIX10_SERVICE) help FPGA manager driver support for the Intel Stratix10 SoC. diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index a03de3f7a8ed..8fbd10cc6944 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -32,7 +32,7 @@ config MFD_ALTERA_A10SR config MFD_ALTERA_SYSMGR bool "Altera SOCFPGA System Manager" - depends on (ARCH_SOCFPGA || ARCH_STRATIX10) && OF + depends on (ARCH_SOCFPGA || ARCH_SOCFPGA64) && OF select MFD_SYSCON help Select this to get System Manager support for all Altera branded diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index e675ba12fde2..ab6eb792fbdb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -140,8 +140,8 @@ config DWMAC_ROCKCHIP config DWMAC_SOCFPGA tristate "SOCFPGA dwmac support" - default (ARCH_SOCFPGA || ARCH_STRATIX10) - depends on OF && (ARCH_SOCFPGA || ARCH_STRATIX10 || COMPILE_TEST) + default (ARCH_SOCFPGA || ARCH_SOCFPGA64) + depends on OF && (ARCH_SOCFPGA || ARCH_SOCFPGA64 || COMPILE_TEST) select MFD_SYSCON help Support for ethernet controller on Altera SOCFPGA diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 4171c6f76385..fa7f1394697b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -183,7 +183,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_AGILEX || ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARC + default ARCH_AGILEX || ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_SOCFPGA64 || ARCH_SUNXI || ARC help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, From patchwork Wed Mar 10 08:38:38 2021 Content-Type: text/plain; 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[84.226.167.205]) by smtp.gmail.com with ESMTPSA id u20sm32781061wru.6.2021.03.10.00.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 00:38:51 -0800 (PST) From: Krzysztof Kozlowski List-Id: To: Catalin Marinas , Will Deacon , Dinh Nguyen , Rob Herring , Michael Turquette , Stephen Boyd , Moritz Fischer , Tom Rix , Lee Jones , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-fpga@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, arm@kernel.org, soc@kernel.org, Arnd Bergmann , Olof Johansson Cc: Krzysztof Kozlowski Subject: [RFC v2 4/5] arm64: intel: merge Agilex and N5X into ARCH_SOCFPGA64 Date: Wed, 10 Mar 2021 09:38:38 +0100 Message-Id: <20210310083840.481615-2-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210310083840.481615-1-krzysztof.kozlowski@canonical.com> References: <20210310083327.480837-1-krzysztof.kozlowski@canonical.com> <20210310083840.481615-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-State: RFC Agilex, N5X and Stratix 10 share all quite similar arm64 hard cores and SoC-part. Up to a point that N5X uses the same DTSI as Agilex. From the Linux kernel point of view these are flavors of the same architecture so there is no need for three top-level arm64 architectures. Simplify this by merging all three architectures into ARCH_SOCFPGA64. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/Kconfig.platforms | 10 ---------- arch/arm64/boot/dts/intel/Makefile | 6 +++--- arch/arm64/configs/defconfig | 1 - drivers/clk/socfpga/Kconfig | 4 ++-- drivers/firmware/Kconfig | 2 +- drivers/reset/Kconfig | 2 +- 6 files changed, 7 insertions(+), 18 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 78bba3633eab..754738029cc6 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -8,16 +8,6 @@ config ARCH_ACTIONS help This enables support for the Actions Semiconductor S900 SoC family. -config ARCH_AGILEX - bool "Intel's Agilex SoCFPGA Family" - help - This enables support for Intel's Agilex SoCFPGA Family. - -config ARCH_N5X - bool "Intel's eASIC N5X SoCFPGA Family" - help - This enables support for Intel's eASIC N5X SoCFPGA Family. - config ARCH_SUNXI bool "Allwinner sunxi 64-bit SoC Family" select ARCH_HAS_RESET_CONTROLLER diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 3a052540605b..bb340584785c 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \ - socfpga_agilex_socdk_nand.dtb +dtb-$(CONFIG_ARCH_SOCFPGA64) += socfpga_agilex_socdk.dtb \ + socfpga_agilex_socdk_nand.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb -dtb-$(CONFIG_ARCH_N5X) += socfpga_n5x_socdk.dtb +dtb-$(CONFIG_ARCH_SOCFPGA64) += socfpga_n5x_socdk.dtb diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index ee742900a150..4968d4b3d89d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -28,7 +28,6 @@ CONFIG_KALLSYMS_ALL=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y CONFIG_ARCH_ACTIONS=y -CONFIG_ARCH_AGILEX=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y CONFIG_ARCH_BCM2835=y diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig index 8cf3dfdba255..834797c68cb2 100644 --- a/drivers/clk/socfpga/Kconfig +++ b/drivers/clk/socfpga/Kconfig @@ -2,5 +2,5 @@ config COMMON_CLK_SOCFPGA64 bool # Intel Stratix / Agilex / N5X clock controller support - default y if ARCH_AGILEX || ARCH_N5X || ARCH_SOCFPGA64 - depends on ARCH_AGILEX || ARCH_N5X || ARCH_SOCFPGA64 + default y if ARCH_SOCFPGA64 + depends on ARCH_SOCFPGA64 diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 59660798f05f..f290fad41731 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -206,7 +206,7 @@ config FW_CFG_SYSFS_CMDLINE config INTEL_STRATIX10_SERVICE tristate "Intel Stratix10 Service Layer" - depends on (ARCH_SOCFPGA64 || ARCH_AGILEX) && HAVE_ARM_SMCCC + depends on ARCH_SOCFPGA64 && HAVE_ARM_SMCCC default n help Intel Stratix10 service layer runs at privileged exception level, diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index fa7f1394697b..796c9e3e5e81 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -183,7 +183,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_AGILEX || ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_SOCFPGA64 || ARCH_SUNXI || ARC + default ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_SOCFPGA64 || ARCH_SUNXI || ARC help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, From patchwork Wed Mar 10 08:38:39 2021 Content-Type: text/plain; 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[84.226.167.205]) by smtp.gmail.com with ESMTPSA id u20sm32781061wru.6.2021.03.10.00.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 00:38:51 -0800 (PST) From: Krzysztof Kozlowski List-Id: To: Catalin Marinas , Will Deacon , Dinh Nguyen , Rob Herring , Michael Turquette , Stephen Boyd , Moritz Fischer , Tom Rix , Lee Jones , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-edac@vger.kernel.org, linux-fpga@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, arm@kernel.org, soc@kernel.org, Arnd Bergmann , Olof Johansson Cc: Krzysztof Kozlowski Subject: [RFC v2 5/5] clk: socfpga: allow compile testing of Stratix 10 / Agilex clocks Date: Wed, 10 Mar 2021 09:38:39 +0100 Message-Id: <20210310083840.481615-3-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210310083840.481615-1-krzysztof.kozlowski@canonical.com> References: <20210310083327.480837-1-krzysztof.kozlowski@canonical.com> <20210310083840.481615-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-State: RFC The Stratix 10 / Agilex / N5X clocks do not use anything other than OF or COMMON_CLK so they should be compile testable on most of the platforms. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/Makefile | 5 +---- drivers/clk/socfpga/Kconfig | 17 ++++++++++++++--- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e34457539edf..9b582b3fca34 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -104,10 +104,7 @@ obj-y += renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ obj-$(CONFIG_CLK_SIFIVE) += sifive/ -obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ -obj-$(CONFIG_ARCH_AGILEX) += socfpga/ -obj-$(CONFIG_ARCH_N5X) += socfpga/ -obj-$(CONFIG_ARCH_SOCFPGA64) += socfpga/ +obj-y += socfpga/ obj-$(CONFIG_PLAT_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_ARCH_STI) += st/ diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig index 834797c68cb2..fb93b7cede27 100644 --- a/drivers/clk/socfpga/Kconfig +++ b/drivers/clk/socfpga/Kconfig @@ -1,6 +1,17 @@ # SPDX-License-Identifier: GPL-2.0 +config COMMON_CLK_SOCFPGA + bool "Intel SoCFPGA family clock support" if COMPILE_TEST && !ARCH_SOCFPGA && !ARCH_SOCFPGA64 + depends on ARCH_SOCFPGA || ARCH_SOCFPGA64 || COMPILE_TEST + default y if ARCH_SOCFPGA || ARCH_SOCFPGA64 + help + Support for the clock controllers present on Intel SoCFPGA and eASIC + devices like Stratix 10, Agilex and N5X eASIC. + +if COMMON_CLK_SOCFPGA + config COMMON_CLK_SOCFPGA64 - bool - # Intel Stratix / Agilex / N5X clock controller support + bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && !ARCH_SOCFPGA64 default y if ARCH_SOCFPGA64 - depends on ARCH_SOCFPGA64 + depends on ARCH_SOCFPGA64 || COMPILE_TEST + +endif # COMMON_CLK_SOCFPGA