From patchwork Wed Mar 10 21:14:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Lipnitskiy X-Patchwork-Id: 12129453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD73CC433DB for ; Wed, 10 Mar 2021 21:22:37 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63B7B64FEF for ; Wed, 10 Mar 2021 21:22:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 63B7B64FEF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=Z1Dzu89jNpf5epfr4hWUZ8Gsct1LvY8v6bjUq0c9irI=; b=iZoFzT5z+ijDAB0Qi1YacT2dYV hyobANRJcDMxJr8+YvzCqFJwTnY8wBJ9LUdZlGFOMK0Aei+Jiyo+MyPAAh5DBmWQE/zjZUiQhq9WC 4OiQnI6Wi0x3G8RQxd+OXWXj+FVOQLPMuVM70S3iap+7wfsiYsXgBu20liZfFhbePcVaMfuPfQCKS YCAbvZcXt4RbkN5QlhKIB5Asm0RkvRz8TD6ocRkhtWrYj6vVgl0vDmw2RgoOLfAg/MCwDCNhTrGSM kCzDMvU+XjvnIdQUkHfT1h7FFibXbFbqxpcNNkZ0T83FplupPr7eJAmnu8IgMJwuhh2+QU51WqgDI x3tyEkjg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lK6G7-007mEG-SD; Wed, 10 Mar 2021 21:20:48 +0000 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lK69z-007kRE-6n; Wed, 10 Mar 2021 21:14:34 +0000 Received: by mail-pj1-x102d.google.com with SMTP id f2-20020a17090a4a82b02900c67bf8dc69so7944663pjh.1; Wed, 10 Mar 2021 13:14:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4FsyvPll9hketVRRLkgN32e9nK5xbA0yUQ+/xWtjN5A=; b=sS6imgOph8gR00hEK59z03oQEPnKC5OOit9DuHc9a9zW2bnRVXnbj4Sw2fC032b0w1 Z40vFIAbd7Yg2JVUAlD0lsjjiKM5UyAS4EBh/3RAhonPZdbdzZcrXYiidJo2DkgJX2nL iiny/jjkthqyHfBbwuEkA44ykbHmGoMM97WzSzveom1U4u9koOGpnryhADOT/I6WTQ3u IH6mSU5vuAWSxYl6cCvbPWu2QDBsWEaMnM1KP2S0K5uk6gp0ZG/JBh1LXBnnibnqDEA2 6H7ZYyd/lbb+asSbJAIYAIMIALiWGYV8PnZXdwrX/iXVy5Khvx/t581cLa1Preoz7UaU M6+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4FsyvPll9hketVRRLkgN32e9nK5xbA0yUQ+/xWtjN5A=; b=D9Vh0P4VKvkSjpz91SJtmzuhowtK00eGI9ypdo4AQVoIdf65tgpNF07cBdW8pwz9w7 yppoLumY753pyLfDOVtfDOqu/JaqcGTd1GkvPGfQYUgG9nDI/y7cwEwxREu27JwUTu+Y JLMETulgiFyOFhN7kfSIrQbbwkzNfLYRXPFL4PwP7nmYdeljJn1hbgj55mudhg5+u6Rg yfsjPIZSeR09AkUhMteggLM+znpi4Qhl/2Yy7kOm7wO7gwlQYGbi2OvJWF+BNMByQ1FC JTdIYje5ibqBNB8zWYxxW4qBEx5UJQthwZW3gKQknvGUoX78egF7LmdnFCM2Mz7UzhTC dDNg== X-Gm-Message-State: AOAM530eaE4kM+9HxHIjJCcOTp7l64iH+EtTx7rtZ9LT6d34vjtQJVTU NA4EXRaZ1kri0I5j0r8H+X0= X-Google-Smtp-Source: ABdhPJw4sfCLQailZ4/acL2LUKzPF+3TwjE25+ZJKEaff5COFkOBbZnQseKx/45xHgF0zVbL/vIMLA== X-Received: by 2002:a17:90b:3890:: with SMTP id mu16mr5447946pjb.9.1615410865096; Wed, 10 Mar 2021 13:14:25 -0800 (PST) Received: from ilya-fury.lan ([2602:61:738f:1000::b87]) by smtp.gmail.com with ESMTPSA id 35sm412090pgr.14.2021.03.10.13.14.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 13:14:24 -0800 (PST) From: Ilya Lipnitskiy To: Sean Wang , Landen Chao , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Matthias Brugger , Philipp Zabel , Russell King , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Ilya Lipnitskiy Subject: [PATCH 1/3] net: dsa: mt7530: remove redundant clock enables Date: Wed, 10 Mar 2021 13:14:18 -0800 Message-Id: <20210310211420.649985-1-ilya.lipnitskiy@gmail.com> X-Mailer: git-send-email 2.30.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210310_211428_502687_EFF062D7 X-CRM114-Status: GOOD ( 11.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In RGMII mode, the REG_GSWCK_EN bit of CORE_TRGMII_GSW_CLK_CG gets set three times in a row. In TRGMII mode, two times. Simplify the code and only set it once for both modes. Signed-off-by: Ilya Lipnitskiy --- drivers/net/dsa/mt7530.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index f06f5fa2f898..e785f80f966b 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -461,12 +461,9 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) RG_GSWPLL_POSDIV_200M(2) | RG_GSWPLL_FBKDIV_200M(32)); - /* Enable MT7530 core clock */ - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); } /* Setup the MT7530 TRGMII Tx Clock */ - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); @@ -480,6 +477,8 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); + + /* Enable MT7530 core and TRGMII Tx clocks */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN | REG_TRGMIICK_EN); From patchwork Wed Mar 10 21:14:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Lipnitskiy X-Patchwork-Id: 12129455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F4A8C433E0 for ; Wed, 10 Mar 2021 21:23:37 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DF93D64FEF for ; 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Wed, 10 Mar 2021 13:14:26 -0800 (PST) From: Ilya Lipnitskiy To: Sean Wang , Landen Chao , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Matthias Brugger , Philipp Zabel , Russell King , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Ilya Lipnitskiy Subject: [PATCH 2/3] net: dsa: mt7530: use core_write wrapper Date: Wed, 10 Mar 2021 13:14:19 -0800 Message-Id: <20210310211420.649985-2-ilya.lipnitskiy@gmail.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210310211420.649985-1-ilya.lipnitskiy@gmail.com> References: <20210310211420.649985-1-ilya.lipnitskiy@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210310_211429_345444_B73309AA X-CRM114-Status: GOOD ( 11.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When disabling PLL, there is no need to call core_write_mmd_indirect directly, use the core_write wrapper instead like the rest of the code in the function does. This change helps with consistency and readability. Signed-off-by: Ilya Lipnitskiy --- drivers/net/dsa/mt7530.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index e785f80f966b..b106ea816778 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -445,10 +445,7 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) * provide our own core_write_mmd_indirect to complete this * function. */ - core_write_mmd_indirect(priv, - CORE_GSWPLL_GRP1, - MDIO_MMD_VEND2, - 0); + core_write(priv, CORE_GSWPLL_GRP1, 0); /* Set core clock into 500Mhz */ core_write(priv, CORE_GSWPLL_GRP2, From patchwork Wed Mar 10 21:14:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Lipnitskiy X-Patchwork-Id: 12129457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85046C433E0 for ; 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Wed, 10 Mar 2021 13:14:28 -0800 (PST) Received: from ilya-fury.lan ([2602:61:738f:1000::b87]) by smtp.gmail.com with ESMTPSA id 35sm412090pgr.14.2021.03.10.13.14.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 13:14:27 -0800 (PST) From: Ilya Lipnitskiy To: Sean Wang , Landen Chao , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Matthias Brugger , Philipp Zabel , Russell King , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Ilya Lipnitskiy Subject: [PATCH 3/3] net: dsa: mt7530: setup core clock even in TRGMII mode Date: Wed, 10 Mar 2021 13:14:20 -0800 Message-Id: <20210310211420.649985-3-ilya.lipnitskiy@gmail.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210310211420.649985-1-ilya.lipnitskiy@gmail.com> References: <20210310211420.649985-1-ilya.lipnitskiy@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210310_211430_709566_C6775B7A X-CRM114-Status: GOOD ( 14.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org 3f9ef7785a9c ("MIPS: ralink: manage low reset lines") made it so mt7530 actually resets the switch on platforms such as mt7621 (where bit 2 is the reset line for the switch). That exposed an issue where the switch would not function properly in TRGMII mode after a reset. Reconfigure core clock in TRGMII mode to fix the issue. Also, disable both core and TRGMII Tx clocks prior to reconfiguring. Previously, only the core clock was disabled, but not TRGMII Tx clock. Tested on Ubiquity ER-X (MT7621) with TRGMII mode enabled. Signed-off-by: Ilya Lipnitskiy Signed-off-by: tag. --- drivers/net/dsa/mt7530.c | 44 ++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index b106ea816778..7ef5e7c23e05 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -435,30 +435,30 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), TD_DM_DRVP(8) | TD_DM_DRVN(8)); - /* Setup core clock for MT7530 */ - if (!trgint) { - /* Disable MT7530 core clock */ - core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); - - /* Disable PLL, since phy_device has not yet been created - * provided for phy_[read,write]_mmd_indirect is called, we - * provide our own core_write_mmd_indirect to complete this - * function. - */ - core_write(priv, CORE_GSWPLL_GRP1, 0); - - /* Set core clock into 500Mhz */ - core_write(priv, CORE_GSWPLL_GRP2, - RG_GSWPLL_POSDIV_500M(1) | - RG_GSWPLL_FBKDIV_500M(25)); + /* Since phy_device has not yet been created and + * phy_[read,write]_mmd_indirect is not available, we provide our own + * core_write_mmd_indirect with core_{clear,write,set} wrappers to + * complete this function. + */ - /* Enable PLL */ - core_write(priv, CORE_GSWPLL_GRP1, - RG_GSWPLL_EN_PRE | - RG_GSWPLL_POSDIV_200M(2) | - RG_GSWPLL_FBKDIV_200M(32)); + /* Disable MT7530 core and TRGMII Tx clocks */ + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, + REG_GSWCK_EN | REG_TRGMIICK_EN); - } + /* Setup core clock for MT7530 */ + /* Disable PLL */ + core_write(priv, CORE_GSWPLL_GRP1, 0); + + /* Set core clock into 500Mhz */ + core_write(priv, CORE_GSWPLL_GRP2, + RG_GSWPLL_POSDIV_500M(1) | + RG_GSWPLL_FBKDIV_500M(25)); + + /* Enable PLL */ + core_write(priv, CORE_GSWPLL_GRP1, + RG_GSWPLL_EN_PRE | + RG_GSWPLL_POSDIV_200M(2) | + RG_GSWPLL_FBKDIV_200M(32)); /* Setup the MT7530 TRGMII Tx Clock */ core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));