From patchwork Fri Mar 12 08:07:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ilya Lipnitskiy X-Patchwork-Id: 12133909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68D88C433E0 for ; Fri, 12 Mar 2021 08:09:23 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DB9E264DF0 for ; Fri, 12 Mar 2021 08:09:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DB9E264DF0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=du4m2IiARv0iUcnULkkkBP4Cn1klqa3p4cSbxfVj1ec=; b=AjRZYs/KlK+B8BFovMmOBcCB8 hX46xe8rwhcyjNgDlOQ2xpAyU3idr47sI7AcvuuYuupnoRoP4WBS12+HFSSQ8Ecn/zbhJPQVAR1MO XAEzgisaCTuhqU96bOeTMMejJesX2b/l9yjqprJTT2vsTdZn2trxwXr92gpTi3UJGL7TxKqRpsjYD Kyu4oPyyU4WlnItliTaAGl0JYLJpfbAE6Jje7Ed5YOmPjkh3wCsITrxjLLkN0JdZSoyIMeaML7Uxp WTp1cjH9Pl1n5JRDZ0bl+tMFZMVlTTKknpc3HqAjv+lEqMNYA8BuaZxG34L04fL7ePQ3hKs6QTzEk MVA9kghNQ==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lKcpk-00AqvS-KU; Fri, 12 Mar 2021 08:07:44 +0000 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lKcpe-00AqsR-Gq; Fri, 12 Mar 2021 08:07:41 +0000 Received: by mail-pg1-x530.google.com with SMTP id 16so8932304pgo.13; Fri, 12 Mar 2021 00:07:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=te3KkZ/7y8l0N1gnz9fMIpGsfWHYXiKPURp+vcWCB8E=; b=FihTQ2zVIfHyWNyLkfgjwMHDyPxCwUHIqC185KqAZJEdBqYjqLCb1Q/l5CK+41xDCf AiNkLws86GhP4FP3Acc+xWa2+xXBenk6JZEsb9HbOcvdBcQgDSA8p3761b2pPRUhWgr+ nSLqprGw/+owuMqtBkPCiyjVGpguvMpen4mGlBbsGw4Yi/Crvuk+MzVCI00GfuWX1afu ddFffOoJ06oXlfWpzRaLscR00h9VQdXQX3fEO9OMwiUs/wn+0XOmsjkd8FaljK1lpRVw de2s8KqSdI1oMi52qdtFwwZRqieQZlojKTfkotKkvXutErd8kzYiMMrJqPic7grk6wkL z4Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=te3KkZ/7y8l0N1gnz9fMIpGsfWHYXiKPURp+vcWCB8E=; b=ksdZHBxBnpg52exD0AhndvA8IgtfBaS1uvxME4TMVr0kxLc+JLafeC7AY9W/w92nKY N02Ma++ATCwn4cKK3Ldz3Ly5y5O9kZywaM3IZO3UBwZZBo0pP4svErtYJuNs/nqPIbu3 mxy+/IaZLMwRO68ua50TFudGXjKzgyYlcfDRmVOsgeoOLWGE2iYJSskM7HzljIpzwNBI nxwhGMr7CI6GPmZ00/gRTF+o6AOY6x3/o6oPXCefixY6lSQglHFRCcKC7ZolqyDmwD2C v5x8yawqnrAi+6aem9Py0HhH14w1ZtEKIfOA2APzbOJcuaMIGqmdZmzjRH/3AdzdD2Fn 70DA== X-Gm-Message-State: AOAM530pfiTHBEKCWKi93nNNxZrKb+WkdmKnbaHA5AAswEhMrjyg6ygM VouFcuAiUVylDy+StgoFSJo= X-Google-Smtp-Source: ABdhPJyAJm82NZ7DHwzELUMbIN2BgR52bHmEYM8VjrfkOBKeQ1wmBxxKrehZJ/MjRIv0iXyZEAOymg== X-Received: by 2002:a63:3544:: with SMTP id c65mr10768213pga.284.1615536456233; Fri, 12 Mar 2021 00:07:36 -0800 (PST) Received: from z640-arch.lan ([2602:61:738f:1000::678]) by smtp.gmail.com with ESMTPSA id h5sm4459973pgv.87.2021.03.12.00.07.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Mar 2021 00:07:35 -0800 (PST) From: Ilya Lipnitskiy To: Sean Wang , Landen Chao , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Matthias Brugger , Philipp Zabel , Russell King , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, sander@svanheule.net, tsbogend@alpha.franken.de, john@phrozen.org Cc: Ilya Lipnitskiy Subject: [PATCH net, v2] net: dsa: mt7530: setup core clock even in TRGMII mode Date: Fri, 12 Mar 2021 00:07:03 -0800 Message-Id: <20210312080703.63281-1-ilya.lipnitskiy@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210311012108.7190-1-ilya.lipnitskiy@gmail.com> References: <20210311012108.7190-1-ilya.lipnitskiy@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210312_080738_716227_6F736BE5 X-CRM114-Status: GOOD ( 12.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A recent change to MIPS ralink reset logic made it so mt7530 actually resets the switch on platforms such as mt7621 (where bit 2 is the reset line for the switch). That exposed an issue where the switch would not function properly in TRGMII mode after a reset. Reconfigure core clock in TRGMII mode to fix the issue. Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled. Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines") Signed-off-by: Ilya Lipnitskiy Tested-by: René van Dorst --- drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index f06f5fa2f898..9871d7cff93a 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -436,34 +436,32 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) TD_DM_DRVP(8) | TD_DM_DRVN(8)); /* Setup core clock for MT7530 */ - if (!trgint) { - /* Disable MT7530 core clock */ - core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); - - /* Disable PLL, since phy_device has not yet been created - * provided for phy_[read,write]_mmd_indirect is called, we - * provide our own core_write_mmd_indirect to complete this - * function. - */ - core_write_mmd_indirect(priv, - CORE_GSWPLL_GRP1, - MDIO_MMD_VEND2, - 0); - - /* Set core clock into 500Mhz */ - core_write(priv, CORE_GSWPLL_GRP2, - RG_GSWPLL_POSDIV_500M(1) | - RG_GSWPLL_FBKDIV_500M(25)); + /* Disable MT7530 core clock */ + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); - /* Enable PLL */ - core_write(priv, CORE_GSWPLL_GRP1, - RG_GSWPLL_EN_PRE | - RG_GSWPLL_POSDIV_200M(2) | - RG_GSWPLL_FBKDIV_200M(32)); - - /* Enable MT7530 core clock */ - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); - } + /* Disable PLL, since phy_device has not yet been created + * provided for phy_[read,write]_mmd_indirect is called, we + * provide our own core_write_mmd_indirect to complete this + * function. + */ + core_write_mmd_indirect(priv, + CORE_GSWPLL_GRP1, + MDIO_MMD_VEND2, + 0); + + /* Set core clock into 500Mhz */ + core_write(priv, CORE_GSWPLL_GRP2, + RG_GSWPLL_POSDIV_500M(1) | + RG_GSWPLL_FBKDIV_500M(25)); + + /* Enable PLL */ + core_write(priv, CORE_GSWPLL_GRP1, + RG_GSWPLL_EN_PRE | + RG_GSWPLL_POSDIV_200M(2) | + RG_GSWPLL_FBKDIV_200M(32)); + + /* Enable MT7530 core clock */ + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); /* Setup the MT7530 TRGMII Tx Clock */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);