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Fri, 12 Mar 2021 13:48:39 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 12 Mar 2021 13:48:34 +0000 Received: from vdi.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 12 Mar 2021 13:48:37 +0000 From: Liming Sun To: Adrian Hunter , Ulf Hansson , Khalil Blaiech CC: Liming Sun , , Subject: [PATCH v1 1/1] mmc: sdhci-acpi: Add support for NVIDIA BlueField-3 SoC Date: Fri, 12 Mar 2021 08:48:25 -0500 Message-ID: X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4f13125f-939c-4dbc-6579-08d8e55d8b03 X-MS-TrafficTypeDiagnostic: BL1PR12MB5174: X-Microsoft-Antispam-PRVS: X-MS-Exchange-Transport-Forked: True X-MS-Oob-TLC-OOBClassifiers: OLM:254; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OCLF5HShpAuJvnVW+E21IRKXTkpFqySQe75xv/Nq+P1231MDJ+CgLV9VfvYXroBoc8CW886MjwLtGxHoqrceQrG+304PfX84TBoTZNCUTqX9XQU0X+YxpGqufZxtIRiJ33BK70+mzgk0B7uPnGYYgdhBB/6azhrnPYgHWSYX5yLVGqSn2Fey5/8+0cbQjFhv2TSxYSf8YB+NUBjjBYSourLUOyolvsIm8eP1Z6dIb/O+EUD/mlzMor1DB3/nbGR/q9IWjvMAMArP3n2XGy3PQefjB+xkRFJfO/O/KH3myMUpoGD3JUat0i5NM+GLcuSXVMJoCZkuSwuqfsMnhw6q3iGFh3kIQS5y6bRQEz+WjNM3H7xi3y3cuTcw2jdelZOZbpUQgF2zkPrTteG69gnQKE96GLyy1ZwaXjePgVIvkqYASDjcrU6xHLlB4/L+dCxGz0NNbo95qgLmXJcPkee5LsOo9fZJUgNLeSqkEYTeLJoRQyE8KiND77rzZ2XTQ35jrNiDmWzJyCEW6UDt/LwgKqoHzO9jGVFZVsiFykU7s6MIzXOvzsGfY6tRSgRvZQAdv37MSea2JNcF0VonGb2FCd/lzJDEjjNrWRWjbeafQ/s9hRosUUtDcXu8k4UU5WHlQDP2ro/k27BmW9N3gCDysAY9X6OURcbHQpfgUPur58oKvMXRQCmU9adSg1wcPri3 X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(136003)(396003)(376002)(346002)(39860400002)(46966006)(36840700001)(6636002)(70586007)(70206006)(316002)(54906003)(36906005)(478600001)(26005)(110136005)(8676002)(8936002)(36756003)(336012)(426003)(4326008)(86362001)(5660300002)(186003)(6666004)(2616005)(83380400001)(34020700004)(7696005)(82310400003)(2906002)(36860700001)(7636003)(356005)(82740400003)(47076005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2021 13:48:39.6471 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f13125f-939c-4dbc-6579-08d8e55d8b03 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5174 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This commit adds ACPI support for the BlueField-3 SoC which uses the DWC_mshc eMMC controller. The boundary check logic in static function dwcmshc_adma_write_desc() comes from sdhci-of-dwcmshc.c. Signed-off-by: Liming Sun Reviewed-by: Khalil Blaiech --- drivers/mmc/host/sdhci-acpi.c | 64 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c index 54205e3..6448e94e 100644 --- a/drivers/mmc/host/sdhci-acpi.c +++ b/drivers/mmc/host/sdhci-acpi.c @@ -716,6 +716,68 @@ static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev, .priv_size = sizeof(struct amd_sdhci_host), }; +/* Check DMA address/length boundary. */ +static inline bool dwcmshc_adma_boundary_ok(dma_addr_t addr, int len) +{ + return (addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)); +} + +/* + * If DMA addr spans 128MB boundary, we split the DMA transfer into two + * so that each DMA transfer doesn't exceed the boundary. + */ +static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, + dma_addr_t addr, int len, unsigned int cmd) +{ + int tmplen, offset; + + if (likely(!len || dwcmshc_adma_boundary_ok(addr, len))) { + sdhci_adma_write_desc(host, desc, addr, len, cmd); + return; + } + + offset = addr & (SZ_128M - 1); + tmplen = SZ_128M - offset; + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); + + addr += tmplen; + len -= tmplen; + sdhci_adma_write_desc(host, desc, addr, len, cmd); +} + +static int sdhci_acpi_emmc_nvda_bf_probe_slot(struct platform_device *pdev, + struct acpi_device *adev) +{ + struct sdhci_acpi_host *c = platform_get_drvdata(pdev); + struct sdhci_host *host = c->host; + u32 extra; + + /* Extra adma table cnt for cross 128M boundary handling. */ + extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M); + extra = min(extra, (u32)SDHCI_MAX_SEGS); + host->adma_table_cnt += extra; + + return 0; +} + +static const struct sdhci_ops sdhci_acpi_ops_nvda_bf = { + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = sdhci_set_uhs_signaling, + .reset = sdhci_reset, + .adma_write_desc = dwcmshc_adma_write_desc, +}; + +static const struct sdhci_acpi_chip sdhci_acpi_chip_nvda_bf = { + .ops = &sdhci_acpi_ops_nvda_bf, +}; + +static const struct sdhci_acpi_slot sdhci_acpi_slot_nvda_bf_emmc = { + .chip = &sdhci_acpi_chip_nvda_bf, + .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, + .probe_slot = sdhci_acpi_emmc_nvda_bf_probe_slot, +}; + struct sdhci_acpi_uid_slot { const char *hid; const char *uid; @@ -740,6 +802,7 @@ struct sdhci_acpi_uid_slot { { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v }, { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd }, { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc }, + { "MLNXBF30", NULL, &sdhci_acpi_slot_nvda_bf_emmc }, { }, }; @@ -757,6 +820,7 @@ struct sdhci_acpi_uid_slot { { "QCOM8051" }, { "QCOM8052" }, { "AMDI0040" }, + { "MLNXBF30" }, { }, }; MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);