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Fri, 19 Mar 2021 10:08:17 +0000 From: quanyang.wang@windriver.com To: Michael Turquette , Stephen Boyd , Michal Simek Cc: Rajan Vaja , Jolly Shah , Greg Kroah-Hartman , Laurent Pinchart , Quanyang Wang , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable Date: Fri, 19 Mar 2021 18:07:17 +0800 Message-Id: <20210319100717.507500-1-quanyang.wang@windriver.com> X-Mailer: git-send-email 2.25.1 X-Originating-IP: [60.247.85.82] X-ClientProxiedBy: HKAPR03CA0025.apcprd03.prod.outlook.com (2603:1096:203:c9::12) To CY4PR11MB0071.namprd11.prod.outlook.com (2603:10b6:910:7a::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from pek-qwang2-d1.wrs.com (60.247.85.82) by HKAPR03CA0025.apcprd03.prod.outlook.com (2603:1096:203:c9::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3977.9 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: MvE7xU/h2O0fI631dpqoiW4AsSVj+krJZa56+EpEqQ2yuu53lmrM9Z8HPCrK7RPw1q6kcy/OGkKc8A/iUdiLxZ9eiV+lk4PTBhNJLQTZqSwObEq6q4HvOtN3FscWoAjvhHXhwEPEE7EJtByJRbpViE8ikMYKZx03fcbyoekfsvRjCzHchm0RLizWGh1aMSRjdkwm5Oz1UlwRYx0c1V9WhFdsdsaIrBOE0NvwwJ12aWLjRnchdjB+OMxHhhvS1QBIDK1P6JDTnFau099KNevfVlAhJkhOogdKyTanA8jFDNhVlmfNHiIxFBUN4uBiF/J8ryhHMyS9BABx/k3pDejcNpocBWhOBM4XBjYD/RKfj9r1GECUpd/onbRk06jsLAaQClZ7eXa88m/j8bf9L9kJBpdIuKbpUngrNr1m0rd/21TA/BUxUZNB5BiNp9fJcmbDl6NQX0UnmqqOVCseYKR0EPkk7kV1lb86Va97pqCQ76B3CrHIGMHClKIgXFXgmIetie/fyey9yU8NrfJs4YbyleyrMLqgO0iTNKM3CBd4cW6l1puJ1wyjyVCrGr1c+oSXyhRVtklbRDTGAskhAaMalgN8sgH3VgL3pRaYmOQO5N+Cn04o2TG4wFBpfKHKni/sHQKmI31ZXKzHYB8c4wGDKBSPQpGUIVxWB20eZtvID6gGfeIvvadbxG91hq9eARgBnJcfoNqNw13vC+fAMuRZiTelNoc/05h4UHzMWm0aqcAiwXhsgikc695jV9Y6YOag8HXpH4EIHxb5dPjAx/b8IBRUGdkMyd7wnragzQ+CmGZmtl6NnnKFOnr+6cQRHhty1j8voKIcKkoOvGSDTCVJfPkj5PbVVofofbZlGucH63KfZZFzSDeQwRLyCtHuBBBdkX8jqHItBfQJO+DuXT3lmUjk5lEk52wFEZJHhmcR9P4qIfNJ4v3zZctLCqvy11y4fqpWAYx8znIRyjVu/Zj5VMFOMSlsRsIO2SiQAJ7T2Txqsj+WfQvHKMiAfuaI9CB+GokqIRgBTFPA9VLUqWYA2LBxFquAA2oy/cwDReaMkAcXRxmJWJFoAXDCvWokoOTrWNsoC/5CRwarZQdpioHBPU4VgnQQgMBAui8mPATeG8T3JS5EYkm9iupuNfWe55RlkLtyWl39NRVnU2WK48dkz5ymsnQOgQV5HOcMvu9+SWuPqQ82tRRDvRz0FJT393Z3x3r4vcIvePub3CcDnZpksIOjTpJL2TCfe16SudEh0osTJ2/iuT0zDxQEvtVw19WKSWARH+0wGjRsmELqPULJJg+CfDuSYmQL17Sxz1MLby+/eXjofh1rgDoCnEaMcKXZ X-OriginatorOrg: windriver.com X-MS-Exchange-CrossTenant-Network-Message-Id: b449a92d-d76a-4040-39d9-08d8eabeeaa8 X-MS-Exchange-CrossTenant-AuthSource: CY4PR11MB0071.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2021 10:08:17.7032 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 8ddb2873-a1ad-4a18-ae4e-4644631433be X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FLgHuGDFa8n9cXtBYDs7FW1VIEn5KBLGef5Ce+nyD+JVGYksC6pzywKTb0+G/NCgmKm13C8p6vD2WgUNJ5I7iQI8Zm3ht6hOH8zpBuUCv6Y= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR11MB0072 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Quanyang Wang If there is a IOCTL_SET_PLL_FRAC_MODE request sent to ATF ever, we shouldn't skip invoking PM_CLOCK_ENABLE fn even though this pll has been enabled. In ATF implementation, it will only assign the mode to the variable (struct pm_pll *)pll->mode when handling IOCTL_SET_PLL_FRAC_MODE call. Invoking PM_CLOCK_ENABLE can force ATF send request to PWU to set the pll mode to PLL's register. There is a scenario that happens in enabling VPLL_INT(clk_id:96): 1) VPLL_INT has been enabled during booting. 2) A driver calls clk_set_rate and according to the rate, the VPLL_INT should be set to FRAC mode. Then zynqmp_pll_set_mode is called to pass IOCTL_SET_PLL_FRAC_MODE to ATF. Note that at this point ATF just stores the mode to a variable. 3) This driver calls clk_prepare_enable and zynqmp_pll_enable is called to try to enable VPLL_INT pll. Because of 1), the function zynqmp_pll_enable just returns without doing anything after checking that this pll has been enabled. In the scenario above, the pll mode of VPLL_INT will never be set successfully. So adding set_pll_mode to chec condition to fix it. Signed-off-by: Quanyang Wang Tested-by: Laurent Pinchart --- drivers/clk/zynqmp/pll.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index 92f449ed38e5..f1e8f37d7f52 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -14,10 +14,12 @@ * struct zynqmp_pll - PLL clock * @hw: Handle between common and hardware-specific interfaces * @clk_id: PLL clock ID + * @set_pll_mode: Whether an IOCTL_SET_PLL_FRAC_MODE request be sent to ATF */ struct zynqmp_pll { struct clk_hw hw; u32 clk_id; + bool set_pll_mode; }; #define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw) @@ -81,6 +83,8 @@ static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on) if (ret) pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n", __func__, clk_name, ret); + else + clk->set_pll_mode = true; } /** @@ -240,9 +244,14 @@ static int zynqmp_pll_enable(struct clk_hw *hw) u32 clk_id = clk->clk_id; int ret; - if (zynqmp_pll_is_enabled(hw)) + /* Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request + * that has been sent to ATF. + */ + if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode)) return 0; + clk->set_pll_mode = false; + ret = zynqmp_pm_clock_enable(clk_id); if (ret) pr_warn_once("%s() clock enable failed for %s, ret = %d\n",