From patchwork Mon Mar 22 18:10:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12155747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29870C433DB for ; Mon, 22 Mar 2021 18:09:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE68B61878 for ; Mon, 22 Mar 2021 18:09:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CE68B61878 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A6956E151; Mon, 22 Mar 2021 18:09:01 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 700036E102 for ; Mon, 22 Mar 2021 18:08:59 +0000 (UTC) IronPort-SDR: muT+jeFkKUI55tGspsKV9ixcm9cStx8oVlsMJsPtkqy+0+O29Aj2MjVIVoHkVfjRwY8Eet0/oq itqh+ibddqPA== X-IronPort-AV: E=McAfee;i="6000,8403,9931"; a="169654090" X-IronPort-AV: E=Sophos;i="5.81,269,1610438400"; d="scan'208";a="169654090" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2021 11:08:58 -0700 IronPort-SDR: CMpvCpleHoMiY4k1l6cQy1hmLgYeMp/vAQhjENNRSgoi+ImkcQEw2Tbz7hQUEVBJd2HEUz95DK UIliOoPLcxwg== X-IronPort-AV: E=Sophos;i="5.81,269,1610438400"; d="scan'208";a="524538838" Received: from ryanmart-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.180.219]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2021 11:08:56 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Mar 2021 11:10:53 -0700 Message-Id: <20210322181055.207619-1-jose.souza@intel.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Warn when display irq functions are called without display X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With previous changes none of those warnings will be printed but let's add them so CI can caught regressions. Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_fifo_underrun.c | 2 ++ drivers/gpu/drm/i915/display/intel_hotplug.c | 2 ++ drivers/gpu/drm/i915/i915_irq.c | 17 +++++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index 813a4f7033e1..f3631e319e5d 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -373,6 +373,8 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, { struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + /* We may be called too early in init, thanks BIOS! */ if (crtc == NULL) return; diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index f46a1b7190b8..77ce4a54a137 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -478,6 +478,8 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, if (!pin_mask) return; + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + spin_lock(&dev_priv->irq_lock); /* diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 44aed4cbf894..cbb2aae4fc13 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -519,6 +519,8 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv, i915_reg_t reg = PIPESTAT(pipe); u32 enable_mask; + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, "pipe %c: status_mask=0x%x\n", pipe_name(pipe), status_mask); @@ -1273,6 +1275,7 @@ static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915, static void gmbus_irq_handler(struct drm_i915_private *dev_priv) { + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); wake_up_all(&dev_priv->gmbus_wait_queue); } @@ -1366,6 +1369,8 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, { u32 res1, res2; + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + if (INTEL_GEN(dev_priv) >= 3) res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe)); else @@ -1558,6 +1563,8 @@ static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) u32 hotplug_status = 0, hotplug_status_mask; int i; + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | @@ -1597,6 +1604,8 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 pin_mask = 0, long_mask = 0; u32 hotplug_trigger; + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; @@ -2038,6 +2047,8 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe; u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + if (hotplug_trigger) ilk_hpd_irq_handler(dev_priv, hotplug_trigger); @@ -2087,6 +2098,8 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe; u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + if (hotplug_trigger) ilk_hpd_irq_handler(dev_priv, hotplug_trigger); @@ -2421,6 +2434,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) u32 iir; enum pipe pipe; + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + if (master_ctl & GEN8_DE_MISC_IRQ) { iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); if (iir) { @@ -3477,6 +3492,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) { u32 hotplug_irqs, enabled_irqs; + drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); + if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); From patchwork Mon Mar 22 18:10:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12155749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EDD6C433E0 for ; Mon, 22 Mar 2021 18:09:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB7D561878 for ; Mon, 22 Mar 2021 18:09:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CB7D561878 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A0EEE6E102; Mon, 22 Mar 2021 18:09:02 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 590CC6E102 for ; Mon, 22 Mar 2021 18:09:01 +0000 (UTC) IronPort-SDR: Ofg1/mF1Xl9t9/nIRcY6yBSIKdUxbsX+kc2977EAXnOreA4dXNbebF4IsIs1A0xtrEK+f66RSj LNA9cbtQVEeg== X-IronPort-AV: E=McAfee;i="6000,8403,9931"; a="169654091" X-IronPort-AV: E=Sophos;i="5.81,269,1610438400"; d="scan'208";a="169654091" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2021 11:09:00 -0700 IronPort-SDR: 4eE1wtkrWko6DI2PeA7wfm2YpYwk6uUKXzC3OlECDZ3y1mkS941jH/xZILO1qByeZ6n3UEMPmY jPm66rzvGKXQ== X-IronPort-AV: E=Sophos;i="5.81,269,1610438400"; d="scan'208";a="524538854" Received: from ryanmart-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.180.219]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2021 11:08:58 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Mar 2021 11:10:54 -0700 Message-Id: <20210322181055.207619-2-jose.souza@intel.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210322181055.207619-1-jose.souza@intel.com> References: <20210322181055.207619-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Do not set any power wells when there is no display X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Power wells are only part of display block and not necessary when running a headless driver. Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 7e0eaa872350..e6a3b3e6b1f7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4673,7 +4673,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) * The enabling order will be from lower to higher indexed wells, * the disabling order is reversed. */ - if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { + if (!HAS_DISPLAY(dev_priv)) { + power_domains->power_well_count = 0; + err = 0; + } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { err = set_power_wells_mask(power_domains, tgl_power_wells, BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); } else if (IS_ROCKETLAKE(dev_priv)) { From patchwork Mon Mar 22 18:10:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12155751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBCC1C433DB for ; Mon, 22 Mar 2021 18:09:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A522661584 for ; Mon, 22 Mar 2021 18:09:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A522661584 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 415B46E15D; Mon, 22 Mar 2021 18:09:05 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id D6DE76E15D for ; Mon, 22 Mar 2021 18:09:03 +0000 (UTC) IronPort-SDR: yDQWKnNZyUaCs01xj6V+mXCeqtxdzUJQEaraRV032pp8DnbB7GMblm9ic/5AXz74L2lQR0lEEE BbCxYpSZvusA== X-IronPort-AV: E=McAfee;i="6000,8403,9931"; a="169654098" X-IronPort-AV: E=Sophos;i="5.81,269,1610438400"; d="scan'208";a="169654098" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2021 11:09:03 -0700 IronPort-SDR: LWzR0u9xQ45hhdHdQpOgyBdz8okiM5eMMIvOG8jugLUHFRlmsiXNC4okvnhtg1O5h+SRJWOe+x YZVpq/UH3iqw== X-IronPort-AV: E=Sophos;i="5.81,269,1610438400"; d="scan'208";a="524538872" Received: from ryanmart-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.180.219]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2021 11:09:00 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Mar 2021 11:10:55 -0700 Message-Id: <20210322181055.207619-3-jose.souza@intel.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210322181055.207619-1-jose.souza@intel.com> References: <20210322181055.207619-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/3] drm/i915: skip display initialization when there is no display X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Display features should not be initialized or de-initialized when there is no display. Skip modeset initialization, output setup, plane, crtc, encoder, connector registration, display cdclk and rawclk initialization, display core initialization, etc. Skip the functionality at as high level as possible, and remove any redundant checks. If the functionality is conditional to *other* display checks, do not add more. If the un-initialization has checks for initialization, do not add more. We explicitly do not care about any GMCH/VLV/CHV code paths, as they've always had and will have display. Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 44 +++++++++++++++---- .../drm/i915/display/intel_display_power.c | 36 +++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.c | 6 +++ drivers/gpu/drm/i915/display/intel_gmbus.c | 3 -- drivers/gpu/drm/i915/display/intel_hotplug.c | 12 +++++ drivers/gpu/drm/i915/display/intel_pps.c | 5 ++- drivers/gpu/drm/i915/i915_drv.c | 28 +++++++++--- drivers/gpu/drm/i915/i915_suspend.c | 6 +++ 8 files changed, 120 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7b38b9a38b85..b10bf7e06ee7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1613,6 +1613,9 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, struct intel_crtc *crtc; struct intel_plane *plane; + if (!HAS_DISPLAY(dev_priv)) + return 0; + /* * We assume the primary plane for pipe A has * the highest stride limits of them all, @@ -4629,6 +4632,9 @@ int intel_display_suspend(struct drm_device *dev) struct drm_atomic_state *state; int ret; + if (!HAS_DISPLAY(dev_priv)) + return 0; + state = drm_atomic_helper_suspend(dev); ret = PTR_ERR_OR_ZERO(state); if (ret) @@ -12239,6 +12245,9 @@ static const struct drm_mode_config_funcs intel_mode_funcs = { */ void intel_init_display_hooks(struct drm_i915_private *dev_priv) { + if (!HAS_DISPLAY(dev_priv)) + return; + intel_init_cdclk_hooks(dev_priv); intel_init_audio_hooks(dev_priv); @@ -12281,8 +12290,12 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) void intel_modeset_init_hw(struct drm_i915_private *i915) { - struct intel_cdclk_state *cdclk_state = - to_intel_cdclk_state(i915->cdclk.obj.state); + struct intel_cdclk_state *cdclk_state; + + if (!HAS_DISPLAY(i915)) + return; + + cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state); intel_update_cdclk(i915); intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK"); @@ -12598,6 +12611,9 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915) /* FIXME: completely on the wrong abstraction layer */ intel_power_domains_init_hw(i915, false); + if (!HAS_DISPLAY(i915)) + return 0; + intel_csr_ucode_init(i915); i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); @@ -12648,6 +12664,9 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915) struct intel_crtc *crtc; int ret; + if (!HAS_DISPLAY(i915)) + return 0; + intel_init_pm(i915); intel_panel_sanitize_ssc(i915); @@ -12660,13 +12679,11 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915) INTEL_NUM_PIPES(i915), INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); - if (HAS_DISPLAY(i915)) { - for_each_pipe(i915, pipe) { - ret = intel_crtc_init(i915, pipe); - if (ret) { - intel_mode_config_cleanup(i915); - return ret; - } + for_each_pipe(i915, pipe) { + ret = intel_crtc_init(i915, pipe); + if (ret) { + intel_mode_config_cleanup(i915); + return ret; } } @@ -13602,6 +13619,9 @@ void intel_display_resume(struct drm_device *dev) struct drm_modeset_acquire_ctx ctx; int ret; + if (!HAS_DISPLAY(dev_priv)) + return; + dev_priv->modeset_restore_state = NULL; if (state) state->acquire_ctx = &ctx; @@ -13651,6 +13671,9 @@ static void intel_hpd_poll_fini(struct drm_i915_private *i915) /* part #1: call before irq uninstall */ void intel_modeset_driver_remove(struct drm_i915_private *i915) { + if (!HAS_DISPLAY(i915)) + return; + flush_workqueue(i915->flip_wq); flush_workqueue(i915->modeset_wq); @@ -13661,6 +13684,9 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915) /* part #2: call after irq uninstall */ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) { + if (!HAS_DISPLAY(i915)) + return; + /* * Due to the hpd irq storm handling the hotplug work can re-arm the * poll handlers. Hence disable polling after hpd handling is shut down. diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index e6a3b3e6b1f7..efacd6aba3d0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -821,6 +821,9 @@ static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) { u32 val; + if (!HAS_DISPLAY(dev_priv)) + return; + val = intel_de_read(dev_priv, DC_STATE_EN) & gen9_dc_mask(dev_priv); drm_dbg_kms(&dev_priv->drm, @@ -857,6 +860,9 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) u32 val; u32 mask; + if (!HAS_DISPLAY(dev_priv)) + return; + if (drm_WARN_ON_ONCE(&dev_priv->drm, state & ~dev_priv->csr.allowed_dc_mask)) state &= dev_priv->csr.allowed_dc_mask; @@ -1181,6 +1187,9 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + if (!HAS_DISPLAY(dev_priv)) + return; + dev_priv->display.get_cdclk(dev_priv, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ drm_WARN_ON(&dev_priv->drm, @@ -4533,6 +4542,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, int requested_dc; int max_dc; + if (!HAS_DISPLAY(dev_priv)) + return 0; + if (IS_DG1(dev_priv)) max_dc = 3; else if (INTEL_GEN(dev_priv) >= 12) @@ -5125,6 +5137,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, /* enable PCH reset handshake */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); + if (!HAS_DISPLAY(dev_priv)) + return; + /* enable PG1 and Misc I/O */ mutex_lock(&power_domains->lock); @@ -5149,6 +5164,9 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *well; + if (!HAS_DISPLAY(dev_priv)) + return; + gen9_disable_dc_states(dev_priv); gen9_dbuf_disable(dev_priv); @@ -5189,6 +5207,9 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume */ intel_pch_reset_handshake(dev_priv, false); + if (!HAS_DISPLAY(dev_priv)) + return; + /* Enable PG1 */ mutex_lock(&power_domains->lock); @@ -5210,6 +5231,9 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *well; + if (!HAS_DISPLAY(dev_priv)) + return; + gen9_disable_dc_states(dev_priv); gen9_dbuf_disable(dev_priv); @@ -5243,6 +5267,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume /* 1. Enable PCH Reset Handshake */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); + if (!HAS_DISPLAY(dev_priv)) + return; + /* 2-3. */ intel_combo_phy_init(dev_priv); @@ -5270,6 +5297,9 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *well; + if (!HAS_DISPLAY(dev_priv)) + return; + gen9_disable_dc_states(dev_priv); /* 1. Disable all display engine functions -> aready done */ @@ -5384,6 +5414,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, /* 1. Enable PCH reset handshake. */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); + if (!HAS_DISPLAY(dev_priv)) + return; + /* 2. Initialize all combo phys */ intel_combo_phy_init(dev_priv); @@ -5428,6 +5461,9 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *well; + if (!HAS_DISPLAY(dev_priv)) + return; + gen9_disable_dc_states(dev_priv); /* 1. Disable all display engine functions -> aready done */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1400c5b44c83..fc00bacd00c4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5427,6 +5427,9 @@ void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; + if (!HAS_DISPLAY(dev_priv)) + return; + for_each_intel_encoder(&dev_priv->drm, encoder) { struct intel_dp *intel_dp; @@ -5447,6 +5450,9 @@ void intel_dp_mst_resume(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; + if (!HAS_DISPLAY(dev_priv)) + return; + for_each_intel_encoder(&dev_priv->drm, encoder) { struct intel_dp *intel_dp; int ret; diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 0c952e1d720e..5ee599d20050 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -845,9 +845,6 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv) unsigned int pin; int ret; - if (!HAS_DISPLAY(dev_priv)) - return 0; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; else if (!HAS_GMCH(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 77ce4a54a137..b4680ecb743f 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -597,6 +597,9 @@ void intel_hpd_init(struct drm_i915_private *dev_priv) { int i; + if (!HAS_DISPLAY(dev_priv)) + return; + for_each_hpd_pin(i) { dev_priv->hotplug.stats[i].count = 0; dev_priv->hotplug.stats[i].state = HPD_ENABLED; @@ -672,6 +675,9 @@ static void i915_hpd_poll_init_work(struct work_struct *work) */ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv) { + if (!HAS_DISPLAY(dev_priv)) + return; + WRITE_ONCE(dev_priv->hotplug.poll_enabled, true); /* @@ -704,6 +710,9 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv) */ void intel_hpd_poll_disable(struct drm_i915_private *dev_priv) { + if (!HAS_DISPLAY(dev_priv)) + return; + WRITE_ONCE(dev_priv->hotplug.poll_enabled, false); schedule_work(&dev_priv->hotplug.poll_init_work); } @@ -720,6 +729,9 @@ void intel_hpd_init_work(struct drm_i915_private *dev_priv) void intel_hpd_cancel_work(struct drm_i915_private *dev_priv) { + if (!HAS_DISPLAY(dev_priv)) + return; + spin_lock_irq(&dev_priv->irq_lock); dev_priv->hotplug.long_port_mask = 0; diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 932f56951914..e1aacd25c9d8 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -319,6 +319,9 @@ void intel_pps_reset_all(struct drm_i915_private *dev_priv) IS_GEN9_LP(dev_priv)))) return; + if (!HAS_DISPLAY(dev_priv)) + return; + /* * We can't grab pps_mutex here due to deadlock with power_domain * mutex when power_domain functions are called while holding pps_mutex. @@ -1378,7 +1381,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) int pps_num; int pps_idx; - if (HAS_DDI(dev_priv)) + if (!HAS_DISPLAY(dev_priv) || HAS_DDI(dev_priv)) return; /* * This w/a is needed at least on CPT/PPT, but to be sure apply it diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 64edcab59fe1..ee27962a6044 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -977,8 +977,12 @@ static int i915_driver_open(struct drm_device *dev, struct drm_file *file) */ static void i915_driver_lastclose(struct drm_device *dev) { + struct drm_i915_private *i915 = to_i915(dev); + intel_fbdev_restore_mode(dev); - vga_switcheroo_process_delayed_switch(); + + if (HAS_DISPLAY(i915)) + vga_switcheroo_process_delayed_switch(); } static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) @@ -999,6 +1003,9 @@ static void intel_suspend_encoders(struct drm_i915_private *dev_priv) struct drm_device *dev = &dev_priv->drm; struct intel_encoder *encoder; + if (!HAS_DISPLAY(dev_priv)) + return; + drm_modeset_lock_all(dev); for_each_intel_encoder(dev, encoder) if (encoder->suspend) @@ -1011,6 +1018,9 @@ static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) struct drm_device *dev = &dev_priv->drm; struct intel_encoder *encoder; + if (!HAS_DISPLAY(dev_priv)) + return; + drm_modeset_lock_all(dev); for_each_intel_encoder(dev, encoder) if (encoder->shutdown) @@ -1026,9 +1036,11 @@ void i915_driver_shutdown(struct drm_i915_private *i915) i915_gem_suspend(i915); - drm_kms_helper_poll_disable(&i915->drm); + if (HAS_DISPLAY(i915)) { + drm_kms_helper_poll_disable(&i915->drm); - drm_atomic_helper_shutdown(&i915->drm); + drm_atomic_helper_shutdown(&i915->drm); + } intel_dp_mst_suspend(i915); @@ -1084,8 +1096,8 @@ static int i915_drm_suspend(struct drm_device *dev) /* We do a lot of poking in a lot of registers, make sure they work * properly. */ intel_power_domains_disable(dev_priv); - - drm_kms_helper_poll_disable(dev); + if (HAS_DISPLAY(dev_priv)) + drm_kms_helper_poll_disable(dev); pci_save_state(pdev); @@ -1232,7 +1244,8 @@ static int i915_drm_resume(struct drm_device *dev) */ intel_runtime_pm_enable_interrupts(dev_priv); - drm_mode_config_reset(dev); + if (HAS_DISPLAY(dev_priv)) + drm_mode_config_reset(dev); i915_gem_resume(dev_priv); @@ -1245,7 +1258,8 @@ static int i915_drm_resume(struct drm_device *dev) intel_display_resume(dev); intel_hpd_poll_disable(dev_priv); - drm_kms_helper_poll_enable(dev); + if (HAS_DISPLAY(dev_priv)) + drm_kms_helper_poll_enable(dev); intel_opregion_resume(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 0bc7b49f843c..5fcc32821e18 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -87,6 +87,9 @@ void i915_save_display(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + if (!HAS_DISPLAY(dev_priv)) + return; + /* Display arbitration control */ if (INTEL_GEN(dev_priv) <= 4) dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); @@ -102,6 +105,9 @@ void i915_restore_display(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + if (!HAS_DISPLAY(dev_priv)) + return; + intel_restore_swf(dev_priv); if (IS_GEN(dev_priv, 4))