From patchwork Wed Mar 24 12:37:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kai Vehmanen X-Patchwork-Id: 12161021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE908C433DB for ; Wed, 24 Mar 2021 12:41:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 56F5261A06 for ; Wed, 24 Mar 2021 12:41:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 56F5261A06 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BE40E6E9F9; Wed, 24 Mar 2021 12:41:34 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id D19EE6E9F9 for ; Wed, 24 Mar 2021 12:41:33 +0000 (UTC) IronPort-SDR: Y7sEeV2Sx3YXLc6AzTr0yKf9T3HBJHTK70ASitFYdsqxok00ScVwuVIg07AWDDpE66tGVF3OkQ fyVZV2PC2ddw== X-IronPort-AV: E=McAfee;i="6000,8403,9932"; a="178251222" X-IronPort-AV: E=Sophos;i="5.81,274,1610438400"; d="scan'208";a="178251222" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2021 05:41:31 -0700 IronPort-SDR: e/lfci7ism2fZgPg4RWYfloboJ//g9AmR4buU/a5xELrRymFhl+p0J5uF4vpCRQXh0R3d94+HD 7jcxGG0sRf9Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,274,1610438400"; d="scan'208";a="442951942" Received: from eliteleevi.tm.intel.com ([10.237.54.20]) by FMSMGA003.fm.intel.com with ESMTP; 24 Mar 2021 05:41:26 -0700 From: Kai Vehmanen To: intel-gfx@lists.freedesktop.org Date: Wed, 24 Mar 2021 14:37:25 +0200 Message-Id: <20210324123725.4170214-1-kai.vehmanen@linux.intel.com> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2] drm/i915/audio: set HDA link parameters in driver X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Update logic to program AUD_FREQ_CNTRL register based on new guidance. Earlier this register was configured by BIOS and driver discovered the value at init. This is no longer recommended and instead driver should set the values based on the hardware revision. Add the recommended values for all supported hardware. This change applies for all GEN12+ hardware. For TGL, some special case handling is needed to not break existing systems. Extend the debug print to also include values of the register as written by BIOS. This can help debug rare cases where BIOS has configured the link settings to incorrect values. Bspec: 49279 Signed-off-by: Kai Vehmanen Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_audio.c | 30 ++++++++++++++++++---- 1 file changed, 25 insertions(+), 5 deletions(-) base-commit: 9d58aa46291d4d696bb1eac3436d3118f7bf2573 diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 3ea20c857440..9671c8f6e892 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -1266,6 +1266,15 @@ static const struct component_ops i915_audio_component_bind_ops = { .unbind = i915_audio_component_unbind, }; +#define AUD_FREQ_TMODE_SHIFT 14 +#define AUD_FREQ_4T 0 +#define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) +#define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) +#define AUD_FREQ_BCLK_96M BIT(4) + +#define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) +#define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) + /** * i915_audio_component_init - initialize and register the audio component * @dev_priv: i915 device instance @@ -1284,6 +1293,7 @@ static const struct component_ops i915_audio_component_bind_ops = { */ static void i915_audio_component_init(struct drm_i915_private *dev_priv) { + u32 aud_freq, aud_freq_init; int ret; ret = component_add_typed(dev_priv->drm.dev, @@ -1297,11 +1307,21 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv) } if (DISPLAY_VER(dev_priv) >= 9) { - dev_priv->audio_freq_cntrl = intel_de_read(dev_priv, - AUD_FREQ_CNTRL); - drm_dbg_kms(&dev_priv->drm, - "init value of AUD_FREQ_CNTRL of 0x%x\n", - dev_priv->audio_freq_cntrl); + aud_freq_init = intel_de_read(dev_priv, AUD_FREQ_CNTRL); + + if (INTEL_GEN(dev_priv) >= 12) + aud_freq = AUD_FREQ_GEN12; + else + aud_freq = aud_freq_init; + + /* use BIOS provided value for TGL unless it is a known bad value */ + if (IS_TIGERLAKE(dev_priv) && aud_freq_init != AUD_FREQ_TGL_BROKEN) + aud_freq = aud_freq_init; + + drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", + aud_freq, aud_freq_init); + + dev_priv->audio_freq_cntrl = aud_freq; } dev_priv->audio_component_registered = true;