From patchwork Wed Mar 24 15:00:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7CA7C433E0 for ; Wed, 24 Mar 2021 15:00:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A0C4161A0E for ; Wed, 24 Mar 2021 15:00:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A0C4161A0E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ECA576EA24; Wed, 24 Mar 2021 15:00:34 +0000 (UTC) Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by gabe.freedesktop.org (Postfix) with ESMTPS id B69796EA24 for ; Wed, 24 Mar 2021 15:00:31 +0000 (UTC) Received: by mail-lf1-x12a.google.com with SMTP id b4so8495781lfi.6 for ; Wed, 24 Mar 2021 08:00:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V5a0SElwgMSR05OnVZxlFyzafRcs18clf2FpnQ1Pirw=; b=FXluN6BbG0HZTXJyP6TVendzyux+n4NQNsn62YDIl3r/Qny5xdJHvNxbxGhpTrCQ7W gIGKyE8tqlpcLOmjhNAa8wLoN0pp+5LDqnlf9sYGsTRyR39zxWWJPEc9S9c8FMPOV30w ftto/Aga4NhiyCJHnsTQYOvI/mGU5s5lSrk5WT0HYFY6HKoc7WjYfQrbpN28Kd8uQnpa dP3k6QNk/efsrfLBbVqgQhcahr74CzaVBPh3USS9P/HjhgDUg7WrwpRISyLcKiuTOyFF YZA4XfiII9nut4F8PLNh2vFUPekIPM+OhNk+fLGZGWElNWcqwYcQaCR+WhvNTOdSi1lF HNnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V5a0SElwgMSR05OnVZxlFyzafRcs18clf2FpnQ1Pirw=; b=dK2SP2w6aE7N8Ub3BJffi3QvGVL0I21PZxYhn7DECqYnuorGnWctQLT52eiOhKaEIM M4N185dus3Smx9QiHTgsR25z7zErA4dT6pJi+5x5Quxmzx16zw6ZS7MybTDah4piJcxv upX7C90Z8bE5ipR/8PGD0qxYG3LxryZAxsA9gyyvB8w52qW3ooVC9YZrIveX56PqTrvk wUzLT6zO83/oiLGjuG049mzw0ifsBn8SkAHrPyxX4uGqARmuCv0AXmlCcvYG+Zdyu+1f WGM2r6tMbO0QwP+c4Dr48fvgIvLmFTnt5nn2UpAAtrLrNkVPWLZSSTDFw9H05169mGs3 1DRw== X-Gm-Message-State: AOAM532kvDP1CDtzAOUhkQUAv6pzWy5RPdwDvPPiMf0jBdDbVgxYnGeU RRjlACz3bFUUGJ/ABQ9eOO63hQ== X-Google-Smtp-Source: ABdhPJw6w16Zus9bj6ywWeRfCOVFk45iSfhf9EZexnbh1wiTTH2GJmAbiUgKI4AgiZpogPcSPoTmFQ== X-Received: by 2002:ac2:414c:: with SMTP id c12mr2185512lfi.538.1616598030092; Wed, 24 Mar 2021 08:00:30 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:29 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 01/21] drm/msm/dpu: enable DPU_SSPP_QOS_8LVL for SM8250 Date: Wed, 24 Mar 2021 18:00:04 +0300 Message-Id: <20210324150024.2768215-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" SM8250 platform has a 8-Levels VIG QoS setting. This setting was missed due to bad interaction with b8dab65b5ac3 ("drm/msm/dpu: Move DPU_SSPP_QOS_8LVL bit to SDM845 and SC7180 masks"), which was applied in parallel. Fixes: d21fc5dfc3df ("drm/msm/dpu1: add support for qseed3lite used on sm8250") Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 189f3533525c..e4444452759c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -22,7 +22,7 @@ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) #define VIG_SM8250_MASK \ - (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3LITE)) + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) #define DMA_SDM845_MASK \ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ From patchwork Wed Mar 24 15:00:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0896CC433E1 for ; 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Wed, 24 Mar 2021 08:00:31 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:30 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 02/21] drm/msm/dpu: remove unused dpu_hw_blk features Date: Wed, 24 Mar 2021 18:00:05 +0300 Message-Id: <20210324150024.2768215-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Remove all unused dpu_hw_blk features and functions: - dpu_hw_blk_get()/_put() and respective refcounting, - global list of all dpu_hw_blk instances, - dpu_hw_blk_ops and empty implementation inside each hw_blk subdriver. This leaves dpu_hw_blk as a placeholder with just type and index. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c | 104 +----------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h | 19 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 4 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 4 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 4 +- 10 files changed, 10 insertions(+), 145 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c index 819b26e660b9..abad043f35f5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c @@ -11,33 +11,16 @@ #include "dpu_hw_mdss.h" #include "dpu_hw_blk.h" -/* Serialization lock for dpu_hw_blk_list */ -static DEFINE_MUTEX(dpu_hw_blk_lock); - -/* List of all hw block objects */ -static LIST_HEAD(dpu_hw_blk_list); - /** * dpu_hw_blk_init - initialize hw block object * @hw_blk: pointer to hw block object * @type: hw block type - enum dpu_hw_blk_type * @id: instance id of the hw block - * @ops: Pointer to block operations */ -void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, - struct dpu_hw_blk_ops *ops) +void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id) { - INIT_LIST_HEAD(&hw_blk->list); hw_blk->type = type; hw_blk->id = id; - atomic_set(&hw_blk->refcount, 0); - - if (ops) - hw_blk->ops = *ops; - - mutex_lock(&dpu_hw_blk_lock); - list_add(&hw_blk->list, &dpu_hw_blk_list); - mutex_unlock(&dpu_hw_blk_lock); } /** @@ -51,89 +34,4 @@ void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk) pr_err("invalid parameters\n"); return; } - - if (atomic_read(&hw_blk->refcount)) - pr_err("hw_blk:%d.%d invalid refcount\n", hw_blk->type, - hw_blk->id); - - mutex_lock(&dpu_hw_blk_lock); - list_del(&hw_blk->list); - mutex_unlock(&dpu_hw_blk_lock); -} - -/** - * dpu_hw_blk_get - get hw_blk from free pool - * @hw_blk: if specified, increment reference count only - * @type: if hw_blk is not specified, allocate the next available of this type - * @id: if specified (>= 0), allocate the given instance of the above type - * return: pointer to hw block object - */ -struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id) -{ - struct dpu_hw_blk *curr; - int rc, refcount; - - if (!hw_blk) { - mutex_lock(&dpu_hw_blk_lock); - list_for_each_entry(curr, &dpu_hw_blk_list, list) { - if ((curr->type != type) || - (id >= 0 && curr->id != id) || - (id < 0 && - atomic_read(&curr->refcount))) - continue; - - hw_blk = curr; - break; - } - mutex_unlock(&dpu_hw_blk_lock); - } - - if (!hw_blk) { - pr_debug("no hw_blk:%d\n", type); - return NULL; - } - - refcount = atomic_inc_return(&hw_blk->refcount); - - if (refcount == 1 && hw_blk->ops.start) { - rc = hw_blk->ops.start(hw_blk); - if (rc) { - pr_err("failed to start hw_blk:%d rc:%d\n", type, rc); - goto error_start; - } - } - - pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, - hw_blk->id, refcount); - return hw_blk; - -error_start: - dpu_hw_blk_put(hw_blk); - return ERR_PTR(rc); -} - -/** - * dpu_hw_blk_put - put hw_blk to free pool if decremented refcount is zero - * @hw_blk: hw block to be freed - */ -void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk) -{ - if (!hw_blk) { - pr_err("invalid parameters\n"); - return; - } - - pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, hw_blk->id, - atomic_read(&hw_blk->refcount)); - - if (!atomic_read(&hw_blk->refcount)) { - pr_err("hw_blk:%d.%d invalid put\n", hw_blk->type, hw_blk->id); - return; - } - - if (atomic_dec_return(&hw_blk->refcount)) - return; - - if (hw_blk->ops.stop) - hw_blk->ops.stop(hw_blk); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h index 2bf737f8dd1b..fb3be9a36a50 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h @@ -7,19 +7,9 @@ #include #include -#include struct dpu_hw_blk; -/** - * struct dpu_hw_blk_ops - common hardware block operations - * @start: start operation on first get - * @stop: stop operation on last put - */ -struct dpu_hw_blk_ops { - int (*start)(struct dpu_hw_blk *); - void (*stop)(struct dpu_hw_blk *); -}; /** * struct dpu_hw_blk - definition of hardware block object @@ -29,17 +19,10 @@ struct dpu_hw_blk_ops { * @refcount: reference/usage count */ struct dpu_hw_blk { - struct list_head list; u32 type; int id; - atomic_t refcount; - struct dpu_hw_blk_ops ops; }; -void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, - struct dpu_hw_blk_ops *ops); +void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id); void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk); - -struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id); -void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk); #endif /*_DPU_HW_BLK_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 8981cfa9dbc3..ad60d59d3106 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -560,8 +560,6 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->get_bitmask_dspp = dpu_hw_ctl_get_bitmask_dspp; }; -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -586,7 +584,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, c->mixer_count = m->mixer_count; c->mixer_hw_caps = m->mixer; - dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx); return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c index e42f901a7de5..d2f1045a736a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -85,8 +85,6 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp, return ERR_PTR(-EINVAL); } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -112,7 +110,7 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, c->cap = cfg; _setup_dspp_ops(c, c->cap->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx); return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 6f0f54588124..db78842e3999 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -289,8 +289,6 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -317,7 +315,7 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, c->mdss = m; _setup_intf_ops(&c->ops, c->cap->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx); return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 6ac0b5a0e057..554bb881de3a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -160,8 +160,6 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, ops->setup_border_color = dpu_hw_lm_setup_border_color; } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -184,7 +182,7 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, c->cap = cfg; _setup_mixer_ops(m, &c->ops, c->cap->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx); return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c index 720813e5a8ae..863229dd0140 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c @@ -58,8 +58,6 @@ static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c, c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode; }; -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -81,7 +79,7 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, c->caps = cfg; _setup_merge_3d_ops(c, c->caps->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx); return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 245a7a62b5c6..334d5b28f533 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -261,8 +261,6 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, c->ops.setup_dither = dpu_hw_pp_setup_dither; }; -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -284,7 +282,7 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, c->caps = cfg; _setup_pingpong_ops(c, c->caps->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx); return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 34d81aa16041..ceb2488ea270 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -706,8 +706,6 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, return ERR_PTR(-ENOMEM); } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, void __iomem *addr, struct dpu_mdss_cfg *catalog, bool is_virtual_pipe) @@ -735,7 +733,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, hw_pipe->cap = cfg; _setup_layer_ops(hw_pipe, hw_pipe->cap->features); - dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops); + dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx); return hw_pipe; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 01b76766a9a8..5d2c33ec1de7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -295,8 +295,6 @@ static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp, return ERR_PTR(-EINVAL); } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -324,7 +322,7 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, mdp->caps = cfg; _setup_mdp_ops(&mdp->ops, mdp->caps->features); - dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops); + dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx); return mdp; } From patchwork Wed Mar 24 15:00:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63BCBC433DB for ; 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Wed, 24 Mar 2021 08:00:33 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:32 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 03/21] drm/msm/dpu: drop dpu_hw_blk_destroy function Date: Wed, 24 Mar 2021 18:00:06 +0300 Message-Id: <20210324150024.2768215-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The dpu_hw_blk_destroy() function is empty, so we can drop it now. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c | 13 ------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 -- 10 files changed, 31 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c index abad043f35f5..1f2b74b9eb65 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c @@ -22,16 +22,3 @@ void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id) hw_blk->type = type; hw_blk->id = id; } - -/** - * dpu_hw_blk_destroy - destroy hw block object. - * @hw_blk: pointer to hw block object - * return: none - */ -void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk) -{ - if (!hw_blk) { - pr_err("invalid parameters\n"); - return; - } -} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h index fb3be9a36a50..7768694b558a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h @@ -24,5 +24,4 @@ struct dpu_hw_blk { }; void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id); -void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk); #endif /*_DPU_HW_BLK_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index ad60d59d3106..ac0f10dd0490 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -591,7 +591,5 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx) { - if (ctx) - dpu_hw_blk_destroy(&ctx->base); kfree(ctx); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c index d2f1045a736a..977b25968f34 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -117,9 +117,6 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp) { - if (dspp) - dpu_hw_blk_destroy(&dspp->base); - kfree(dspp); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index db78842e3999..8df75936d906 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -322,8 +322,6 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, void dpu_hw_intf_destroy(struct dpu_hw_intf *intf) { - if (intf) - dpu_hw_blk_destroy(&intf->base); kfree(intf); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 554bb881de3a..76f8b8f75b82 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -189,7 +189,5 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) { - if (lm) - dpu_hw_blk_destroy(&lm->base); kfree(lm); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c index 863229dd0140..406ba950a066 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c @@ -86,7 +86,5 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *hw) { - if (hw) - dpu_hw_blk_destroy(&hw->base); kfree(hw); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 334d5b28f533..92cd724263ce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -289,7 +289,5 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp) { - if (pp) - dpu_hw_blk_destroy(&pp->base); kfree(pp); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index ceb2488ea270..8734a47040aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -740,8 +740,6 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx) { - if (ctx) - dpu_hw_blk_destroy(&ctx->base); kfree(ctx); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 5d2c33ec1de7..dae77d9c2c74 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -329,8 +329,6 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp) { - if (mdp) - dpu_hw_blk_destroy(&mdp->base); kfree(mdp); } From patchwork Wed Mar 24 15:00:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161355 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D053C433C1 for ; Wed, 24 Mar 2021 15:00:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18EFC61A0D for ; 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Wed, 24 Mar 2021 08:00:35 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:33 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 04/21] drm/msm/dpu: get DSPP blocks directly rather than through RM Date: Wed, 24 Mar 2021 18:00:07 +0300 Message-Id: <20210324150024.2768215-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Each DSPP block is tied to a single LM. No LMs can share single DSPP block. So there is no need to handle DSPP blocks through all resource allocation/deallocation/assignment, just receive DSPP block as a part of LM hardware instance. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 116 ++++++-------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 - 6 files changed, 44 insertions(+), 88 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 288e95ee8e1d..b3d50f6d976d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -977,7 +977,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; int num_lm, num_ctl, num_pp; int i, j; @@ -1028,9 +1027,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); - dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp, - ARRAY_SIZE(hw_dspp)); for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) @@ -1043,7 +1039,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); - cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]); + cstate->mixers[i].hw_dspp = cstate->mixers[i].hw_lm->dspp; } cstate->num_mixers = num_lm; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 76f8b8f75b82..35675744a6b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -5,6 +5,7 @@ #include "dpu_kms.h" #include "dpu_hw_catalog.h" #include "dpu_hwio.h" +#include "dpu_hw_dspp.h" #include "dpu_hw_lm.h" #include "dpu_hw_mdss.h" @@ -182,6 +183,9 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, c->cap = cfg; _setup_mixer_ops(m, &c->ops, c->cap->features); + if (cfg->dspp && cfg->dspp < DSPP_MAX) + c->dspp = dpu_hw_dspp_init(cfg->dspp, addr, m); + dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx); return c; @@ -189,5 +193,7 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) { + if (lm) + dpu_hw_dspp_destroy(lm->dspp); kfree(lm); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h index 4a6b2de19ef6..effb78311a43 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -64,6 +64,7 @@ struct dpu_hw_mixer { const struct dpu_lm_cfg *cap; const struct dpu_mdp_cfg *mdp; const struct dpu_ctl_cfg *ctl; + struct dpu_hw_dspp *dspp; /* ops */ struct dpu_hw_lm_ops ops; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index d6717d6672f7..195a854245fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -164,7 +164,6 @@ struct dpu_global_state { uint32_t mixer_to_enc_id[LM_MAX - LM_0]; uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; - uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; }; struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index fd2d104f0a91..bb03ff8b8c9f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -9,7 +9,6 @@ #include "dpu_hw_ctl.h" #include "dpu_hw_pingpong.h" #include "dpu_hw_intf.h" -#include "dpu_hw_dspp.h" #include "dpu_hw_merge3d.h" #include "dpu_encoder.h" #include "dpu_trace.h" @@ -35,6 +34,14 @@ int dpu_rm_destroy(struct dpu_rm *rm) { int i; + for (i = 0; i < ARRAY_SIZE(rm->mixer_blks); i++) { + struct dpu_hw_mixer *hw; + + if (rm->mixer_blks[i]) { + hw = to_dpu_hw_mixer(rm->mixer_blks[i]); + dpu_hw_lm_destroy(hw); + } + } for (i = 0; i < ARRAY_SIZE(rm->pingpong_blks); i++) { struct dpu_hw_pingpong *hw; @@ -51,14 +58,6 @@ int dpu_rm_destroy(struct dpu_rm *rm) dpu_hw_merge_3d_destroy(hw); } } - for (i = 0; i < ARRAY_SIZE(rm->mixer_blks); i++) { - struct dpu_hw_mixer *hw; - - if (rm->mixer_blks[i]) { - hw = to_dpu_hw_mixer(rm->mixer_blks[i]); - dpu_hw_lm_destroy(hw); - } - } for (i = 0; i < ARRAY_SIZE(rm->ctl_blks); i++) { struct dpu_hw_ctl *hw; @@ -94,40 +93,6 @@ int dpu_rm_init(struct dpu_rm *rm, memset(rm, 0, sizeof(*rm)); /* Interrogate HW catalog and create tracking items for hw blocks */ - for (i = 0; i < cat->mixer_count; i++) { - struct dpu_hw_mixer *hw; - const struct dpu_lm_cfg *lm = &cat->mixer[i]; - - if (lm->pingpong == PINGPONG_MAX) { - DPU_DEBUG("skip mixer %d without pingpong\n", lm->id); - continue; - } - - if (lm->id < LM_0 || lm->id >= LM_MAX) { - DPU_ERROR("skip mixer %d with invalid id\n", lm->id); - continue; - } - hw = dpu_hw_lm_init(lm->id, mmio, cat); - if (IS_ERR_OR_NULL(hw)) { - rc = PTR_ERR(hw); - DPU_ERROR("failed lm object creation: err %d\n", rc); - goto fail; - } - rm->mixer_blks[lm->id - LM_0] = &hw->base; - - if (!rm->lm_max_width) { - rm->lm_max_width = lm->sblk->maxwidth; - } else if (rm->lm_max_width != lm->sblk->maxwidth) { - /* - * Don't expect to have hw where lm max widths differ. - * If found, take the min. - */ - DPU_ERROR("unsupported: lm maxwidth differs\n"); - if (rm->lm_max_width > lm->sblk->maxwidth) - rm->lm_max_width = lm->sblk->maxwidth; - } - } - for (i = 0; i < cat->merge_3d_count; i++) { struct dpu_hw_merge_3d *hw; const struct dpu_merge_3d_cfg *merge_3d = &cat->merge_3d[i]; @@ -204,21 +169,38 @@ int dpu_rm_init(struct dpu_rm *rm, rm->ctl_blks[ctl->id - CTL_0] = &hw->base; } - for (i = 0; i < cat->dspp_count; i++) { - struct dpu_hw_dspp *hw; - const struct dpu_dspp_cfg *dspp = &cat->dspp[i]; + for (i = 0; i < cat->mixer_count; i++) { + struct dpu_hw_mixer *hw; + const struct dpu_lm_cfg *lm = &cat->mixer[i]; - if (dspp->id < DSPP_0 || dspp->id >= DSPP_MAX) { - DPU_ERROR("skip dspp %d with invalid id\n", dspp->id); + if (lm->pingpong == PINGPONG_MAX) { + DPU_DEBUG("skip mixer %d without pingpong\n", lm->id); + continue; + } + + if (lm->id < LM_0 || lm->id >= LM_MAX) { + DPU_ERROR("skip mixer %d with invalid id\n", lm->id); continue; } - hw = dpu_hw_dspp_init(dspp->id, mmio, cat); + hw = dpu_hw_lm_init(lm->id, mmio, cat); if (IS_ERR_OR_NULL(hw)) { rc = PTR_ERR(hw); - DPU_ERROR("failed dspp object creation: err %d\n", rc); + DPU_ERROR("failed lm object creation: err %d\n", rc); goto fail; } - rm->dspp_blks[dspp->id - DSPP_0] = &hw->base; + rm->mixer_blks[lm->id - LM_0] = &hw->base; + + if (!rm->lm_max_width) { + rm->lm_max_width = lm->sblk->maxwidth; + } else if (rm->lm_max_width != lm->sblk->maxwidth) { + /* + * Don't expect to have hw where lm max widths differ. + * If found, take the min. + */ + DPU_ERROR("unsupported: lm maxwidth differs\n"); + if (rm->lm_max_width > lm->sblk->maxwidth) + rm->lm_max_width = lm->sblk->maxwidth; + } } return 0; @@ -271,15 +253,13 @@ static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx, * available and appropriate * @pp_idx: output parameter, index of pingpong block attached to the layer * mixer in rm->pingpong_blks[]. - * @dspp_idx: output parameter, index of dspp block attached to the layer - * mixer in rm->dspp_blks[]. * @reqs: input parameter, rm requirements for HW blocks needed in the * datapath. * Return: true if lm matches all requirements, false otherwise */ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, struct dpu_global_state *global_state, - uint32_t enc_id, int lm_idx, int *pp_idx, int *dspp_idx, + uint32_t enc_id, int lm_idx, int *pp_idx, struct dpu_rm_requirements *reqs) { const struct dpu_lm_cfg *lm_cfg; @@ -305,22 +285,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, } *pp_idx = idx; - if (!reqs->topology.num_dspp) - return true; - - idx = lm_cfg->dspp - DSPP_0; - if (idx < 0 || idx >= ARRAY_SIZE(rm->dspp_blks)) { - DPU_ERROR("failed to get dspp on lm %d\n", lm_cfg->dspp); - return false; - } - - if (reserved_by_other(global_state->dspp_to_enc_id, idx, enc_id)) { - DPU_DEBUG("lm %d dspp %d already reserved\n", lm_cfg->id, - lm_cfg->dspp); - return false; - } - *dspp_idx = idx; - return true; } @@ -332,7 +296,6 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, { int lm_idx[MAX_BLOCKS]; int pp_idx[MAX_BLOCKS]; - int dspp_idx[MAX_BLOCKS] = {0}; int i, j, lm_count = 0; if (!reqs->topology.num_lm) { @@ -351,7 +314,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, enc_id, i, &pp_idx[lm_count], - &dspp_idx[lm_count], reqs)) { + reqs)) { continue; } @@ -371,7 +334,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, enc_id, j, - &pp_idx[lm_count], &dspp_idx[lm_count], + &pp_idx[lm_count], reqs)) { continue; } @@ -389,8 +352,6 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, for (i = 0; i < lm_count; i++) { global_state->mixer_to_enc_id[lm_idx[i]] = enc_id; global_state->pingpong_to_enc_id[pp_idx[i]] = enc_id; - global_state->dspp_to_enc_id[dspp_idx[i]] = - reqs->topology.num_dspp ? enc_id : 0; trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, pp_idx[i] + PINGPONG_0); @@ -635,11 +596,6 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, hw_to_enc_id = global_state->intf_to_enc_id; max_blks = ARRAY_SIZE(rm->intf_blks); break; - case DPU_HW_BLK_DSPP: - hw_blks = rm->dspp_blks; - hw_to_enc_id = global_state->dspp_to_enc_id; - max_blks = ARRAY_SIZE(rm->dspp_blks); - break; default: DPU_ERROR("blk type %d not managed by rm\n", type); return 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 1f12c8d5b8aa..91952af6c75b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -19,7 +19,6 @@ struct dpu_global_state; * @mixer_blks: array of layer mixer hardware resources * @ctl_blks: array of ctl hardware resources * @intf_blks: array of intf hardware resources - * @dspp_blks: array of dspp hardware resources * @lm_max_width: cached layer mixer maximum width * @rm_lock: resource manager mutex */ @@ -28,7 +27,6 @@ struct dpu_rm { struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; - struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; uint32_t lm_max_width; From patchwork Wed Mar 24 15:00:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24599C433E0 for ; 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Wed, 24 Mar 2021 08:00:36 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:35 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 05/21] drm/msm/dpu: get MERGE_3D blocks directly rather than through RM Date: Wed, 24 Mar 2021 18:00:08 +0300 Message-Id: <20210324150024.2768215-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" MERGE_3D blocks are not really handled by resource manager, they are used by corresponding PP blocks directly, each merge_3d is used by two known PP blocks. So allocate them outside of RM and use them directly. Signed-off-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 +++--- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 7 +++- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 6 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 27 +++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 36 +++---------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 8 ++--- 7 files changed, 48 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 9a69fad832cd..e77a68c2fc73 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -284,7 +284,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( intf_cfg.stream_sel = 0; /* Don't care value for video mode */ intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); if (phys_enc->hw_pp->merge_3d) - intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id; + intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, @@ -298,11 +298,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine( true, phys_enc->hw_pp->idx); - if (phys_enc->hw_pp->merge_3d) { - struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d); - - merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d); - } + if (phys_enc->hw_pp->merge_3d) + phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); @@ -461,7 +458,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx); if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d) - ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id); + ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); skip_flush: DPU_DEBUG_VIDENC(phys_enc, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 92cd724263ce..89c1123d957f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -8,6 +8,7 @@ #include "dpu_hwio.h" #include "dpu_hw_catalog.h" #include "dpu_hw_pingpong.h" +#include "dpu_hw_merge3d.h" #include "dpu_kms.h" #include "dpu_trace.h" @@ -263,7 +264,8 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, void __iomem *addr, - const struct dpu_mdss_cfg *m) + const struct dpu_mdss_cfg *m, + struct dpu_hw_merge_3d **merge_3d_blks) { struct dpu_hw_pingpong *c; const struct dpu_pingpong_cfg *cfg; @@ -282,6 +284,9 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, c->caps = cfg; _setup_pingpong_ops(c, c->caps->features); + if (cfg->merge_3d && cfg->merge_3d < MERGE_3D_MAX) + c->merge_3d = merge_3d_blks[cfg->merge_3d - MERGE_3D_0]; + dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx); return c; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index 845b9ce80e31..a9e960b8814b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -133,7 +133,7 @@ struct dpu_hw_pingpong { /* pingpong */ enum dpu_pingpong idx; const struct dpu_pingpong_cfg *caps; - struct dpu_hw_blk *merge_3d; + struct dpu_hw_merge_3d *merge_3d; /* ops */ struct dpu_hw_pingpong_ops ops; @@ -155,11 +155,13 @@ static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw) * @idx: Pingpong index for which driver object is required * @addr: Mapped register io address of MDP * @m: Pointer to mdss catalog data + * @merge_3d_blks: Pointer to merge 3d blocks * Returns: Error code or allocated dpu_hw_pingpong context */ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, void __iomem *addr, - const struct dpu_mdss_cfg *m); + const struct dpu_mdss_cfg *m, + struct dpu_hw_merge_3d **merge_3d_blks); /** * dpu_hw_pingpong_destroy - destroys pingpong driver context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 85f2c3564c96..8e00214426bc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -22,6 +22,7 @@ #include "dpu_kms.h" #include "dpu_core_irq.h" #include "dpu_formats.h" +#include "dpu_hw_merge3d.h" #include "dpu_hw_vbif.h" #include "dpu_vbif.h" #include "dpu_encoder.h" @@ -687,6 +688,16 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) dpu_rm_destroy(&dpu_kms->rm); dpu_kms->rm_init = false; + /* After RM destroy, as PP blocks reference MERGE_3D blocks */ + if (dpu_kms->catalog) { + for (i = 0; i < dpu_kms->catalog->merge_3d_count; i++) { + u32 merge_3d_idx = dpu_kms->catalog->merge_3d[i].id; + + if ((merge_3d_idx < MERGE_3D_MAX) && dpu_kms->hw_merge_3d[merge_3d_idx]) + dpu_hw_merge_3d_destroy(dpu_kms->hw_merge_3d[merge_3d_idx]); + } + } + if (dpu_kms->catalog) dpu_hw_catalog_deinit(dpu_kms->catalog); dpu_kms->catalog = NULL; @@ -962,7 +973,21 @@ static int dpu_kms_hw_init(struct msm_kms *kms) goto power_error; } - rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio); + /* Before RM init so PP blocks can find MERGE_3D blocks */ + for (i = 0; i < dpu_kms->catalog->merge_3d_count; i++) { + u32 merge_3d_idx = dpu_kms->catalog->merge_3d[i].id; + + dpu_kms->hw_merge_3d[i] = dpu_hw_merge_3d_init(merge_3d_idx, + dpu_kms->mmio, dpu_kms->catalog); + if (IS_ERR(dpu_kms->hw_merge_3d[merge_3d_idx])) { + rc = PTR_ERR(dpu_kms->hw_merge_3d[merge_3d_idx]); + DPU_ERROR("failed to init merge_3d %d: %d\n", merge_3d_idx, rc); + dpu_kms->hw_merge_3d[merge_3d_idx] = NULL; + goto power_error; + } + } + + rc = dpu_rm_init(&dpu_kms->rm, dpu_kms); if (rc) { DPU_ERROR("rm init failed: %d\n", rc); goto power_error; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 195a854245fa..057fdf0ca9f4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -123,6 +123,7 @@ struct dpu_kms { bool rm_init; struct dpu_hw_vbif *hw_vbif[VBIF_MAX]; + struct dpu_hw_merge_3d *hw_merge_3d[MERGE_3D_MAX]; struct dpu_hw_mdp *hw_mdp; bool has_danger_ctrl; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index bb03ff8b8c9f..2ddf02eda2e5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -9,7 +9,6 @@ #include "dpu_hw_ctl.h" #include "dpu_hw_pingpong.h" #include "dpu_hw_intf.h" -#include "dpu_hw_merge3d.h" #include "dpu_encoder.h" #include "dpu_trace.h" @@ -50,14 +49,6 @@ int dpu_rm_destroy(struct dpu_rm *rm) dpu_hw_pingpong_destroy(hw); } } - for (i = 0; i < ARRAY_SIZE(rm->merge_3d_blks); i++) { - struct dpu_hw_merge_3d *hw; - - if (rm->merge_3d_blks[i]) { - hw = to_dpu_hw_merge_3d(rm->merge_3d_blks[i]); - dpu_hw_merge_3d_destroy(hw); - } - } for (i = 0; i < ARRAY_SIZE(rm->ctl_blks); i++) { struct dpu_hw_ctl *hw; @@ -79,9 +70,10 @@ int dpu_rm_destroy(struct dpu_rm *rm) } int dpu_rm_init(struct dpu_rm *rm, - struct dpu_mdss_cfg *cat, - void __iomem *mmio) + struct dpu_kms *dpu_kms) { + struct dpu_mdss_cfg *cat = dpu_kms->catalog; + void __iomem *mmio = dpu_kms->mmio; int rc, i; if (!rm || !cat || !mmio) { @@ -93,24 +85,6 @@ int dpu_rm_init(struct dpu_rm *rm, memset(rm, 0, sizeof(*rm)); /* Interrogate HW catalog and create tracking items for hw blocks */ - for (i = 0; i < cat->merge_3d_count; i++) { - struct dpu_hw_merge_3d *hw; - const struct dpu_merge_3d_cfg *merge_3d = &cat->merge_3d[i]; - - if (merge_3d->id < MERGE_3D_0 || merge_3d->id >= MERGE_3D_MAX) { - DPU_ERROR("skip merge_3d %d with invalid id\n", merge_3d->id); - continue; - } - hw = dpu_hw_merge_3d_init(merge_3d->id, mmio, cat); - if (IS_ERR_OR_NULL(hw)) { - rc = PTR_ERR(hw); - DPU_ERROR("failed merge_3d object creation: err %d\n", - rc); - goto fail; - } - rm->merge_3d_blks[merge_3d->id - MERGE_3D_0] = &hw->base; - } - for (i = 0; i < cat->pingpong_count; i++) { struct dpu_hw_pingpong *hw; const struct dpu_pingpong_cfg *pp = &cat->pingpong[i]; @@ -119,15 +93,13 @@ int dpu_rm_init(struct dpu_rm *rm, DPU_ERROR("skip pingpong %d with invalid id\n", pp->id); continue; } - hw = dpu_hw_pingpong_init(pp->id, mmio, cat); + hw = dpu_hw_pingpong_init(pp->id, mmio, cat, dpu_kms->hw_merge_3d); if (IS_ERR_OR_NULL(hw)) { rc = PTR_ERR(hw); DPU_ERROR("failed pingpong object creation: err %d\n", rc); goto fail; } - if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX) - hw->merge_3d = rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]; rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 91952af6c75b..4c0c15453c98 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -27,22 +27,20 @@ struct dpu_rm { struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; - struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; uint32_t lm_max_width; }; +struct dpu_kms; /** * dpu_rm_init - Read hardware catalog and create reservation tracking objects * for all HW blocks. * @rm: DPU Resource Manager handle - * @cat: Pointer to hardware catalog - * @mmio: mapped register io address of MDP + * @dpu_kms: DPU KMS data * @Return: 0 on Success otherwise -ERROR */ int dpu_rm_init(struct dpu_rm *rm, - struct dpu_mdss_cfg *cat, - void __iomem *mmio); + struct dpu_kms *dpu_kms); /** * dpu_rm_destroy - Free all memory allocated by dpu_rm_init From patchwork Wed Mar 24 15:00:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161353 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 997FDC433DB for ; Wed, 24 Mar 2021 15:00:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6266961A0D for ; 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Wed, 24 Mar 2021 08:00:37 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:36 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 06/21] drm/msm/dpu: get PINGPONG blocks directly rather than through RM Date: Wed, 24 Mar 2021 18:00:09 +0300 Message-Id: <20210324150024.2768215-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Each PINGPONG block is tied to a single LM. No LMs can share single PINGPONG block. So there is no need to handle PINGPONG blocks through all resource allocation/deallocation/assignment, just receive PINGPONG block as a part of LM hardware instance. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 12 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 6 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 99 ++----------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 - drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 9 +- 8 files changed, 26 insertions(+), 114 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index b3d50f6d976d..d98b4e4097fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -974,10 +974,9 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, struct drm_crtc *drm_crtc; struct dpu_crtc_state *cstate; struct dpu_global_state *global_state; - struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; - int num_lm, num_ctl, num_pp; + int num_lm, num_ctl; int i, j; if (!drm_enc) { @@ -1020,18 +1019,11 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, break; /* Query resource that have been reserved in atomic check step. */ - num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_PINGPONG, hw_pp, - ARRAY_SIZE(hw_pp)); num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm)); - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) - dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) - : NULL; - cstate = to_dpu_crtc_state(drm_crtc->state); for (i = 0; i < num_lm; i++) { @@ -1040,6 +1032,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]); cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]); cstate->mixers[i].hw_dspp = cstate->mixers[i].hw_lm->dspp; + + dpu_enc->hw_pp[i] = cstate->mixers[i].hw_lm->pingpong; } cstate->num_mixers = num_lm; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 35675744a6b7..fd09b9ab9b4b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -8,6 +8,7 @@ #include "dpu_hw_dspp.h" #include "dpu_hw_lm.h" #include "dpu_hw_mdss.h" +#include "dpu_hw_pingpong.h" #define LM_OP_MODE 0x00 #define LM_OUT_SIZE 0x04 @@ -163,7 +164,8 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void __iomem *addr, - const struct dpu_mdss_cfg *m) + const struct dpu_mdss_cfg *m, + struct dpu_hw_merge_3d **merge_3d_blks) { struct dpu_hw_mixer *c; const struct dpu_lm_cfg *cfg; @@ -185,6 +187,8 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, if (cfg->dspp && cfg->dspp < DSPP_MAX) c->dspp = dpu_hw_dspp_init(cfg->dspp, addr, m); + if (cfg->pingpong && cfg->pingpong < PINGPONG_MAX) + c->pingpong = dpu_hw_pingpong_init(cfg->pingpong, addr, m, merge_3d_blks); dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx); @@ -193,7 +197,9 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) { - if (lm) + if (lm) { dpu_hw_dspp_destroy(lm->dspp); + dpu_hw_pingpong_destroy(lm->pingpong); + } kfree(lm); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h index effb78311a43..182740f2914b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -64,6 +64,7 @@ struct dpu_hw_mixer { const struct dpu_lm_cfg *cap; const struct dpu_mdp_cfg *mdp; const struct dpu_ctl_cfg *ctl; + struct dpu_hw_pingpong *pingpong; struct dpu_hw_dspp *dspp; /* ops */ @@ -83,16 +84,19 @@ static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw) return container_of(hw, struct dpu_hw_mixer, base); } +struct dpu_hw_merge_3d; /** * dpu_hw_lm_init(): Initializes the mixer hw driver object. * should be called once before accessing every mixer. * @idx: mixer index for which driver object is required * @addr: mapped register io address of MDP * @m : pointer to mdss catalog data + * @merge_3d_blks: Pointer to merge 3d blocks */ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void __iomem *addr, - const struct dpu_mdss_cfg *m); + const struct dpu_mdss_cfg *m, + struct dpu_hw_merge_3d **merge_3d_blks); /** * dpu_hw_lm_destroy(): Destroys layer mixer driver context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index a9e960b8814b..a3db536210bf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -149,6 +149,7 @@ static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw) return container_of(hw, struct dpu_hw_pingpong, base); } +struct dpu_rm; /** * dpu_hw_pingpong_init - initializes the pingpong driver for the passed * pingpong idx. diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 057fdf0ca9f4..0b936258bde0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -161,7 +161,6 @@ struct vsync_info { struct dpu_global_state { struct drm_private_state base; - uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0]; uint32_t mixer_to_enc_id[LM_MAX - LM_0]; uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; uint32_t intf_to_enc_id[INTF_MAX - INTF_0]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 2ddf02eda2e5..7792dff60bcd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -7,7 +7,6 @@ #include "dpu_kms.h" #include "dpu_hw_lm.h" #include "dpu_hw_ctl.h" -#include "dpu_hw_pingpong.h" #include "dpu_hw_intf.h" #include "dpu_encoder.h" #include "dpu_trace.h" @@ -41,14 +40,6 @@ int dpu_rm_destroy(struct dpu_rm *rm) dpu_hw_lm_destroy(hw); } } - for (i = 0; i < ARRAY_SIZE(rm->pingpong_blks); i++) { - struct dpu_hw_pingpong *hw; - - if (rm->pingpong_blks[i]) { - hw = to_dpu_hw_pingpong(rm->pingpong_blks[i]); - dpu_hw_pingpong_destroy(hw); - } - } for (i = 0; i < ARRAY_SIZE(rm->ctl_blks); i++) { struct dpu_hw_ctl *hw; @@ -85,24 +76,6 @@ int dpu_rm_init(struct dpu_rm *rm, memset(rm, 0, sizeof(*rm)); /* Interrogate HW catalog and create tracking items for hw blocks */ - for (i = 0; i < cat->pingpong_count; i++) { - struct dpu_hw_pingpong *hw; - const struct dpu_pingpong_cfg *pp = &cat->pingpong[i]; - - if (pp->id < PINGPONG_0 || pp->id >= PINGPONG_MAX) { - DPU_ERROR("skip pingpong %d with invalid id\n", pp->id); - continue; - } - hw = dpu_hw_pingpong_init(pp->id, mmio, cat, dpu_kms->hw_merge_3d); - if (IS_ERR_OR_NULL(hw)) { - rc = PTR_ERR(hw); - DPU_ERROR("failed pingpong object creation: err %d\n", - rc); - goto fail; - } - rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base; - } - for (i = 0; i < cat->intf_count; i++) { struct dpu_hw_intf *hw; const struct dpu_intf_cfg *intf = &cat->intf[i]; @@ -154,7 +127,7 @@ int dpu_rm_init(struct dpu_rm *rm, DPU_ERROR("skip mixer %d with invalid id\n", lm->id); continue; } - hw = dpu_hw_lm_init(lm->id, mmio, cat); + hw = dpu_hw_lm_init(lm->id, mmio, cat, dpu_kms->hw_merge_3d); if (IS_ERR_OR_NULL(hw)) { rc = PTR_ERR(hw); DPU_ERROR("failed lm object creation: err %d\n", rc); @@ -213,53 +186,6 @@ static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx, return true; } -/** - * _dpu_rm_check_lm_and_get_connected_blks - check if proposed layer mixer meets - * proposed use case requirements, incl. hardwired dependent blocks like - * pingpong - * @rm: dpu resource manager handle - * @global_state: resources shared across multiple kms objects - * @enc_id: encoder id requesting for allocation - * @lm_idx: index of proposed layer mixer in rm->mixer_blks[], function checks - * if lm, and all other hardwired blocks connected to the lm (pp) is - * available and appropriate - * @pp_idx: output parameter, index of pingpong block attached to the layer - * mixer in rm->pingpong_blks[]. - * @reqs: input parameter, rm requirements for HW blocks needed in the - * datapath. - * Return: true if lm matches all requirements, false otherwise - */ -static bool _dpu_rm_check_lm_and_get_connected_blks(struct dpu_rm *rm, - struct dpu_global_state *global_state, - uint32_t enc_id, int lm_idx, int *pp_idx, - struct dpu_rm_requirements *reqs) -{ - const struct dpu_lm_cfg *lm_cfg; - int idx; - - /* Already reserved? */ - if (reserved_by_other(global_state->mixer_to_enc_id, lm_idx, enc_id)) { - DPU_DEBUG("lm %d already reserved\n", lm_idx + LM_0); - return false; - } - - lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[lm_idx])->cap; - idx = lm_cfg->pingpong - PINGPONG_0; - if (idx < 0 || idx >= ARRAY_SIZE(rm->pingpong_blks)) { - DPU_ERROR("failed to get pp on lm %d\n", lm_cfg->pingpong); - return false; - } - - if (reserved_by_other(global_state->pingpong_to_enc_id, idx, enc_id)) { - DPU_DEBUG("lm %d pp %d already reserved\n", lm_cfg->id, - lm_cfg->pingpong); - return false; - } - *pp_idx = idx; - - return true; -} - static int _dpu_rm_reserve_lms(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t enc_id, @@ -267,7 +193,6 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, { int lm_idx[MAX_BLOCKS]; - int pp_idx[MAX_BLOCKS]; int i, j, lm_count = 0; if (!reqs->topology.num_lm) { @@ -284,9 +209,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, lm_count = 0; lm_idx[lm_count] = i; - if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, - enc_id, i, &pp_idx[lm_count], - reqs)) { + if (reserved_by_other(global_state->mixer_to_enc_id, i, enc_id)) { + DPU_DEBUG("lm %d already reserved\n", i + LM_0); continue; } @@ -304,10 +228,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, continue; } - if (!_dpu_rm_check_lm_and_get_connected_blks(rm, - global_state, enc_id, j, - &pp_idx[lm_count], - reqs)) { + if (reserved_by_other(global_state->mixer_to_enc_id, j, enc_id)) { + DPU_DEBUG("lm %d already reserved\n", j + LM_0); continue; } @@ -323,10 +245,8 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, for (i = 0; i < lm_count; i++) { global_state->mixer_to_enc_id[lm_idx[i]] = enc_id; - global_state->pingpong_to_enc_id[pp_idx[i]] = enc_id; - trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id, - pp_idx[i] + PINGPONG_0); + trace_dpu_rm_reserve_lms(lm_idx[i] + LM_0, enc_id); } return 0; @@ -492,8 +412,6 @@ static void _dpu_rm_clear_mapping(uint32_t *res_mapping, int cnt, void dpu_rm_release(struct dpu_global_state *global_state, struct drm_encoder *enc) { - _dpu_rm_clear_mapping(global_state->pingpong_to_enc_id, - ARRAY_SIZE(global_state->pingpong_to_enc_id), enc->base.id); _dpu_rm_clear_mapping(global_state->mixer_to_enc_id, ARRAY_SIZE(global_state->mixer_to_enc_id), enc->base.id); _dpu_rm_clear_mapping(global_state->ctl_to_enc_id, @@ -548,11 +466,6 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, int i, num_blks, max_blks; switch (type) { - case DPU_HW_BLK_PINGPONG: - hw_blks = rm->pingpong_blks; - hw_to_enc_id = global_state->pingpong_to_enc_id; - max_blks = ARRAY_SIZE(rm->pingpong_blks); - break; case DPU_HW_BLK_LM: hw_blks = rm->mixer_blks; hw_to_enc_id = global_state->mixer_to_enc_id; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 4c0c15453c98..a618c0ef43db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -15,7 +15,6 @@ struct dpu_global_state; /** * struct dpu_rm - DPU dynamic hardware resource manager - * @pingpong_blks: array of pingpong hardware resources * @mixer_blks: array of layer mixer hardware resources * @ctl_blks: array of ctl hardware resources * @intf_blks: array of intf hardware resources @@ -23,7 +22,6 @@ struct dpu_global_state; * @rm_lock: resource manager mutex */ struct dpu_rm { - struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0]; struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 6714b088970f..23b587b10d77 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -835,20 +835,17 @@ DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls, ); TRACE_EVENT(dpu_rm_reserve_lms, - TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id), - TP_ARGS(id, enc_id, pp_id), + TP_PROTO(uint32_t id, uint32_t enc_id), + TP_ARGS(id, enc_id), TP_STRUCT__entry( __field( uint32_t, id ) __field( uint32_t, enc_id ) - __field( uint32_t, pp_id ) ), TP_fast_assign( __entry->id = id; __entry->enc_id = enc_id; - __entry->pp_id = pp_id; ), - TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id, - __entry->enc_id, __entry->pp_id) + TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id) ); TRACE_EVENT(dpu_vbif_wait_xin_halt_fail, From patchwork Wed Mar 24 15:00:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44BD4C433E1 for ; Wed, 24 Mar 2021 15:00:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 102F761A06 for ; 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Wed, 24 Mar 2021 08:00:39 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:38 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 07/21] drm/msm/dpu: drop unused lm_max_width from RM Date: Wed, 24 Mar 2021 18:00:10 +0300 Message-Id: <20210324150024.2768215-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" No code uses lm_max_width from resource manager, so drop it. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 12 ------------ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 4 ---- 2 files changed, 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 7792dff60bcd..dbcf4929810b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -134,18 +134,6 @@ int dpu_rm_init(struct dpu_rm *rm, goto fail; } rm->mixer_blks[lm->id - LM_0] = &hw->base; - - if (!rm->lm_max_width) { - rm->lm_max_width = lm->sblk->maxwidth; - } else if (rm->lm_max_width != lm->sblk->maxwidth) { - /* - * Don't expect to have hw where lm max widths differ. - * If found, take the min. - */ - DPU_ERROR("unsupported: lm maxwidth differs\n"); - if (rm->lm_max_width > lm->sblk->maxwidth) - rm->lm_max_width = lm->sblk->maxwidth; - } } return 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index a618c0ef43db..3f68a1c0dc1e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -18,15 +18,11 @@ struct dpu_global_state; * @mixer_blks: array of layer mixer hardware resources * @ctl_blks: array of ctl hardware resources * @intf_blks: array of intf hardware resources - * @lm_max_width: cached layer mixer maximum width - * @rm_lock: resource manager mutex */ struct dpu_rm { struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0]; struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0]; struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0]; - - uint32_t lm_max_width; }; struct dpu_kms; From patchwork Wed Mar 24 15:00:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39C0FC433E0 for ; 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Wed, 24 Mar 2021 08:00:40 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:40 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 08/21] drm/msm/dpu: simplify peer LM handling Date: Wed, 24 Mar 2021 18:00:11 +0300 Message-Id: <20210324150024.2768215-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For each LM there is at max 1 peer LM which can be driven by the same CTL, so there no need to have a mask instead of just an ID of the peer LM. Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 30 +++++-------------- 3 files changed, 11 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index e4444452759c..f21f630af476 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -497,7 +497,7 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = { .features = _fmask, \ .sblk = _sblk, \ .pingpong = _pp, \ - .lm_pair_mask = (1 << _lmpair), \ + .lm_pair = _lmpair, \ .dspp = _dspp \ } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index ea4647d21a20..08864f0addc4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -494,14 +494,14 @@ struct dpu_sspp_cfg { * @features bit mask identifying sub-blocks/features * @sblk: LM Sub-blocks information * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported - * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL + * @lm_pair: ID of LM that can be controlled by same CTL */ struct dpu_lm_cfg { DPU_HW_BLK_INFO; const struct dpu_lm_sub_blks *sblk; u32 pingpong; u32 dspp; - unsigned long lm_pair_mask; + unsigned long lm_pair; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index dbcf4929810b..969286c6f104 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -150,28 +150,19 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top) } /** - * _dpu_rm_check_lm_peer - check if a mixer is a peer of the primary + * _dpu_rm_get_lm_peer - get the id of a mixer which is a peer of the primary * @rm: dpu resource manager handle * @primary_idx: index of primary mixer in rm->mixer_blks[] - * @peer_idx: index of other mixer in rm->mixer_blks[] - * Return: true if rm->mixer_blks[peer_idx] is a peer of - * rm->mixer_blks[primary_idx] */ -static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx, - int peer_idx) +static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx) { const struct dpu_lm_cfg *prim_lm_cfg; - const struct dpu_lm_cfg *peer_cfg; prim_lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[primary_idx])->cap; - peer_cfg = to_dpu_hw_mixer(rm->mixer_blks[peer_idx])->cap; - if (!test_bit(peer_cfg->id, &prim_lm_cfg->lm_pair_mask)) { - DPU_DEBUG("lm %d not peer of lm %d\n", peer_cfg->id, - peer_cfg->id); - return false; - } - return true; + if (prim_lm_cfg->lm_pair >= LM_0 && prim_lm_cfg->lm_pair < LM_MAX) + return prim_lm_cfg->lm_pair - LM_0; + return -EINVAL; } static int _dpu_rm_reserve_lms(struct dpu_rm *rm, @@ -205,17 +196,12 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, ++lm_count; /* Valid primary mixer found, find matching peers */ - for (j = i + 1; j < ARRAY_SIZE(rm->mixer_blks) && - lm_count < reqs->topology.num_lm; j++) { + j = _dpu_rm_get_lm_peer(rm, i); + /* ignore the peer if there is an error or if the peer was already processed */ + if (j > i) { if (!rm->mixer_blks[j]) continue; - if (!_dpu_rm_check_lm_peer(rm, i, j)) { - DPU_DEBUG("lm %d not peer of lm %d\n", LM_0 + j, - LM_0 + i); - continue; - } - if (reserved_by_other(global_state->mixer_to_enc_id, j, enc_id)) { DPU_DEBUG("lm %d already reserved\n", j + LM_0); continue; From patchwork Wed Mar 24 15:00:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0FF3C433C1 for ; Wed, 24 Mar 2021 15:00:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7A6FD61A06 for ; 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Wed, 24 Mar 2021 08:00:41 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:41 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 09/21] drm/msm/dpu: drop dpu_encoder_phys's get_hw_resources() callback Date: Wed, 24 Mar 2021 18:00:12 +0300 Message-Id: <20210324150024.2768215-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Drop get_hw_resources() callback, by filling hw resource information using data from dpu_encoder_phys itself. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5 ----- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8 -------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 8 -------- 4 files changed, 1 insertion(+), 23 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index d98b4e4097fb..f80694456fd6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -441,8 +441,7 @@ void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc, for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (phys->ops.get_hw_resources) - phys->ops.get_hw_resources(phys, hw_res); + hw_res->intfs[phys->intf_idx - INTF_0] = phys->intf_mode; } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index f8f25157f635..23493c680231 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -91,9 +91,6 @@ struct dpu_encoder_virt_ops { * @disable: DRM Call. Disable mode. * @atomic_check: DRM Call. Atomic check new DRM state. * @destroy: DRM Call. Destroy and release resources. - * @get_hw_resources: Populate the structure with the hardware - * resources that this phys_enc is using. - * Expect no overlap between phys_encs. * @control_vblank_irq Register/Deregister for VBLANK IRQ * @wait_for_commit_done: Wait for hardware to have flushed the * current pending frames to hardware @@ -129,8 +126,6 @@ struct dpu_encoder_phys_ops { struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state); void (*destroy)(struct dpu_encoder_phys *encoder); - void (*get_hw_resources)(struct dpu_encoder_phys *encoder, - struct dpu_encoder_hw_resources *hw_res); int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable); int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc); int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index b2be39b9144e..adbd59326b99 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -541,13 +541,6 @@ static void dpu_encoder_phys_cmd_destroy(struct dpu_encoder_phys *phys_enc) kfree(cmd_enc); } -static void dpu_encoder_phys_cmd_get_hw_resources( - struct dpu_encoder_phys *phys_enc, - struct dpu_encoder_hw_resources *hw_res) -{ - hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_CMD; -} - static void dpu_encoder_phys_cmd_prepare_for_kickoff( struct dpu_encoder_phys *phys_enc) { @@ -747,7 +740,6 @@ static void dpu_encoder_phys_cmd_init_ops( ops->enable = dpu_encoder_phys_cmd_enable; ops->disable = dpu_encoder_phys_cmd_disable; ops->destroy = dpu_encoder_phys_cmd_destroy; - ops->get_hw_resources = dpu_encoder_phys_cmd_get_hw_resources; ops->control_vblank_irq = dpu_encoder_phys_cmd_control_vblank_irq; ops->wait_for_commit_done = dpu_encoder_phys_cmd_wait_for_commit_done; ops->prepare_for_kickoff = dpu_encoder_phys_cmd_prepare_for_kickoff; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index e77a68c2fc73..b6a004ca3927 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -477,13 +477,6 @@ static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc) kfree(phys_enc); } -static void dpu_encoder_phys_vid_get_hw_resources( - struct dpu_encoder_phys *phys_enc, - struct dpu_encoder_hw_resources *hw_res) -{ - hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO; -} - static int dpu_encoder_phys_vid_wait_for_vblank( struct dpu_encoder_phys *phys_enc) { @@ -663,7 +656,6 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) ops->enable = dpu_encoder_phys_vid_enable; ops->disable = dpu_encoder_phys_vid_disable; ops->destroy = dpu_encoder_phys_vid_destroy; - ops->get_hw_resources = dpu_encoder_phys_vid_get_hw_resources; ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq; ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done; ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank; From patchwork Wed Mar 24 15:00:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D90BC433DB for ; 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Wed, 24 Mar 2021 08:00:42 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:42 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 10/21] drm/msm/dpu: drop dpu_hw_lm_setup_blend_config() Date: Wed, 24 Mar 2021 18:00:13 +0300 Message-Id: <20210324150024.2768215-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" DPU1 driver supports only hardware with the version of 4.0 and higher (>= sdm845), so drop the dpu_hw_lm_setup_blend_config() used by previous hardware generations. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 26 +---------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index fd09b9ab9b4b..7d5b620f7f42 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -23,9 +23,6 @@ #define LM_FG_COLOR_FILL_SIZE 0x10 #define LM_FG_COLOR_FILL_XY 0x14 -#define LM_BLEND0_FG_ALPHA 0x04 -#define LM_BLEND0_BG_ALPHA 0x08 - static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -117,24 +114,6 @@ static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx, DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } -static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, - u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) -{ - struct dpu_hw_blk_reg_map *c = &ctx->hw; - int stage_off; - - if (stage == DPU_STAGE_BASE) - return; - - stage_off = _stage_offset(ctx, stage); - if (WARN_ON(stage_off < 0)) - return; - - DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); - DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); - DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); -} - static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, uint32_t mixer_op_mode) { @@ -154,10 +133,7 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, unsigned long features) { ops->setup_mixer_out = dpu_hw_lm_setup_out; - if (m->hwversion >= DPU_HW_VER_400) - ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; - else - ops->setup_blend_config = dpu_hw_lm_setup_blend_config; + ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; ops->setup_alpha_out = dpu_hw_lm_setup_color3; ops->setup_border_color = dpu_hw_lm_setup_border_color; } From patchwork Wed Mar 24 15:00:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A420C433C1 for ; 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Wed, 24 Mar 2021 08:00:43 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:43 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 11/21] drm/msm/dpu: call hw_lm ops directly Date: Wed, 24 Mar 2021 18:00:14 +0300 Message-Id: <20210324150024.2768215-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace dpu_hw_lm callbacks with direct functions calls. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 19 ++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 59 ++++++++++------------- 3 files changed, 33 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 56eb22554197..5a0a6741a431 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -84,7 +84,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, DPU_BLEND_BG_INV_ALPHA; } - lm->ops.setup_blend_config(lm, pstate->stage, + dpu_hw_lm_setup_blend_config(lm, pstate->stage, 0xFF, 0, blend_op); DPU_DEBUG("format:%s, alpha_en:%u blend_op:0x%x\n", @@ -112,7 +112,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) cfg.out_height = drm_rect_height(lm_roi); cfg.right_mixer = lm_horiz_position++; cfg.flags = 0; - hw_lm->ops.setup_mixer_out(hw_lm, &cfg); + dpu_hw_lm_setup_mixer_out(hw_lm, &cfg); } } @@ -217,7 +217,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) ctl = mixer[i].lm_ctl; lm = mixer[i].hw_lm; - lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); + dpu_hw_lm_setup_alpha_out(lm, mixer[i].mixer_op_mode); mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, mixer[i].hw_lm->idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 7d5b620f7f42..1e95d52180cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -59,7 +59,7 @@ static inline int _stage_offset(struct dpu_hw_mixer *ctx, enum dpu_stage stage) return -EINVAL; } -static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx, +void dpu_hw_lm_setup_mixer_out(struct dpu_hw_mixer *ctx, struct dpu_hw_mixer_cfg *mixer) { struct dpu_hw_blk_reg_map *c = &ctx->hw; @@ -79,7 +79,7 @@ static void dpu_hw_lm_setup_out(struct dpu_hw_mixer *ctx, DPU_REG_WRITE(c, LM_OP_MODE, op_mode); } -static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, +void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, struct dpu_mdss_color *color, u8 border_en) { @@ -95,7 +95,7 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, } } -static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx, +void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) { struct dpu_hw_blk_reg_map *c = &ctx->hw; @@ -114,7 +114,7 @@ static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx, DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } -static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, +void dpu_hw_lm_setup_alpha_out(struct dpu_hw_mixer *ctx, uint32_t mixer_op_mode) { struct dpu_hw_blk_reg_map *c = &ctx->hw; @@ -128,16 +128,6 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx, DPU_REG_WRITE(c, LM_OP_MODE, op_mode); } -static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, - struct dpu_hw_lm_ops *ops, - unsigned long features) -{ - ops->setup_mixer_out = dpu_hw_lm_setup_out; - ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; - ops->setup_alpha_out = dpu_hw_lm_setup_color3; - ops->setup_border_color = dpu_hw_lm_setup_border_color; -} - struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void __iomem *addr, const struct dpu_mdss_cfg *m, @@ -159,7 +149,6 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, /* Assign ops */ c->idx = idx; c->cap = cfg; - _setup_mixer_ops(m, &c->ops, c->cap->features); if (cfg->dspp && cfg->dspp < DSPP_MAX) c->dspp = dpu_hw_dspp_init(cfg->dspp, addr, m); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h index 182740f2914b..a43c1931c5e4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -22,38 +22,34 @@ struct dpu_hw_color3_cfg { u8 keep_fg[DPU_STAGE_MAX]; }; -/** - * - * struct dpu_hw_lm_ops : Interface to the mixer Hw driver functions +/* * Assumption is these functions will be called after clocks are enabled */ -struct dpu_hw_lm_ops { - /* - * Sets up mixer output width and height - * and border color if enabled - */ - void (*setup_mixer_out)(struct dpu_hw_mixer *ctx, - struct dpu_hw_mixer_cfg *cfg); - - /* - * Alpha blending configuration - * for the specified stage - */ - void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage, - uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op); - - /* - * Alpha color component selection from either fg or bg - */ - void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op); - - /** - * setup_border_color : enable/disable border color - */ - void (*setup_border_color)(struct dpu_hw_mixer *ctx, - struct dpu_mdss_color *color, - u8 border_en); -}; +/* + * Sets up mixer output width and height + * and border color if enabled + */ +void dpu_hw_lm_setup_mixer_out(struct dpu_hw_mixer *ctx, + struct dpu_hw_mixer_cfg *cfg); + +/* + * Alpha blending configuration + * for the specified stage + */ +void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, uint32_t stage, + uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op); + +/* + * Alpha color component selection from either fg or bg + */ +void dpu_hw_lm_setup_alpha_out(struct dpu_hw_mixer *ctx, uint32_t mixer_op); + +/** + * setup_border_color : enable/disable border color + */ +void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, + struct dpu_mdss_color *color, + u8 border_en); struct dpu_hw_mixer { struct dpu_hw_blk base; @@ -67,9 +63,6 @@ struct dpu_hw_mixer { struct dpu_hw_pingpong *pingpong; struct dpu_hw_dspp *dspp; - /* ops */ - struct dpu_hw_lm_ops ops; - /* store mixer info specific to display */ struct dpu_hw_mixer_cfg cfg; }; From patchwork Wed Mar 24 15:00:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECBE7C433DB for ; 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Wed, 24 Mar 2021 08:00:44 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:44 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 12/21] drm/msm/dpu: call hw_dspp ops directly Date: Wed, 24 Mar 2021 18:00:15 +0300 Message-Id: <20210324150024.2768215-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace dpu_hw_dspp callbacks with direct functions calls. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 15 ++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h | 19 ++++++------------- 3 files changed, 15 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 5a0a6741a431..bf3048e44001 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -462,14 +462,14 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) ctl = mixer[i].lm_ctl; dspp = mixer[i].hw_dspp; - if (!dspp || !dspp->ops.setup_pcc) + if (!dspp) continue; if (!state->ctm) { - dspp->ops.setup_pcc(dspp, NULL); + dpu_hw_dspp_setup_pcc(dspp, NULL); } else { _dpu_crtc_get_pcc_coeff(state, &cfg); - dspp->ops.setup_pcc(dspp, &cfg); + dpu_hw_dspp_setup_pcc(dspp, &cfg); } mixer[i].flush_mask |= ctl->ops.get_bitmask_dspp(ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c index 977b25968f34..c17f2bf3324f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -22,7 +22,7 @@ #define PCC_BLUE_G_OFF 0x24 #define PCC_BLUE_B_OFF 0x30 -static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx, +void dpu_hw_dspp_setup_pcc(struct dpu_hw_dspp *ctx, struct dpu_hw_pcc_cfg *cfg) { @@ -33,6 +33,11 @@ static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx, return; } + if (!test_bit(DPU_DSPP_PCC, &ctx->cap->features)) { + DRM_ERROR("called for wrong DSPP block\n"); + return; + } + if (!cfg) { DRM_DEBUG_DRIVER("disable pcc feature\n"); DPU_REG_WRITE(&ctx->hw, base, PCC_DIS); @@ -54,13 +59,6 @@ static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx, DPU_REG_WRITE(&ctx->hw, base, PCC_EN); } -static void _setup_dspp_ops(struct dpu_hw_dspp *c, - unsigned long features) -{ - if (test_bit(DPU_DSPP_PCC, &features)) - c->ops.setup_pcc = dpu_setup_dspp_pcc; -} - static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -108,7 +106,6 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, /* Assign ops */ c->idx = idx; c->cap = cfg; - _setup_dspp_ops(c, c->cap->features); dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h index 7fa189cfcb06..e712e3e4c67b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h @@ -36,19 +36,15 @@ struct dpu_hw_pcc_cfg { }; /** - * struct dpu_hw_dspp_ops - interface to the dspp hardware driver functions * Caller must call the init function to get the dspp context for each dspp * Assumption is these functions will be called after clocks are enabled */ -struct dpu_hw_dspp_ops { - /** - * setup_pcc - setup dspp pcc - * @ctx: Pointer to dspp context - * @cfg: Pointer to configuration - */ - void (*setup_pcc)(struct dpu_hw_dspp *ctx, struct dpu_hw_pcc_cfg *cfg); - -}; +/** + * setup_pcc - setup dspp pcc + * @ctx: Pointer to dspp context + * @cfg: Pointer to configuration + */ +void dpu_hw_dspp_setup_pcc(struct dpu_hw_dspp *ctx, struct dpu_hw_pcc_cfg *cfg); /** * struct dpu_hw_dspp - dspp description @@ -65,9 +61,6 @@ struct dpu_hw_dspp { /* dspp */ int idx; const struct dpu_dspp_cfg *cap; - - /* Ops */ - struct dpu_hw_dspp_ops ops; }; /** From patchwork Wed Mar 24 15:00:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 264D1C433DB for ; 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Wed, 24 Mar 2021 08:00:45 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:45 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 13/21] drm/msm/dpu: hw_pp: make setup_dither mandatory Date: Wed, 24 Mar 2021 18:00:16 +0300 Message-Id: <20210324150024.2768215-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" All supported hardware instances feature DPU_PINGPONG_DITHER option, so just mark setup_dither as mandatory rather than optional callback. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 3 +-- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index f80694456fd6..ac03f329491d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -217,9 +217,6 @@ static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bp { struct dpu_hw_dither_cfg dither_cfg = { 0 }; - if (!hw_pp->ops.setup_dither) - return; - switch (bpc) { case 6: dither_cfg.c0_bitdepth = 6; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 89c1123d957f..5c1ce835cf49 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -258,8 +258,7 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; c->ops.get_line_count = dpu_hw_pp_get_line_count; - if (test_bit(DPU_PINGPONG_DITHER, &features)) - c->ops.setup_dither = dpu_hw_pp_setup_dither; + c->ops.setup_dither = dpu_hw_pp_setup_dither; }; struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, From patchwork Wed Mar 24 15:00:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E85A6C433C1 for ; Wed, 24 Mar 2021 15:01:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B42B861A0E for ; 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Wed, 24 Mar 2021 08:00:47 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:46 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 14/21] drm/msm/dpu: call hw_pingpong ops directly Date: Wed, 24 Mar 2021 18:00:17 +0300 Message-Id: <20210324150024.2768215-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace dpu_hw_pingpong callbacks with direct functions calls. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 31 ++--- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 36 ++---- .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 111 ++++++++---------- 4 files changed, 70 insertions(+), 112 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index ac03f329491d..72a3cd08295e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -226,14 +226,14 @@ static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bp dither_cfg.temporal_en = 0; break; default: - hw_pp->ops.setup_dither(hw_pp, NULL); + dpu_hw_pingpong_setup_dither(hw_pp, NULL); return; } memcpy(&dither_cfg.matrix, dither_matrix, sizeof(u32) * DITHER_MATRIX_SZ); - hw_pp->ops.setup_dither(hw_pp, &dither_cfg); + dpu_hw_pingpong_setup_dither(hw_pp, &dither_cfg); } void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index adbd59326b99..0525db90f2c6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -345,12 +345,6 @@ static void dpu_encoder_phys_cmd_tearcheck_config( DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0); - if (!phys_enc->hw_pp->ops.setup_tearcheck || - !phys_enc->hw_pp->ops.enable_tearcheck) { - DPU_DEBUG_CMDENC(cmd_enc, "tearcheck not supported\n"); - return; - } - dpu_kms = phys_enc->dpu_kms; /* @@ -401,8 +395,8 @@ static void dpu_encoder_phys_cmd_tearcheck_config( phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.sync_cfg_height, tc_cfg.sync_threshold_start, tc_cfg.sync_threshold_continue); - phys_enc->hw_pp->ops.setup_tearcheck(phys_enc->hw_pp, &tc_cfg); - phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, tc_enable); + dpu_hw_pingpong_setup_tearcheck(phys_enc->hw_pp, &tc_cfg); + dpu_hw_pingpong_enable_tearcheck(phys_enc->hw_pp, tc_enable); } static void _dpu_encoder_phys_cmd_pingpong_config( @@ -479,11 +473,11 @@ static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) static void _dpu_encoder_phys_cmd_connect_te( struct dpu_encoder_phys *phys_enc, bool enable) { - if (!phys_enc->hw_pp || !phys_enc->hw_pp->ops.connect_external_te) + if (!phys_enc->hw_pp) return; trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable); - phys_enc->hw_pp->ops.connect_external_te(phys_enc->hw_pp, enable); + dpu_hw_pingpong_connect_external_te(phys_enc->hw_pp, enable); } static void dpu_encoder_phys_cmd_prepare_idle_pc( @@ -495,19 +489,13 @@ static void dpu_encoder_phys_cmd_prepare_idle_pc( static int dpu_encoder_phys_cmd_get_line_count( struct dpu_encoder_phys *phys_enc) { - struct dpu_hw_pingpong *hw_pp; - if (!phys_enc->hw_pp) return -EINVAL; if (!dpu_encoder_phys_cmd_is_master(phys_enc)) return -EINVAL; - hw_pp = phys_enc->hw_pp; - if (!hw_pp->ops.get_line_count) - return -EINVAL; - - return hw_pp->ops.get_line_count(hw_pp); + return dpu_hw_pingpong_get_line_count(phys_enc->hw_pp); } static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) @@ -528,8 +516,7 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) return; } - if (phys_enc->hw_pp->ops.enable_tearcheck) - phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false); + dpu_hw_pingpong_enable_tearcheck(phys_enc->hw_pp, false); phys_enc->enable_state = DPU_ENC_DISABLED; } @@ -582,7 +569,7 @@ static bool dpu_encoder_phys_cmd_is_ongoing_pptx( if (!phys_enc) return false; - phys_enc->hw_pp->ops.get_vsync_info(phys_enc->hw_pp, &info); + dpu_hw_pingpong_get_vsync_info(phys_enc->hw_pp, &info); if (info.wr_ptr_line_count > 0 && info.wr_ptr_line_count < phys_enc->cached_mode.vdisplay) return true; @@ -605,7 +592,7 @@ static void dpu_encoder_phys_cmd_prepare_commit( return; /* If autorefresh is already disabled, we have nothing to do */ - if (!phys_enc->hw_pp->ops.get_autorefresh(phys_enc->hw_pp, NULL)) + if (!dpu_hw_pingpong_get_autorefresh(phys_enc->hw_pp, NULL)) return; /* @@ -617,7 +604,7 @@ static void dpu_encoder_phys_cmd_prepare_commit( * 5. Enable TE back */ _dpu_encoder_phys_cmd_connect_te(phys_enc, false); - phys_enc->hw_pp->ops.setup_autorefresh(phys_enc->hw_pp, 0, false); + dpu_hw_pingpong_setup_autorefresh(phys_enc->hw_pp, 0, false); do { udelay(DPU_ENC_MAX_POLL_TIMEOUT_US); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 5c1ce835cf49..9c78dd06188b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -61,7 +61,7 @@ static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp, return ERR_PTR(-EINVAL); } -static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp, +void dpu_hw_pingpong_setup_dither(struct dpu_hw_pingpong *pp, struct dpu_hw_dither_cfg *cfg) { struct dpu_hw_blk_reg_map *c; @@ -92,7 +92,7 @@ static void dpu_hw_pp_setup_dither(struct dpu_hw_pingpong *pp, DPU_REG_WRITE(c, base + PP_DITHER_EN, 1); } -static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp, +int dpu_hw_pingpong_setup_tearcheck(struct dpu_hw_pingpong *pp, struct dpu_hw_tear_check *te) { struct dpu_hw_blk_reg_map *c; @@ -122,7 +122,7 @@ static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp, return 0; } -static void dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp, +void dpu_hw_pingpong_setup_autorefresh(struct dpu_hw_pingpong *pp, u32 frame_count, bool enable) { DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG, @@ -130,13 +130,13 @@ static void dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp, } /* - * dpu_hw_pp_get_autorefresh_config - Get autorefresh config from HW + * dpu_hw_pingpong_get_autorefresh - Get autorefresh config from HW * @pp: DPU pingpong structure * @frame_count: Used to return the current frame count from hw * * Returns: True if autorefresh enabled, false if disabled. */ -static bool dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp, +bool dpu_hw_pingpong_get_autorefresh(struct dpu_hw_pingpong *pp, u32 *frame_count) { u32 val = DPU_REG_READ(&pp->hw, PP_AUTOREFRESH_CONFIG); @@ -145,7 +145,7 @@ static bool dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp, return !!((val & BIT(31)) >> 31); } -static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, +int dpu_hw_pingpong_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, u32 timeout_us) { struct dpu_hw_blk_reg_map *c; @@ -162,7 +162,7 @@ static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, return rc; } -static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable) +int dpu_hw_pingpong_enable_tearcheck(struct dpu_hw_pingpong *pp, bool enable) { struct dpu_hw_blk_reg_map *c; @@ -174,7 +174,7 @@ static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable) return 0; } -static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp, +int dpu_hw_pingpong_connect_external_te(struct dpu_hw_pingpong *pp, bool enable_external_te) { struct dpu_hw_blk_reg_map *c = &pp->hw; @@ -197,7 +197,7 @@ static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp, return orig; } -static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp, +int dpu_hw_pingpong_get_vsync_info(struct dpu_hw_pingpong *pp, struct dpu_hw_pp_vsync_info *info) { struct dpu_hw_blk_reg_map *c; @@ -220,7 +220,7 @@ static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp, return 0; } -static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) +u32 dpu_hw_pingpong_get_line_count(struct dpu_hw_pingpong *pp) { struct dpu_hw_blk_reg_map *c = &pp->hw; u32 height, init; @@ -246,21 +246,6 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) return line; } -static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, - unsigned long features) -{ - c->ops.setup_tearcheck = dpu_hw_pp_setup_te_config; - c->ops.enable_tearcheck = dpu_hw_pp_enable_te; - c->ops.connect_external_te = dpu_hw_pp_connect_external_te; - c->ops.get_vsync_info = dpu_hw_pp_get_vsync_info; - c->ops.setup_autorefresh = dpu_hw_pp_setup_autorefresh_config; - c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config; - c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; - c->ops.get_line_count = dpu_hw_pp_get_line_count; - - c->ops.setup_dither = dpu_hw_pp_setup_dither; -}; - struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, void __iomem *addr, const struct dpu_mdss_cfg *m, @@ -281,7 +266,6 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, c->idx = idx; c->caps = cfg; - _setup_pingpong_ops(c, c->caps->features); if (cfg->merge_3d && cfg->merge_3d < MERGE_3D_MAX) c->merge_3d = merge_3d_blks[cfg->merge_3d - MERGE_3D_0]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index a3db536210bf..78d2fed4c6a3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -56,75 +56,65 @@ struct dpu_hw_dither_cfg { u32 matrix[DITHER_MATRIX_SZ]; }; -/** - * - * struct dpu_hw_pingpong_ops : Interface to the pingpong Hw driver functions +/* * Assumption is these functions will be called after clocks are enabled - * @setup_tearcheck : program tear check values - * @enable_tearcheck : enables tear check - * @get_vsync_info : retries timing info of the panel - * @setup_autorefresh : configure and enable the autorefresh config - * @get_autorefresh : retrieve autorefresh config from hardware - * @setup_dither : function to program the dither hw block - * @get_line_count: obtain current vertical line counter */ -struct dpu_hw_pingpong_ops { - /** - * enables vysnc generation and sets up init value of - * read pointer and programs the tear check cofiguration - */ - int (*setup_tearcheck)(struct dpu_hw_pingpong *pp, - struct dpu_hw_tear_check *cfg); - /** - * enables tear check block - */ - int (*enable_tearcheck)(struct dpu_hw_pingpong *pp, - bool enable); +/** + * enables vysnc generation and sets up init value of + * read pointer and programs the tear check cofiguration + */ +int dpu_hw_pingpong_setup_tearcheck(struct dpu_hw_pingpong *pp, + struct dpu_hw_tear_check *cfg); - /** - * read, modify, write to either set or clear listening to external TE - * @Return: 1 if TE was originally connected, 0 if not, or -ERROR - */ - int (*connect_external_te)(struct dpu_hw_pingpong *pp, - bool enable_external_te); +/** + * enables tear check block + */ +int dpu_hw_pingpong_enable_tearcheck(struct dpu_hw_pingpong *pp, + bool enable); - /** - * provides the programmed and current - * line_count - */ - int (*get_vsync_info)(struct dpu_hw_pingpong *pp, - struct dpu_hw_pp_vsync_info *info); +/** + * read, modify, write to either set or clear listening to external TE + * @Return: 1 if TE was originally connected, 0 if not, or -ERROR + */ +int dpu_hw_pingpong_connect_external_te(struct dpu_hw_pingpong *pp, + bool enable_external_te); - /** - * configure and enable the autorefresh config - */ - void (*setup_autorefresh)(struct dpu_hw_pingpong *pp, - u32 frame_count, bool enable); +/** + * provides the programmed and current + * line_count + */ +int dpu_hw_pingpong_get_vsync_info(struct dpu_hw_pingpong *pp, + struct dpu_hw_pp_vsync_info *info); - /** - * retrieve autorefresh config from hardware - */ - bool (*get_autorefresh)(struct dpu_hw_pingpong *pp, - u32 *frame_count); +/** + * configure and enable the autorefresh config + */ +void dpu_hw_pingpong_setup_autorefresh(struct dpu_hw_pingpong *pp, + u32 frame_count, bool enable); - /** - * poll until write pointer transmission starts - * @Return: 0 on success, -ETIMEDOUT on timeout - */ - int (*poll_timeout_wr_ptr)(struct dpu_hw_pingpong *pp, u32 timeout_us); +/** + * retrieve autorefresh config from hardware + */ +bool dpu_hw_pingpong_get_autorefresh(struct dpu_hw_pingpong *pp, + u32 *frame_count); - /** - * Obtain current vertical line counter - */ - u32 (*get_line_count)(struct dpu_hw_pingpong *pp); +/** + * poll until write pointer transmission starts + * @Return: 0 on success, -ETIMEDOUT on timeout + */ +int dpu_hw_pingpong_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, u32 timeout_us); - /** - * Setup dither matix for pingpong block - */ - void (*setup_dither)(struct dpu_hw_pingpong *pp, - struct dpu_hw_dither_cfg *cfg); -}; +/** + * Obtain current vertical line counter + */ +u32 dpu_hw_pingpong_get_line_count(struct dpu_hw_pingpong *pp); + +/** + * Setup dither matix for pingpong block + */ +void dpu_hw_pingpong_setup_dither(struct dpu_hw_pingpong *pp, + struct dpu_hw_dither_cfg *cfg); struct dpu_hw_pingpong { struct dpu_hw_blk base; @@ -134,9 +124,6 @@ struct dpu_hw_pingpong { enum dpu_pingpong idx; const struct dpu_pingpong_cfg *caps; struct dpu_hw_merge_3d *merge_3d; - - /* ops */ - struct dpu_hw_pingpong_ops ops; }; /** From patchwork Wed Mar 24 15:00:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD70BC433DB for ; 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Wed, 24 Mar 2021 08:00:48 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:47 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 15/21] drm/msm/dpu: call hw_merge_3d ops directly Date: Wed, 24 Mar 2021 18:00:18 +0300 Message-Id: <20210324150024.2768215-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace dpu_hw_merge_3d callbacks with direct functions calls. Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 9 +-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h | 13 ++----------- 3 files changed, 4 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index b6a004ca3927..868bb2f06125 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -299,7 +299,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( phys_enc->hw_pp->idx); if (phys_enc->hw_pp->merge_3d) - phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); + dpu_hw_merge_3d_setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c index 406ba950a066..4f23bd96b6b9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c @@ -35,7 +35,7 @@ static const struct dpu_merge_3d_cfg *_merge_3d_offset(enum dpu_merge_3d idx, return ERR_PTR(-EINVAL); } -static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d, +void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d, enum dpu_3d_blend_mode mode_3d) { struct dpu_hw_blk_reg_map *c; @@ -52,12 +52,6 @@ static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d, } } -static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c, - unsigned long features) -{ - c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode; -}; - struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -77,7 +71,6 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, c->idx = idx; c->caps = cfg; - _setup_merge_3d_ops(c, c->caps->features); dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h index 870bdb14613e..024e8462ef7f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h @@ -12,18 +12,12 @@ struct dpu_hw_merge_3d; -/** - * - * struct dpu_hw_merge_3d_ops : Interface to the merge_3d Hw driver functions +/* * Assumption is these functions will be called after clocks are enabled - * @setup_3d_mode : enable 3D merge */ -struct dpu_hw_merge_3d_ops { - void (*setup_3d_mode)(struct dpu_hw_merge_3d *merge_3d, +void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d, enum dpu_3d_blend_mode mode_3d); -}; - struct dpu_hw_merge_3d { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; @@ -31,9 +25,6 @@ struct dpu_hw_merge_3d { /* merge_3d */ enum dpu_merge_3d idx; const struct dpu_merge_3d_cfg *caps; - - /* ops */ - struct dpu_hw_merge_3d_ops ops; }; /** From patchwork Wed Mar 24 15:00:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADE2BC433E0 for ; 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Wed, 24 Mar 2021 08:00:49 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:49 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 16/21] drm/msm/dpu: call hw_intf ops directly Date: Wed, 24 Mar 2021 18:00:19 +0300 Message-Id: <20210324150024.2768215-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace dpu_hw_intf callbacks with direct functions calls. Signed-off-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 28 +++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 28 ++++------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 49 +++++++++---------- 3 files changed, 38 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 868bb2f06125..e7a30246eb00 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -202,9 +202,6 @@ static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, u32 vfp_fetch_start_vsync_counter = 0; unsigned long lock_flags; - if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch)) - return; - vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing); if (vfp_fetch_lines) { vert_total = get_vertical_total(timing); @@ -220,7 +217,7 @@ static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, vfp_fetch_lines, vfp_fetch_start_vsync_counter); spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f); + dpu_hw_intf_setup_prg_fetch(phys_enc->hw_intf, &f); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); } @@ -253,10 +250,6 @@ static void dpu_encoder_phys_vid_setup_timing_engine( } mode = phys_enc->cached_mode; - if (!phys_enc->hw_intf->ops.setup_timing_gen) { - DPU_ERROR("timing engine setup is not supported\n"); - return; - } DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n"); drm_mode_debug_printmodeline(&mode); @@ -287,13 +280,12 @@ static void dpu_encoder_phys_vid_setup_timing_engine( intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, + dpu_hw_intf_setup_timing_engine(phys_enc->hw_intf, &timing_params, fmt); phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); /* setup which pp blk will connect to this intf */ - if (phys_enc->hw_intf->ops.bind_pingpong_blk) - phys_enc->hw_intf->ops.bind_pingpong_blk( + dpu_hw_intf_bind_pingpong_blk( phys_enc->hw_intf, true, phys_enc->hw_pp->idx); @@ -440,9 +432,6 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) DPU_DEBUG_VIDENC(phys_enc, "\n"); - if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) - return; - dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx); dpu_encoder_phys_vid_setup_timing_engine(phys_enc); @@ -560,16 +549,13 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) return; } - if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) - return; - if (phys_enc->enable_state == DPU_ENC_DISABLED) { DPU_ERROR("already disabled\n"); return; } spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); + dpu_hw_intf_enable_timing_engine(phys_enc->hw_intf, 0); if (dpu_encoder_phys_vid_is_master(phys_enc)) dpu_encoder_phys_inc_pending(phys_enc); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); @@ -608,7 +594,7 @@ static void dpu_encoder_phys_vid_handle_post_kickoff( trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0); spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1); + dpu_hw_intf_enable_timing_engine(phys_enc->hw_intf, 1); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); phys_enc->enable_state = DPU_ENC_ENABLED; } @@ -642,10 +628,10 @@ static int dpu_encoder_phys_vid_get_line_count( if (!dpu_encoder_phys_vid_is_master(phys_enc)) return -EINVAL; - if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) + if (!phys_enc->hw_intf) return -EINVAL; - return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf); + return dpu_hw_intf_get_line_count(phys_enc->hw_intf); } static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 8df75936d906..3988700dcc85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -80,7 +80,7 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, return ERR_PTR(-EINVAL); } -static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, +void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, const struct intf_timing_params *p, const struct dpu_format *fmt) { @@ -197,7 +197,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); } -static void dpu_hw_intf_enable_timing_engine( +void dpu_hw_intf_enable_timing_engine( struct dpu_hw_intf *intf, u8 enable) { @@ -206,7 +206,7 @@ static void dpu_hw_intf_enable_timing_engine( DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); } -static void dpu_hw_intf_setup_prg_fetch( +void dpu_hw_intf_setup_prg_fetch( struct dpu_hw_intf *intf, const struct intf_prog_fetch *fetch) { @@ -230,7 +230,7 @@ static void dpu_hw_intf_setup_prg_fetch( DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); } -static void dpu_hw_intf_bind_pingpong_blk( +void dpu_hw_intf_bind_pingpong_blk( struct dpu_hw_intf *intf, bool enable, const enum dpu_pingpong pp) @@ -238,6 +238,9 @@ static void dpu_hw_intf_bind_pingpong_blk( struct dpu_hw_blk_reg_map *c = &intf->hw; u32 mux_cfg; + if (!test_bit(DPU_INTF_INPUT_CTRL, &intf->cap->features)) + return; + mux_cfg = DPU_REG_READ(c, INTF_MUX); mux_cfg &= ~0xf; @@ -249,7 +252,7 @@ static void dpu_hw_intf_bind_pingpong_blk( DPU_REG_WRITE(c, INTF_MUX, mux_cfg); } -static void dpu_hw_intf_get_status( +void dpu_hw_intf_get_status( struct dpu_hw_intf *intf, struct intf_status *s) { @@ -265,7 +268,7 @@ static void dpu_hw_intf_get_status( } } -static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) +u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) { struct dpu_hw_blk_reg_map *c; @@ -277,18 +280,6 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) return DPU_REG_READ(c, INTF_LINE_COUNT); } -static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, - unsigned long cap) -{ - ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine; - ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; - ops->get_status = dpu_hw_intf_get_status; - ops->enable_timing = dpu_hw_intf_enable_timing_engine; - ops->get_line_count = dpu_hw_intf_get_line_count; - if (cap & BIT(DPU_INTF_INPUT_CTRL)) - ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; -} - struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -313,7 +304,6 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, c->idx = idx; c->cap = cfg; c->mdss = m; - _setup_intf_ops(&c->ops, c->cap->features); dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 0ead64d3f63d..8661571fec67 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -44,37 +44,35 @@ struct intf_status { u32 line_count; /* current line count including blanking */ }; -/** - * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions +/* * Assumption is these functions will be called after clocks are enabled - * @ setup_timing_gen : programs the timing engine - * @ setup_prog_fetch : enables/disables the programmable fetch logic - * @ enable_timing: enable/disable timing engine - * @ get_status: returns if timing engine is enabled or not - * @ get_line_count: reads current vertical line counter - * @bind_pingpong_blk: enable/disable the connection with pingpong which will - * feed pixels to this interface */ -struct dpu_hw_intf_ops { - void (*setup_timing_gen)(struct dpu_hw_intf *intf, - const struct intf_timing_params *p, - const struct dpu_format *fmt); - void (*setup_prg_fetch)(struct dpu_hw_intf *intf, - const struct intf_prog_fetch *fetch); +/* dpu_hw_intf_setup_timing_engine: programs the timing engine */ +void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, + const struct intf_timing_params *p, + const struct dpu_format *fmt); - void (*enable_timing)(struct dpu_hw_intf *intf, - u8 enable); +/* dpu_hw_intf_setup_prg_fetch : enables/disables the programmable fetch logic */ +void dpu_hw_intf_setup_prg_fetch(struct dpu_hw_intf *intf, + const struct intf_prog_fetch *fetch); - void (*get_status)(struct dpu_hw_intf *intf, - struct intf_status *status); +/* dpu_hw_intf_enable_timing_engine: enable/disable timing engine */ +void dpu_hw_intf_enable_timing_engine(struct dpu_hw_intf *intf, + u8 enable); - u32 (*get_line_count)(struct dpu_hw_intf *intf); +/* dpu_hw_intf_get_status: returns if timing engine is enabled or not */ +void dpu_hw_intf_get_status(struct dpu_hw_intf *intf, + struct intf_status *status); - void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, - bool enable, - const enum dpu_pingpong pp); -}; +/* dpu_hw_intf_get_line_count: reads current vertical line counter */ +u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf); + +/* dpu_hw_intf_bind_pingpong_blk: enable/disable the connection with pingpong + * which will feed pixels to this interface */ +void dpu_hw_intf_bind_pingpong_blk(struct dpu_hw_intf *intf, + bool enable, + const enum dpu_pingpong pp); struct dpu_hw_intf { struct dpu_hw_blk base; @@ -84,9 +82,6 @@ struct dpu_hw_intf { enum dpu_intf idx; const struct dpu_intf_cfg *cap; const struct dpu_mdss_cfg *mdss; - - /* ops */ - struct dpu_hw_intf_ops ops; }; /** From patchwork Wed Mar 24 15:00:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4997CC433C1 for ; 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Wed, 24 Mar 2021 08:00:51 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:50 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 17/21] drm/msm/dpu: call hw_top ops directly Date: Wed, 24 Mar 2021 18:00:20 +0300 Message-Id: <20210324150024.2768215-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace dpu_hw_top callbacks with direct functions calls. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 27 +---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 123 +++++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 15 ++- 5 files changed, 79 insertions(+), 109 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 72a3cd08295e..d8574b2e3abc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -505,8 +505,7 @@ void dpu_encoder_helper_split_config( * update. */ if (phys_enc->split_role == ENC_ROLE_SOLO) { - if (hw_mdptop->ops.setup_split_pipe) - hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); + dpu_hw_setup_split_pipe(hw_mdptop, &cfg); return; } @@ -521,8 +520,7 @@ void dpu_encoder_helper_split_config( if (phys_enc->split_role == ENC_ROLE_MASTER) { DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en); - if (hw_mdptop->ops.setup_split_pipe) - hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg); + dpu_hw_setup_split_pipe(hw_mdptop, &cfg); } } @@ -674,8 +672,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, return; } - if (hw_mdptop->ops.setup_vsync_source && - disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { + if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { for (i = 0; i < dpu_enc->num_phys_encs; i++) vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; @@ -685,7 +682,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, else vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; - hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); + dpu_hw_setup_vsync_source(hw_mdptop, &vsync_cfg); } } @@ -1095,10 +1092,8 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc) if (dpu_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort && - dpu_enc->cur_master->hw_mdptop && - dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select) - dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select( - dpu_enc->cur_master->hw_mdptop); + dpu_enc->cur_master->hw_mdptop) + dpu_hw_intf_audio_select(dpu_enc->cur_master->hw_mdptop); _dpu_encoder_update_vsync_source(dpu_enc, &dpu_enc->disp_info); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index dae77d9c2c74..4c213adedcc4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -50,7 +50,7 @@ #define DCE_SEL 0x450 -static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp, +void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp, struct split_pipe_cfg *cfg) { struct dpu_hw_blk_reg_map *c; @@ -88,7 +88,7 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp, DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1); } -static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp, +bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp, enum dpu_clk_ctrl_type clk_ctrl, bool enable) { struct dpu_hw_blk_reg_map *c; @@ -122,7 +122,7 @@ static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp, } -static void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp, +void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp, struct dpu_danger_safe_status *status) { struct dpu_hw_blk_reg_map *c; @@ -151,7 +151,7 @@ static void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp, status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3; } -static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp, +void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp, struct dpu_vsync_source_cfg *cfg) { struct dpu_hw_blk_reg_map *c; @@ -219,7 +219,7 @@ static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp, } } -static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp, +void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp, struct dpu_danger_safe_status *status) { struct dpu_hw_blk_reg_map *c; @@ -248,7 +248,7 @@ static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp, status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1; } -static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp) +void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp) { struct dpu_hw_blk_reg_map *c; @@ -260,17 +260,6 @@ static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp) DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1); } -static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, - unsigned long cap) -{ - ops->setup_split_pipe = dpu_hw_setup_split_pipe; - ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl; - ops->get_danger_status = dpu_hw_get_danger_status; - ops->setup_vsync_source = dpu_hw_setup_vsync_source; - ops->get_safe_status = dpu_hw_get_safe_status; - ops->intf_audio_select = dpu_hw_intf_audio_select; -} - static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -315,12 +304,8 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, return ERR_PTR(-EINVAL); } - /* - * Assign ops - */ mdp->idx = idx; mdp->caps = cfg; - _setup_mdp_ops(&mdp->ops, mdp->caps->features); dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h index 8018fff5667a..6745711bf129 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h @@ -68,70 +68,66 @@ struct dpu_vsync_source_cfg { u32 vsync_source; }; -/** - * struct dpu_hw_mdp_ops - interface to the MDP TOP Hw driver functions +/* * Assumption is these functions will be called after clocks are enabled. - * @setup_split_pipe : Programs the pipe control registers - * @setup_pp_split : Programs the pp split control registers - * @setup_traffic_shaper : programs traffic shaper control */ -struct dpu_hw_mdp_ops { - /** setup_split_pipe() : Regsiters are not double buffered, thisk - * function should be called before timing control enable - * @mdp : mdp top context driver - * @cfg : upper and lower part of pipe configuration - */ - void (*setup_split_pipe)(struct dpu_hw_mdp *mdp, - struct split_pipe_cfg *p); - - /** - * setup_traffic_shaper() : Setup traffic shaper control - * @mdp : mdp top context driver - * @cfg : traffic shaper configuration - */ - void (*setup_traffic_shaper)(struct dpu_hw_mdp *mdp, - struct traffic_shaper_cfg *cfg); - - /** - * setup_clk_force_ctrl - set clock force control - * @mdp: mdp top context driver - * @clk_ctrl: clock to be controlled - * @enable: force on enable - * @return: if the clock is forced-on by this function - */ - bool (*setup_clk_force_ctrl)(struct dpu_hw_mdp *mdp, - enum dpu_clk_ctrl_type clk_ctrl, bool enable); - - /** - * get_danger_status - get danger status - * @mdp: mdp top context driver - * @status: Pointer to danger safe status - */ - void (*get_danger_status)(struct dpu_hw_mdp *mdp, - struct dpu_danger_safe_status *status); - - /** - * setup_vsync_source - setup vsync source configuration details - * @mdp: mdp top context driver - * @cfg: vsync source selection configuration - */ - void (*setup_vsync_source)(struct dpu_hw_mdp *mdp, - struct dpu_vsync_source_cfg *cfg); - - /** - * get_safe_status - get safe status - * @mdp: mdp top context driver - * @status: Pointer to danger safe status - */ - void (*get_safe_status)(struct dpu_hw_mdp *mdp, - struct dpu_danger_safe_status *status); - - /** - * intf_audio_select - select the external interface for audio - * @mdp: mdp top context driver - */ - void (*intf_audio_select)(struct dpu_hw_mdp *mdp); -}; + +/** + * dpu_hw_setup_split_pipe() : Regsiters are not double buffered, thisk + * function should be called before timing control enable + * @mdp : mdp top context driver + * @cfg : upper and lower part of pipe configuration + */ +void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp, + struct split_pipe_cfg *p); + +/** + * dpu_hw_setup_traffic_shaper() : Setup traffic shaper control + * @mdp : mdp top context driver + * @cfg : traffic shaper configuration + */ +void dpu_hw_setup_traffic_shaper(struct dpu_hw_mdp *mdp, + struct traffic_shaper_cfg *cfg); + +/** + * dpu_hw_setup_clk_force_ctrl - set clock force control + * @mdp: mdp top context driver + * @clk_ctrl: clock to be controlled + * @enable: force on enable + * @return: if the clock is forced-on by this function + */ +bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp, + enum dpu_clk_ctrl_type clk_ctrl, bool enable); + +/** + * dpu_hw_get_danger_status - get danger status + * @mdp: mdp top context driver + * @status: Pointer to danger safe status + */ +void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp, + struct dpu_danger_safe_status *status); + +/** + * dpu_hw_setup_vsync_source - setup vsync source configuration details + * @mdp: mdp top context driver + * @cfg: vsync source selection configuration + */ +void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp, + struct dpu_vsync_source_cfg *cfg); + +/** + * dpu_hw_get_safe_status - get safe status + * @mdp: mdp top context driver + * @status: Pointer to danger safe status + */ +void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp, + struct dpu_danger_safe_status *status); + +/** + * dpu_hw_intf_audio_select - select the external interface for audio + * @mdp: mdp top context driver + */ +void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp); struct dpu_hw_mdp { struct dpu_hw_blk base; @@ -140,9 +136,6 @@ struct dpu_hw_mdp { /* top */ enum dpu_mdp idx; const struct dpu_mdp_cfg *caps; - - /* ops */ - struct dpu_hw_mdp_ops ops; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 8e00214426bc..28a52ebe1195 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -67,13 +67,11 @@ static int _dpu_danger_signal_status(struct seq_file *s, pm_runtime_get_sync(&kms->pdev->dev); if (danger_status) { seq_puts(s, "\nDanger signal status:\n"); - if (kms->hw_mdp->ops.get_danger_status) - kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, + dpu_hw_get_danger_status(kms->hw_mdp, &status); } else { seq_puts(s, "\nSafe signal status:\n"); - if (kms->hw_mdp->ops.get_danger_status) - kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, + dpu_hw_get_danger_status(kms->hw_mdp, &status); } pm_runtime_put_sync(&kms->pdev->dev); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c index 7e08f40e7e6f..c9351c69834a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c @@ -168,9 +168,8 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, return; } - if (!mdp->ops.setup_clk_force_ctrl || - !vbif->ops.set_limit_conf || - !vbif->ops.set_halt_ctrl) + if (!vbif->ops.set_limit_conf || + !vbif->ops.set_halt_ctrl) return; /* set write_gather_en for all write clients */ @@ -185,7 +184,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, trace_dpu_perf_set_ot(params->num, params->xin_id, ot_lim, params->vbif_idx); - forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true); + forced_on = dpu_hw_setup_clk_force_ctrl(mdp, params->clk_ctrl, true); vbif->ops.set_limit_conf(vbif, params->xin_id, params->rd, ot_lim); @@ -198,7 +197,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, vbif->ops.set_halt_ctrl(vbif, params->xin_id, false); if (forced_on) - mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false); + dpu_hw_setup_clk_force_ctrl(mdp, params->clk_ctrl, false); } void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, @@ -229,7 +228,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, return; } - if (!vbif->ops.set_qos_remap || !mdp->ops.setup_clk_force_ctrl) { + if (!vbif->ops.set_qos_remap) { DPU_DEBUG("qos remap not supported\n"); return; } @@ -242,7 +241,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, return; } - forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true); + forced_on = dpu_hw_setup_clk_force_ctrl(mdp, params->clk_ctrl, true); for (i = 0; i < qos_tbl->npriority_lvl; i++) { DPU_DEBUG("vbif:%d xin:%d lvl:%d/%d\n", @@ -253,7 +252,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, } if (forced_on) - mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false); + dpu_hw_setup_clk_force_ctrl(mdp, params->clk_ctrl, false); } void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms) From patchwork Wed Mar 24 15:00:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 050D7C433DB for ; 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Wed, 24 Mar 2021 08:00:52 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:51 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 18/21] drm/msm/dpu: hw_vbif: make set_qos_remap mandatory Date: Wed, 24 Mar 2021 18:00:21 +0300 Message-Id: <20210324150024.2768215-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" All supported hardware instances feature DPU_VBIF_QOS_REMAP option, so just mark setup_dither as mandatory rather than optional callback. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c index b757054e1c23..377d5e8ae615 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c @@ -204,8 +204,7 @@ static void _setup_vbif_ops(struct dpu_hw_vbif_ops *ops, ops->get_limit_conf = dpu_hw_get_limit_conf; ops->set_halt_ctrl = dpu_hw_set_halt_ctrl; ops->get_halt_ctrl = dpu_hw_get_halt_ctrl; - if (test_bit(DPU_VBIF_QOS_REMAP, &cap)) - ops->set_qos_remap = dpu_hw_set_qos_remap; + ops->set_qos_remap = dpu_hw_set_qos_remap; ops->set_mem_type = dpu_hw_set_mem_type; ops->clear_errors = dpu_hw_clear_errors; ops->set_write_gather_en = dpu_hw_set_write_gather_en; From patchwork Wed Mar 24 15:00:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C368BC433DB for ; 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Wed, 24 Mar 2021 08:00:53 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:53 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 19/21] drm/msm/dpu: call hw_vbif ops directly Date: Wed, 24 Mar 2021 18:00:22 +0300 Message-Id: <20210324150024.2768215-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace dpu_hw_vbif callbacks with direct functions calls. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 30 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h | 159 ++++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 39 ++--- 3 files changed, 100 insertions(+), 128 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c index 377d5e8ae615..d7d2e7edc0e3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c @@ -32,7 +32,7 @@ #define VBIF_XINL_QOS_RP_REMAP_000 0x0550 #define VBIF_XINL_QOS_LVL_REMAP_000(v) (v < DPU_HW_VER_400 ? 0x570 : 0x0590) -static void dpu_hw_clear_errors(struct dpu_hw_vbif *vbif, +void dpu_hw_vbif_clear_errors(struct dpu_hw_vbif *vbif, u32 *pnd_errors, u32 *src_errors) { struct dpu_hw_blk_reg_map *c; @@ -52,7 +52,7 @@ static void dpu_hw_clear_errors(struct dpu_hw_vbif *vbif, DPU_REG_WRITE(c, VBIF_XIN_CLR_ERR, pnd | src); } -static void dpu_hw_set_mem_type(struct dpu_hw_vbif *vbif, +void dpu_hw_vbif_set_mem_type(struct dpu_hw_vbif *vbif, u32 xin_id, u32 value) { struct dpu_hw_blk_reg_map *c; @@ -82,7 +82,7 @@ static void dpu_hw_set_mem_type(struct dpu_hw_vbif *vbif, DPU_REG_WRITE(c, reg_off, reg_val); } -static void dpu_hw_set_limit_conf(struct dpu_hw_vbif *vbif, +void dpu_hw_vbif_set_limit_conf(struct dpu_hw_vbif *vbif, u32 xin_id, bool rd, u32 limit) { struct dpu_hw_blk_reg_map *c = &vbif->hw; @@ -103,7 +103,7 @@ static void dpu_hw_set_limit_conf(struct dpu_hw_vbif *vbif, DPU_REG_WRITE(c, reg_off, reg_val); } -static u32 dpu_hw_get_limit_conf(struct dpu_hw_vbif *vbif, +u32 dpu_hw_vbif_get_limit_conf(struct dpu_hw_vbif *vbif, u32 xin_id, bool rd) { struct dpu_hw_blk_reg_map *c = &vbif->hw; @@ -125,7 +125,7 @@ static u32 dpu_hw_get_limit_conf(struct dpu_hw_vbif *vbif, return limit; } -static void dpu_hw_set_halt_ctrl(struct dpu_hw_vbif *vbif, +void dpu_hw_vbif_set_halt_ctrl(struct dpu_hw_vbif *vbif, u32 xin_id, bool enable) { struct dpu_hw_blk_reg_map *c = &vbif->hw; @@ -141,7 +141,7 @@ static void dpu_hw_set_halt_ctrl(struct dpu_hw_vbif *vbif, DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val); } -static bool dpu_hw_get_halt_ctrl(struct dpu_hw_vbif *vbif, +bool dpu_hw_vbif_get_halt_ctrl(struct dpu_hw_vbif *vbif, u32 xin_id) { struct dpu_hw_blk_reg_map *c = &vbif->hw; @@ -152,7 +152,7 @@ static bool dpu_hw_get_halt_ctrl(struct dpu_hw_vbif *vbif, return (reg_val & BIT(xin_id)) ? true : false; } -static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif, +void dpu_hw_vbif_set_qos_remap(struct dpu_hw_vbif *vbif, u32 xin_id, u32 level, u32 remap_level) { struct dpu_hw_blk_reg_map *c; @@ -182,7 +182,7 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif, DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl); } -static void dpu_hw_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id) +void dpu_hw_vbif_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id) { struct dpu_hw_blk_reg_map *c; u32 reg_val; @@ -197,19 +197,6 @@ static void dpu_hw_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id) DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val); } -static void _setup_vbif_ops(struct dpu_hw_vbif_ops *ops, - unsigned long cap) -{ - ops->set_limit_conf = dpu_hw_set_limit_conf; - ops->get_limit_conf = dpu_hw_get_limit_conf; - ops->set_halt_ctrl = dpu_hw_set_halt_ctrl; - ops->get_halt_ctrl = dpu_hw_get_halt_ctrl; - ops->set_qos_remap = dpu_hw_set_qos_remap; - ops->set_mem_type = dpu_hw_set_mem_type; - ops->clear_errors = dpu_hw_clear_errors; - ops->set_write_gather_en = dpu_hw_set_write_gather_en; -} - static const struct dpu_vbif_cfg *_top_offset(enum dpu_vbif vbif, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -253,7 +240,6 @@ struct dpu_hw_vbif *dpu_hw_vbif_init(enum dpu_vbif idx, */ c->idx = idx; c->cap = cfg; - _setup_vbif_ops(&c->ops, c->cap->features); /* no need to register sub-range in dpu dbg, dump entire vbif io base */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h index 6417aa28d32c..7a81f0729d9b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h @@ -11,87 +11,85 @@ struct dpu_hw_vbif; -/** - * struct dpu_hw_vbif_ops : Interface to the VBIF hardware driver functions +/* * Assumption is these functions will be called after clocks are enabled */ -struct dpu_hw_vbif_ops { - /** - * set_limit_conf - set transaction limit config - * @vbif: vbif context driver - * @xin_id: client interface identifier - * @rd: true for read limit; false for write limit - * @limit: outstanding transaction limit - */ - void (*set_limit_conf)(struct dpu_hw_vbif *vbif, - u32 xin_id, bool rd, u32 limit); - - /** - * get_limit_conf - get transaction limit config - * @vbif: vbif context driver - * @xin_id: client interface identifier - * @rd: true for read limit; false for write limit - * @return: outstanding transaction limit - */ - u32 (*get_limit_conf)(struct dpu_hw_vbif *vbif, - u32 xin_id, bool rd); - - /** - * set_halt_ctrl - set halt control - * @vbif: vbif context driver - * @xin_id: client interface identifier - * @enable: halt control enable - */ - void (*set_halt_ctrl)(struct dpu_hw_vbif *vbif, - u32 xin_id, bool enable); - - /** - * get_halt_ctrl - get halt control - * @vbif: vbif context driver - * @xin_id: client interface identifier - * @return: halt control enable - */ - bool (*get_halt_ctrl)(struct dpu_hw_vbif *vbif, - u32 xin_id); - - /** - * set_qos_remap - set QoS priority remap - * @vbif: vbif context driver - * @xin_id: client interface identifier - * @level: priority level - * @remap_level: remapped level - */ - void (*set_qos_remap)(struct dpu_hw_vbif *vbif, - u32 xin_id, u32 level, u32 remap_level); - - /** - * set_mem_type - set memory type - * @vbif: vbif context driver - * @xin_id: client interface identifier - * @value: memory type value - */ - void (*set_mem_type)(struct dpu_hw_vbif *vbif, - u32 xin_id, u32 value); - - /** - * clear_errors - clear any vbif errors - * This function clears any detected pending/source errors - * on the VBIF interface, and optionally returns the detected - * error mask(s). - * @vbif: vbif context driver - * @pnd_errors: pointer to pending error reporting variable - * @src_errors: pointer to source error reporting variable - */ - void (*clear_errors)(struct dpu_hw_vbif *vbif, - u32 *pnd_errors, u32 *src_errors); - - /** - * set_write_gather_en - set write_gather enable - * @vbif: vbif context driver - * @xin_id: client interface identifier - */ - void (*set_write_gather_en)(struct dpu_hw_vbif *vbif, u32 xin_id); -}; + +/** + * dpu_hw_vbif_set_limit_conf - set transaction limit config + * @vbif: vbif context driver + * @xin_id: client interface identifier + * @rd: true for read limit; false for write limit + * @limit: outstanding transaction limit + */ +void dpu_hw_vbif_set_limit_conf(struct dpu_hw_vbif *vbif, + u32 xin_id, bool rd, u32 limit); + +/** + * dpu_hw_vbif_get_limit_conf - get transaction limit config + * @vbif: vbif context driver + * @xin_id: client interface identifier + * @rd: true for read limit; false for write limit + * @return: outstanding transaction limit + */ +u32 dpu_hw_vbif_get_limit_conf(struct dpu_hw_vbif *vbif, + u32 xin_id, bool rd); + +/** + * dpu_hw_vbif_set_halt_ctrl - set halt control + * @vbif: vbif context driver + * @xin_id: client interface identifier + * @enable: halt control enable + */ +void dpu_hw_vbif_set_halt_ctrl(struct dpu_hw_vbif *vbif, + u32 xin_id, bool enable); + +/** + * dpu_hw_vbif_get_halt_ctrl - get halt control + * @vbif: vbif context driver + * @xin_id: client interface identifier + * @return: halt control enable + */ +bool dpu_hw_vbif_get_halt_ctrl(struct dpu_hw_vbif *vbif, + u32 xin_id); + +/** + * dpu_hw_vbif_set_qos_remap - set QoS priority remap + * @vbif: vbif context driver + * @xin_id: client interface identifier + * @level: priority level + * @remap_level: remapped level + */ +void dpu_hw_vbif_set_qos_remap(struct dpu_hw_vbif *vbif, + u32 xin_id, u32 level, u32 remap_level); + +/** + * dpu_hw_vbif_set_mem_type - set memory type + * @vbif: vbif context driver + * @xin_id: client interface identifier + * @value: memory type value + */ +void dpu_hw_vbif_set_mem_type(struct dpu_hw_vbif *vbif, + u32 xin_id, u32 value); + +/** + * dpu_hw_vbif_clear_errors - clear any vbif errors + * This function clears any detected pending/source errors + * on the VBIF interface, and optionally returns the detected + * error mask(s). + * @vbif: vbif context driver + * @pnd_errors: pointer to pending error reporting variable + * @src_errors: pointer to source error reporting variable + */ +void dpu_hw_vbif_clear_errors(struct dpu_hw_vbif *vbif, + u32 *pnd_errors, u32 *src_errors); + +/** + * dpu_hw_vbif_set_write_gather_en - set write_gather enable + * @vbif: vbif context driver + * @xin_id: client interface identifier + */ +void dpu_hw_vbif_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id); struct dpu_hw_vbif { /* base */ @@ -100,9 +98,6 @@ struct dpu_hw_vbif { /* vbif */ enum dpu_vbif idx; const struct dpu_vbif_cfg *cap; - - /* ops */ - struct dpu_hw_vbif_ops ops; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c index c9351c69834a..776da9e834a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c @@ -23,18 +23,18 @@ static int _dpu_vbif_wait_for_xin_halt(struct dpu_hw_vbif *vbif, u32 xin_id) bool status; int rc; - if (!vbif || !vbif->cap || !vbif->ops.get_halt_ctrl) { + if (!vbif || !vbif->cap) { DPU_ERROR("invalid arguments vbif %d\n", vbif != NULL); return -EINVAL; } timeout = ktime_add_us(ktime_get(), vbif->cap->xin_halt_timeout); for (;;) { - status = vbif->ops.get_halt_ctrl(vbif, xin_id); + status = dpu_hw_vbif_get_halt_ctrl(vbif, xin_id); if (status) break; if (ktime_compare_safe(ktime_get(), timeout) > 0) { - status = vbif->ops.get_halt_ctrl(vbif, xin_id); + status = dpu_hw_vbif_get_halt_ctrl(vbif, xin_id); break; } usleep_range(501, 1000); @@ -125,8 +125,8 @@ static u32 _dpu_vbif_get_ot_limit(struct dpu_hw_vbif *vbif, /* Modify the limits if the target and the use case requires it */ _dpu_vbif_apply_dynamic_ot_limit(vbif, &ot_lim, params); - if (vbif && vbif->ops.get_limit_conf) { - val = vbif->ops.get_limit_conf(vbif, + if (vbif) { + val = dpu_hw_vbif_get_limit_conf(vbif, params->xin_id, params->rd); if (val == ot_lim) ot_lim = 0; @@ -168,13 +168,9 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, return; } - if (!vbif->ops.set_limit_conf || - !vbif->ops.set_halt_ctrl) - return; - /* set write_gather_en for all write clients */ - if (vbif->ops.set_write_gather_en && !params->rd) - vbif->ops.set_write_gather_en(vbif, params->xin_id); + if (!params->rd) + dpu_hw_vbif_set_write_gather_en(vbif, params->xin_id); ot_lim = _dpu_vbif_get_ot_limit(vbif, params) & 0xFF; @@ -186,15 +182,15 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, forced_on = dpu_hw_setup_clk_force_ctrl(mdp, params->clk_ctrl, true); - vbif->ops.set_limit_conf(vbif, params->xin_id, params->rd, ot_lim); + dpu_hw_vbif_set_limit_conf(vbif, params->xin_id, params->rd, ot_lim); - vbif->ops.set_halt_ctrl(vbif, params->xin_id, true); + dpu_hw_vbif_set_halt_ctrl(vbif, params->xin_id, true); ret = _dpu_vbif_wait_for_xin_halt(vbif, params->xin_id); if (ret) trace_dpu_vbif_wait_xin_halt_fail(vbif->idx, params->xin_id); - vbif->ops.set_halt_ctrl(vbif, params->xin_id, false); + dpu_hw_vbif_set_halt_ctrl(vbif, params->xin_id, false); if (forced_on) dpu_hw_setup_clk_force_ctrl(mdp, params->clk_ctrl, false); @@ -228,11 +224,6 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, return; } - if (!vbif->ops.set_qos_remap) { - DPU_DEBUG("qos remap not supported\n"); - return; - } - qos_tbl = params->is_rt ? &vbif->cap->qos_rt_tbl : &vbif->cap->qos_nrt_tbl; @@ -247,7 +238,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, DPU_DEBUG("vbif:%d xin:%d lvl:%d/%d\n", params->vbif_idx, params->xin_id, i, qos_tbl->priority_lvl[i]); - vbif->ops.set_qos_remap(vbif, params->xin_id, i, + dpu_hw_vbif_set_qos_remap(vbif, params->xin_id, i, qos_tbl->priority_lvl[i]); } @@ -262,8 +253,8 @@ void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms) for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) { vbif = dpu_kms->hw_vbif[i]; - if (vbif && vbif->ops.clear_errors) { - vbif->ops.clear_errors(vbif, &pnd, &src); + if (vbif) { + dpu_hw_vbif_clear_errors(vbif, &pnd, &src); if (pnd || src) { DRM_DEBUG_KMS("VBIF %d: pnd 0x%X, src 0x%X\n", vbif->idx - VBIF_0, pnd, src); @@ -279,9 +270,9 @@ void dpu_vbif_init_memtypes(struct dpu_kms *dpu_kms) for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) { vbif = dpu_kms->hw_vbif[i]; - if (vbif && vbif->cap && vbif->ops.set_mem_type) { + if (vbif && vbif->cap) { for (j = 0; j < vbif->cap->memtype_count; j++) - vbif->ops.set_mem_type( + dpu_hw_vbif_set_mem_type( vbif, j, vbif->cap->memtype[j]); } } From patchwork Wed Mar 24 15:00:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D9ACC433E0 for ; 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Wed, 24 Mar 2021 08:00:55 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:54 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 20/21] drm/msm/dpu: fix smart dma support Date: Wed, 24 Mar 2021 18:00:23 +0300 Message-Id: <20210324150024.2768215-21-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Downstream driver uses dpu->caps->smart_dma_rev to update sspp->cap->features with the bit corresponding to the supported SmartDMA version. Upstream driver does not do this, resulting in SSPP subdriver not enbaling setup_multirect callback. Make SSPP subdriver check global smart_dma_rev to decide if setup_multirect should be enabled. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16 ++++++++++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 +++++---- 3 files changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index f21f630af476..5552f45f818c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -145,7 +145,7 @@ static const struct dpu_caps sdm845_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, + .smart_dma_rev = DPU_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_src_split = true, .has_dim_layer = true, @@ -161,7 +161,7 @@ static const struct dpu_caps sc7180_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x9, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, + .smart_dma_rev = DPU_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_dim_layer = true, .has_idle_pc = true, @@ -173,7 +173,7 @@ static const struct dpu_caps sm8150_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .smart_dma_rev = DPU_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_30, .has_src_split = true, .has_dim_layer = true, @@ -189,7 +189,7 @@ static const struct dpu_caps sm8250_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .smart_dma_rev = DPU_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 08864f0addc4..1202a82918eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -70,6 +70,18 @@ enum { DPU_HW_UBWC_VER_40 = 0x400, }; +/** + * SmartDMA support + * @DPU_SMART_DMA_UNSUPPORTED, SmartDMA not support + * @DPU_SMART_DMA_V1, SmartDMA 1.0 support + * @DPU_SMART_DMA_V2, SmartDMA 2.0 support + */ +enum { + DPU_SMART_DMA_UNSUPPORTED, + DPU_SMART_DMA_V1, + DPU_SMART_DMA_V2, +}; + /** * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe @@ -104,8 +116,6 @@ enum { * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect - * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support - * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec * @DPU_SSPP_CDP Supports client driven prefetch @@ -124,8 +134,6 @@ enum { DPU_SSPP_QOS, DPU_SSPP_QOS_8LVL, DPU_SSPP_EXCL_RECT, - DPU_SSPP_SMART_DMA_V1, - DPU_SSPP_SMART_DMA_V2, DPU_SSPP_TS_PREFILL, DPU_SSPP_TS_PREFILL_REC1, DPU_SSPP_CDP, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 8734a47040aa..4165ff2d7a3c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -647,7 +647,8 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, } static void _setup_layer_ops(struct dpu_hw_pipe *c, - unsigned long features) + unsigned long features, + int smart_dma_rev) { if (test_bit(DPU_SSPP_SRC, &features)) { c->ops.setup_format = dpu_hw_sspp_setup_format; @@ -668,8 +669,8 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c, test_bit(DPU_SSPP_CSC_10BIT, &features)) c->ops.setup_csc = dpu_hw_sspp_setup_csc; - if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || - test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) + if (smart_dma_rev == DPU_SMART_DMA_V1 || + smart_dma_rev == DPU_SMART_DMA_V2) c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) || @@ -731,7 +732,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, hw_pipe->mdp = &catalog->mdp[0]; hw_pipe->idx = idx; hw_pipe->cap = cfg; - _setup_layer_ops(hw_pipe, hw_pipe->cap->features); + _setup_layer_ops(hw_pipe, hw_pipe->cap->features, catalog->caps->smart_dma_rev); dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx); From patchwork Wed Mar 24 15:00:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12161377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C17DC433C1 for ; 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Wed, 24 Mar 2021 08:00:57 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id p5sm252463lfe.154.2021.03.24.08.00.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 08:00:55 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Jonathan Marek Subject: [PATCH 21/21] drm/msm/dpu: call hw_intr ops directly Date: Wed, 24 Mar 2021 18:00:24 +0300 Message-Id: <20210324150024.2768215-22-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace dpu_hw_intr callbacks with direct functions calls. Signed-off-by: Dmitry Baryshkov Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 27 ++- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 36 ++-- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 180 +++++++++--------- 3 files changed, 111 insertions(+), 132 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c index 84ea09d9692f..57c5485c0213 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c @@ -47,7 +47,7 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx) * NOTE: dpu_core_irq_callback_handler is protected by top-level * spinlock, so it is safe to clear any interrupt status here. */ - dpu_kms->hw_intr->ops.clear_intr_status_nolock( + dpu_hw_intr_clear_intr_status_nolock( dpu_kms->hw_intr, irq_idx); } @@ -55,10 +55,10 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx) int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms, enum dpu_intr_type intr_type, u32 instance_idx) { - if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.irq_idx_lookup) + if (!dpu_kms->hw_intr) return -EINVAL; - return dpu_kms->hw_intr->ops.irq_idx_lookup(intr_type, + return dpu_hw_intr_irq_idx_lookup(intr_type, instance_idx); } @@ -89,7 +89,7 @@ static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx) trace_dpu_core_irq_enable_idx(irq_idx, enable_count); if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) { - ret = dpu_kms->hw_intr->ops.enable_irq( + ret = dpu_hw_intr_enable_irq( dpu_kms->hw_intr, irq_idx); if (ret) @@ -152,7 +152,7 @@ static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx) trace_dpu_core_irq_disable_idx(irq_idx, enable_count); if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) { - ret = dpu_kms->hw_intr->ops.disable_irq( + ret = dpu_hw_intr_disable_irq( dpu_kms->hw_intr, irq_idx); if (ret) @@ -185,8 +185,7 @@ int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear) { - if (!dpu_kms->hw_intr || - !dpu_kms->hw_intr->ops.get_interrupt_status) + if (!dpu_kms->hw_intr) return 0; if (irq_idx < 0) { @@ -195,7 +194,7 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear) return 0; } - return dpu_kms->hw_intr->ops.get_interrupt_status(dpu_kms->hw_intr, + return dpu_hw_intr_get_interrupt_status(dpu_kms->hw_intr, irq_idx, clear); } @@ -273,18 +272,18 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx, static void dpu_clear_all_irqs(struct dpu_kms *dpu_kms) { - if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.clear_all_irqs) + if (!dpu_kms->hw_intr) return; - dpu_kms->hw_intr->ops.clear_all_irqs(dpu_kms->hw_intr); + dpu_hw_intr_clear_all_irqs(dpu_kms->hw_intr); } static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms) { - if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.disable_all_irqs) + if (!dpu_kms->hw_intr) return; - dpu_kms->hw_intr->ops.disable_all_irqs(dpu_kms->hw_intr); + dpu_hw_intr_disable_all_irqs(dpu_kms->hw_intr); } #ifdef CONFIG_DEBUG_FS @@ -383,7 +382,7 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) * Individual interrupt status bit will only get stored if it * is enabled. */ - dpu_kms->hw_intr->ops.get_interrupt_statuses(dpu_kms->hw_intr); + dpu_hw_intr_get_interrupt_statuses(dpu_kms->hw_intr); /* * Dispatch to HW driver to handle interrupt lookup that is being @@ -393,7 +392,7 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) * callback, and do the interrupt status clearing once the registered * callback is finished. */ - dpu_kms->hw_intr->ops.dispatch_irqs( + dpu_hw_intr_dispatch_irqs( dpu_kms->hw_intr, dpu_core_irq_callback_handler, dpu_kms); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 5c521de71567..a2db9807b41d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -755,7 +755,7 @@ static const struct dpu_irq_type dpu_irq_map[] = { { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, }; -static int dpu_hw_intr_irqidx_lookup(enum dpu_intr_type intr_type, +int dpu_hw_intr_irq_idx_lookup(enum dpu_intr_type intr_type, u32 instance_idx) { int i; @@ -771,7 +771,7 @@ static int dpu_hw_intr_irqidx_lookup(enum dpu_intr_type intr_type, return -EINVAL; } -static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, +void dpu_hw_intr_dispatch_irqs(struct dpu_hw_intr *intr, void (*cbfunc)(void *, int), void *arg) { @@ -825,7 +825,7 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, if (cbfunc) cbfunc(arg, irq_idx); else - intr->ops.clear_intr_status_nolock( + dpu_hw_intr_clear_intr_status_nolock( intr, irq_idx); /* @@ -839,7 +839,7 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, spin_unlock_irqrestore(&intr->irq_lock, irq_flags); } -static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) +int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) { int reg_idx; unsigned long irq_flags; @@ -886,7 +886,7 @@ static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) return 0; } -static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) +int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) { int reg_idx; const struct dpu_intr_reg *reg; @@ -930,7 +930,7 @@ static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) return 0; } -static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx) +int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx) { unsigned long irq_flags; @@ -949,7 +949,7 @@ static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx) return 0; } -static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr) +int dpu_hw_intr_clear_all_irqs(struct dpu_hw_intr *intr) { int i; @@ -968,7 +968,7 @@ static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr) return 0; } -static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr) +int dpu_hw_intr_disable_all_irqs(struct dpu_hw_intr *intr) { int i; @@ -987,7 +987,7 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr) return 0; } -static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr) +void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr) { int i; u32 enable_mask; @@ -1023,7 +1023,7 @@ static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr) spin_unlock_irqrestore(&intr->irq_lock, irq_flags); } -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, +void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, int irq_idx) { int reg_idx; @@ -1039,7 +1039,7 @@ static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, wmb(); } -static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, +u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, int irq_idx, bool clear) { int reg_idx; @@ -1072,19 +1072,6 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, return intr_status; } -static void __setup_intr_ops(struct dpu_hw_intr_ops *ops) -{ - ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup; - ops->enable_irq = dpu_hw_intr_enable_irq; - ops->disable_irq = dpu_hw_intr_disable_irq; - ops->dispatch_irqs = dpu_hw_intr_dispatch_irq; - ops->clear_all_irqs = dpu_hw_intr_clear_irqs; - ops->disable_all_irqs = dpu_hw_intr_disable_irqs; - ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses; - ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock; - ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status; -} - static void __intr_offset(struct dpu_mdss_cfg *m, void __iomem *addr, struct dpu_hw_blk_reg_map *hw) { @@ -1106,7 +1093,6 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, return ERR_PTR(-ENOMEM); __intr_offset(m, addr, &intr->hw); - __setup_intr_ops(&intr->ops); intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index fc9c98617281..17b0f7a862a5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -77,99 +77,94 @@ enum dpu_intr_type { struct dpu_hw_intr; /** - * Interrupt operations. + * dpu_hw_intr_irq_idx_lookup - Lookup IRQ index on the HW interrupt type + * Used for all irq related ops + * @intr_type: Interrupt type defined in dpu_intr_type + * @instance_idx: HW interrupt block instance + * @return: irq_idx or -EINVAL for lookup fail */ -struct dpu_hw_intr_ops { - /** - * irq_idx_lookup - Lookup IRQ index on the HW interrupt type - * Used for all irq related ops - * @intr_type: Interrupt type defined in dpu_intr_type - * @instance_idx: HW interrupt block instance - * @return: irq_idx or -EINVAL for lookup fail - */ - int (*irq_idx_lookup)( - enum dpu_intr_type intr_type, - u32 instance_idx); - - /** - * enable_irq - Enable IRQ based on lookup IRQ index - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - * @return: 0 for success, otherwise failure - */ - int (*enable_irq)( - struct dpu_hw_intr *intr, - int irq_idx); - - /** - * disable_irq - Disable IRQ based on lookup IRQ index - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - * @return: 0 for success, otherwise failure - */ - int (*disable_irq)( - struct dpu_hw_intr *intr, - int irq_idx); - - /** - * clear_all_irqs - Clears all the interrupts (i.e. acknowledges - * any asserted IRQs). Useful during reset. - * @intr: HW interrupt handle - * @return: 0 for success, otherwise failure - */ - int (*clear_all_irqs)( - struct dpu_hw_intr *intr); - - /** - * disable_all_irqs - Disables all the interrupts. Useful during reset. - * @intr: HW interrupt handle - * @return: 0 for success, otherwise failure - */ - int (*disable_all_irqs)( - struct dpu_hw_intr *intr); - - /** - * dispatch_irqs - IRQ dispatcher will call the given callback - * function when a matching interrupt status bit is - * found in the irq mapping table. - * @intr: HW interrupt handle - * @cbfunc: Callback function pointer - * @arg: Argument to pass back during callback - */ - void (*dispatch_irqs)( - struct dpu_hw_intr *intr, - void (*cbfunc)(void *arg, int irq_idx), - void *arg); - - /** - * get_interrupt_statuses - Gets and store value from all interrupt - * status registers that are currently fired. - * @intr: HW interrupt handle - */ - void (*get_interrupt_statuses)( - struct dpu_hw_intr *intr); - - /** - * clear_intr_status_nolock() - clears the HW interrupts without lock - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - */ - void (*clear_intr_status_nolock)( - struct dpu_hw_intr *intr, - int irq_idx); - - /** - * get_interrupt_status - Gets HW interrupt status, and clear if set, - * based on given lookup IRQ index. - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - * @clear: True to clear irq after read - */ - u32 (*get_interrupt_status)( - struct dpu_hw_intr *intr, - int irq_idx, - bool clear); -}; +int dpu_hw_intr_irq_idx_lookup( + enum dpu_intr_type intr_type, + u32 instance_idx); + +/** + * dpu_hw_intr_enable_irq - Enable IRQ based on lookup IRQ index + * @intr: HW interrupt handle + * @irq_idx: Lookup irq index return from irq_idx_lookup + * @return: 0 for success, otherwise failure + */ +int dpu_hw_intr_enable_irq( + struct dpu_hw_intr *intr, + int irq_idx); + +/** + * dpu_hw_intr_disable_irq - Disable IRQ based on lookup IRQ index + * @intr: HW interrupt handle + * @irq_idx: Lookup irq index return from irq_idx_lookup + * @return: 0 for success, otherwise failure + */ +int dpu_hw_intr_disable_irq( + struct dpu_hw_intr *intr, + int irq_idx); + +/** + * dpu_hw_intr_clear_all_irqs - Clears all the interrupts (i.e. acknowledges + * any asserted IRQs). Useful during reset. + * @intr: HW interrupt handle + * @return: 0 for success, otherwise failure + */ +int dpu_hw_intr_clear_all_irqs( + struct dpu_hw_intr *intr); + +/** + * dpu_hw_intr_disable_all_irqs - Disables all the interrupts. Useful during reset. + * @intr: HW interrupt handle + * @return: 0 for success, otherwise failure + */ +int dpu_hw_intr_disable_all_irqs( + struct dpu_hw_intr *intr); + +/** + * dpu_hw_intr_dispatch_irqs - IRQ dispatcher will call the given callback + * function when a matching interrupt status bit is + * found in the irq mapping table. + * @intr: HW interrupt handle + * @cbfunc: Callback function pointer + * @arg: Argument to pass back during callback + */ +void dpu_hw_intr_dispatch_irqs( + struct dpu_hw_intr *intr, + void dpu_hw_intr_cbfunc(void *arg, int irq_idx), + void *arg); + +/** + * dpu_hw_intr_get_interrupt_statuses - Gets and store value from all interrupt + * status registers that are currently fired. + * @intr: HW interrupt handle + */ +void dpu_hw_intr_get_interrupt_statuses( + struct dpu_hw_intr *intr); + +/** + * dpu_hw_intr_clear_intr_status_nolock() - clears the HW interrupts without lock + * @intr: HW interrupt handle + * @irq_idx: Lookup irq index return from irq_idx_lookup + */ +void dpu_hw_intr_clear_intr_status_nolock( + struct dpu_hw_intr *intr, + int irq_idx); + +/** + * dpu_hw_intr_get_interrupt_status - Gets HW interrupt status, and clear if set, + * based on given lookup IRQ index. + * @intr: HW interrupt handle + * @irq_idx: Lookup irq index return from irq_idx_lookup + * @clear: True to clear irq after read + */ +u32 dpu_hw_intr_get_interrupt_status( + struct dpu_hw_intr *intr, + int irq_idx, + bool clear); /** * struct dpu_hw_intr: hw interrupts handling data structure @@ -182,7 +177,6 @@ struct dpu_hw_intr_ops { */ struct dpu_hw_intr { struct dpu_hw_blk_reg_map hw; - struct dpu_hw_intr_ops ops; u32 *cache_irq_mask; u32 *save_irq_status; u32 irq_idx_tbl_size;