From patchwork Fri Mar 26 19:18:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 12167367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E4D8C433E6 for ; Fri, 26 Mar 2021 19:19:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2969461A21 for ; Fri, 26 Mar 2021 19:19:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229957AbhCZTTV (ORCPT ); Fri, 26 Mar 2021 15:19:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230003AbhCZTTP (ORCPT ); Fri, 26 Mar 2021 15:19:15 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AA2DC0613AA; Fri, 26 Mar 2021 12:19:15 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id bx7so7494312edb.12; Fri, 26 Mar 2021 12:19:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+IPVj252zmGnilvXPoux9mM7JML4v4YjgYWvZk+Qg4U=; b=M65o9wpZ7SLprYx/zb2EPO7FAOIQ/Ty797VhdcmceWkngcB+7pSHLzISYrf3KdX2EJ b1WgI02uIFpufwzhj9kNHii/rU+v5v5Uk5tZjx6JPr9Fiq3pN9PpLn+m4vNnpm5OxxuU xHBzZFYOKyFBldoS+9PRcjknxEhEZNu9Zdzf76CbZJKIqoefGiE7HZTc6QDwG9jDqcyj 24o/euWDynZckw56Wg+ay04JD0waBBOpkjVpV/GLf8KgY+e8gS79+D/wt+SJwNNubbTr 32lfhaXGL6OEmvQ3d16pis2y3VPDfXhqS7bz5e7Ko1JzcVE9sfVV/0Ru3tHDJggRU2h3 aPDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+IPVj252zmGnilvXPoux9mM7JML4v4YjgYWvZk+Qg4U=; b=abhE9fK1blhrdRpYBcYaSfNpeuqcvouXzPI0gRDQiraYvtgO5sE2ajqqRZQBJhiDhi m854HPUS+d1eQ+6kwAnT0bKVWb48HVuoXvMyVbImjxafPBaYLM6iZ5nzgf5DOrulxJYr IQaBwhdEyamPsZDGtKeGSkOwJ/HDUqwatzKg+UYE4+q++6xI+l3GeT6js8NPpT8067vs i22DCYrsghca2o1T9wTeq5A6j4j5RXcD3qJRIOVuIygEkn5XiInCJIZXjqSQc6xQeFsW A2xVceX/XGisfmax91MRSVmSBo35BAkPYqR6lmY92si0PMV7zQBCLmH/0BmI+5J0yc/i nsWg== X-Gm-Message-State: AOAM533Hkwmv1spM9O6xGuV3kfDc0iOv0rmjDMPD29R2ofV3OIa5YYHv UwCAIvL0f/QzIS9RszreHmEjJYLttWs= X-Google-Smtp-Source: ABdhPJyvLnIpJVd3BHSpVbYfUnsyrfxd4BC0VTfFm56gk4m+fLdCqZ59Z2z/T/FPInS7MN7t71wVkg== X-Received: by 2002:aa7:cd54:: with SMTP id v20mr16928005edw.80.1616786353794; Fri, 26 Mar 2021 12:19:13 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id c19sm4739373edu.20.2021.03.26.12.19.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 12:19:13 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Bjorn Helgaas , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 1/6] dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators Date: Fri, 26 Mar 2021 15:18:59 -0400 Message-Id: <20210326191906.43567-2-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210326191906.43567-1-jim2101024@gmail.com> References: <20210326191906.43567-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Similar to the regulator bindings found in "rockchip-pcie-host.txt", this allows optional regulators to be attached and controlled by the PCIe RC driver. That being said, this driver searches in the DT subnode (the EP node, eg pci@0,0) for the regulator property. The use of a regulator property in the pcie EP subnode such as "vpcie12v-supply" depends on a pending pullreq to the pci-bus.yaml file at https://github.com/devicetree-org/dt-schema/pull/54 Signed-off-by: Jim Quinlan --- Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index f90557f6deb8..ea3e6f55e365 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -156,5 +156,11 @@ examples: <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; brcm,enable-ssc; brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; + + pcie-ep@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pci14e4,1688"; + vpcie12v-supply: <&vreg12>; + }; }; }; From patchwork Fri Mar 26 19:19:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 12167365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38E2CC433E1 for ; Fri, 26 Mar 2021 19:19:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E5D5E61A48 for ; Fri, 26 Mar 2021 19:19:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229969AbhCZTTV (ORCPT ); Fri, 26 Mar 2021 15:19:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230026AbhCZTTS (ORCPT ); Fri, 26 Mar 2021 15:19:18 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E053FC0613AA; Fri, 26 Mar 2021 12:19:17 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id dm8so7552923edb.2; Fri, 26 Mar 2021 12:19:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RkZZdk3QudoBe1sAkD0QhbZpJjcwJBNFIhvSYhdMvdI=; b=t+2UyPKsP4XR/NthDhhp2gU0ss4Ahhc+//T5Q4rYs4OpfFjQKmiXpN0Zer11AEr2JL naTyuWHWipdhLqLMfqDGq096qlSta8vKKLqeyGm18uCamymMSIhIzAyugwFCUWIS2cqm eo+J43o4BN743gQqOYOMpwmphYycNfuARBhJaZoP8u4ze1gj9KpzUw0dlg7hSHDW9E6P kofQ9AXLNuVXdUdzqLO7nZKUHDMF0G4O++zdrzOiLGsA0Q9Dp5X5YuN4GWhIdjQ+keNp tEeeE21MSnF4J69MEle1bfMSqt/zhXMc6NeaA1s2VMEm9bHC6/xpuy+HilL2xiFiadJg 9cow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RkZZdk3QudoBe1sAkD0QhbZpJjcwJBNFIhvSYhdMvdI=; b=TG+ZhKguXapBkB5gs3m+JaiO8MmGiKa5296jQEUF2bDokK2aQsgZ/nAdr+MEM0c5qe JoUKQsauIiMdrfN3NLSTfchJLglU/dW3VdxaAheEdnC6dnHCh6xzsfJ+pyi6TC7VuPIb pc90B8HcrDiuPZ83shHXdRMKERepJWuwRwNs7s73QmG2FXtckA8OBm1MzxBfeaCwkPhB 7ml6ihcm8v6fGH539gQOeF6U0uwJJ/lqoeM3YyBWobFLHas4crkpZH1yttZoeG2z3Vuk /KFhuCLOTOxZPHcogixYb5bQCscc6BmvfuCu1+fW0gjpqaSzAI4eflx6Y2oOfGZ3XsSc A5LA== X-Gm-Message-State: AOAM533X5C3iH0uO9db6SlO3eIfw+J4GtIjIGqCuKwhRfu8YP3aCWKyX /Uz1DXTWHCBhsmKdLCfCjLWMQ1RuG10= X-Google-Smtp-Source: ABdhPJzO2bYY91kOKz77RXey8eUwkdUAaGESFQ9o8UhmYKP8qs1zCbp2CmI/zGb/uNvlpFj3o5xHAg== X-Received: by 2002:a05:6402:51cd:: with SMTP id r13mr17089295edd.116.1616786356281; Fri, 26 Mar 2021 12:19:16 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id c19sm4739373edu.20.2021.03.26.12.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 12:19:15 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 2/6] PCI: brcmstb: Add control of EP voltage regulators Date: Fri, 26 Mar 2021 15:19:00 -0400 Message-Id: <20210326191906.43567-3-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210326191906.43567-1-jim2101024@gmail.com> References: <20210326191906.43567-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Control of EP regulators by the RC is needed because of the chicken-and-egg situation: although the regulator is "owned" by the EP and would be best handled on its driver, the EP cannot be discovered and probed unless its regulator is already turned on. Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 90 ++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index e330e6811f0b..b76ec7d9af32 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -169,6 +170,7 @@ #define SSC_STATUS_SSC_MASK 0x400 #define SSC_STATUS_PLL_LOCK_MASK 0x800 #define PCIE_BRCM_MAX_MEMC 3 +#define PCIE_BRCM_MAX_EP_REGULATORS 4 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) @@ -295,8 +297,27 @@ struct brcm_pcie { u32 hw_rev; void (*perst_set)(struct brcm_pcie *pcie, u32 val); void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + struct regulator_bulk_data supplies[PCIE_BRCM_MAX_EP_REGULATORS]; + unsigned int num_supplies; }; +static int brcm_set_regulators(struct brcm_pcie *pcie, bool on) +{ + struct device *dev = pcie->dev; + int ret; + + if (!pcie->num_supplies) + return 0; + if (on) + ret = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); + else + ret = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); + if (ret) + dev_err(dev, "failed to %s EP regulators\n", + on ? "enable" : "disable"); + return ret; +} + /* * This is to convert the size of the inbound "BAR" region to the * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE @@ -1141,16 +1162,63 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) pcie->bridge_sw_init_set(pcie, 1); } +static int brcm_pcie_get_regulators(struct brcm_pcie *pcie) +{ + struct device_node *child, *parent = pcie->np; + const unsigned int max_name_len = 64 + 4; + struct property *pp; + + /* Look for regulator supply property in the EP device subnodes */ + for_each_available_child_of_node(parent, child) { + /* + * Do a santiy test to ensure that this is an EP node + * (e.g. node name: "pci-ep@0,0"). The slot number + * should always be 0 as our controller only has a single + * port. + */ + const char *p = strstr(child->full_name, "@0"); + + if (!p || (p[2] && p[2] != ',')) + continue; + + /* Now look for regulator supply properties */ + for_each_property_of_node(child, pp) { + int i, n = strnlen(pp->name, max_name_len); + + if (n <= 7 || strncmp("-supply", &pp->name[n - 7], 7)) + continue; + + /* Make sure this is not a duplicate */ + for (i = 0; i < pcie->num_supplies; i++) + if (strncmp(pcie->supplies[i].supply, + pp->name, max_name_len) == 0) + continue; + + if (pcie->num_supplies < PCIE_BRCM_MAX_EP_REGULATORS) + pcie->supplies[pcie->num_supplies++].supply = pp->name; + else + dev_warn(pcie->dev, "No room for EP supply %s\n", + pp->name); + } + } + /* + * Get the regulators that the EP devices require. We cannot use + * pcie->dev as the device argument in regulator_bulk_get() since + * it will not find the regulators. Instead, use NULL and the + * regulators are looked up by their name. + */ + return regulator_bulk_get(NULL, pcie->num_supplies, pcie->supplies); +} + static int brcm_pcie_suspend(struct device *dev) { struct brcm_pcie *pcie = dev_get_drvdata(dev); - int ret; brcm_pcie_turn_off(pcie); - ret = brcm_phy_stop(pcie); + brcm_phy_stop(pcie); clk_disable_unprepare(pcie->clk); - return ret; + return brcm_set_regulators(pcie, false); } static int brcm_pcie_resume(struct device *dev) @@ -1163,6 +1231,10 @@ static int brcm_pcie_resume(struct device *dev) base = pcie->base; clk_prepare_enable(pcie->clk); + ret = brcm_set_regulators(pcie, true); + if (ret) + return ret; + ret = brcm_phy_start(pcie); if (ret) goto err; @@ -1199,6 +1271,8 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie) brcm_phy_stop(pcie); reset_control_assert(pcie->rescal); clk_disable_unprepare(pcie->clk); + brcm_set_regulators(pcie, false); + regulator_bulk_free(pcie->num_supplies, pcie->supplies); } static int brcm_pcie_remove(struct platform_device *pdev) @@ -1289,6 +1363,16 @@ static int brcm_pcie_probe(struct platform_device *pdev) return ret; } + ret = brcm_pcie_get_regulators(pcie); + if (ret) { + dev_err(pcie->dev, "failed to get regulators (err=%d)\n", ret); + goto fail; + } + + ret = brcm_set_regulators(pcie, true); + if (ret) + goto fail; + ret = brcm_pcie_setup(pcie); if (ret) goto fail; From patchwork Fri Mar 26 19:19:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 12167369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBE62C433DB for ; Fri, 26 Mar 2021 19:20:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 91B65619C7 for ; Fri, 26 Mar 2021 19:20:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230240AbhCZTTx (ORCPT ); Fri, 26 Mar 2021 15:19:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230152AbhCZTTV (ORCPT ); Fri, 26 Mar 2021 15:19:21 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A72ABC0613AA; Fri, 26 Mar 2021 12:19:20 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id y6so7554606eds.1; Fri, 26 Mar 2021 12:19:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aRGVWfDxNXOJckN8x4iVoENPxOwno7jCXTgCsRiW338=; b=fhc+yzrE/z+CWOtndebBylxn1QIw88dre7bmz0hmlsJ84Sj6NyudXUnUiZxwxUe+he pq15Jcdf43l2ZgzhJ1kWhqGBWyUECV2gUsGB0QgE2lfzC97p7puVbJcQfhDNTSbteNzM 5Jfo+W8RPRE06lMROGyCb9cdAh5Vt9IB6U1TwoFNB7VJ1ybkvZ0usXc/keEvkL/riry8 HcqZeZg4qgD2RBEhJza0BIBtNeNq4k5jqkLmyYnhmCfYWHssD4ZFed+UBKpTFgA4PNjH 5p5hEHRt066Vz95OdG4cO4v8nHNLuJK6cNPeQUO6fbOzjz95R8lfoeET/YB1FRqIVxnZ Kg/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aRGVWfDxNXOJckN8x4iVoENPxOwno7jCXTgCsRiW338=; b=RNq6C2Zc1BoIo6hCVT4c2KAx8QjSu1YmYabDnrZmtJHsCh7GLIejQQSifQ7/NR4iYH N6ch5wMF4zCve4/3nF1rHgDpHemVtb5Z1pfQ0NNSHjGtycgLsKoRzTsL1DdpMm8o6FhP LXOUdWiWIeeocVQ9t7hU/7+j9X0xt77GFUxD2zX59tOrSyR2zkQLY3GKTOn+ZVRfVpeY WSmEbu6AhFFk/7M7PzGVlEu1Cr8NM8u/H81VB1BnpgkMNtXwBmHk1RoqSYfLLehXx9Mm qphuZSKFysycvGlK8pdNPYbrCZA8UCOBE/MYH15eE25pX0G5PjUna3H/lUCe4oBhpfn3 3ztw== X-Gm-Message-State: AOAM532bv2VqsbpVMayPuY5RLBhYTA1Ybgg3mLWAWpx4IT95bo7Uxmwi DBtTyVkIBY/VDg30XPQaT3pe8sK3K/w= X-Google-Smtp-Source: ABdhPJw4elY6W9cfQuMiOKMYTuCL7b1gW0Zn04QBKF0fyxgs+fwH+RuJke3SmnIdGFbDYT8FPRzdZA== X-Received: by 2002:a05:6402:312b:: with SMTP id dd11mr16712199edb.149.1616786358870; Fri, 26 Mar 2021 12:19:18 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id c19sm4739373edu.20.2021.03.26.12.19.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 12:19:18 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 3/6] PCI: brcmstb: Do not turn off regulators if EP can wake up Date: Fri, 26 Mar 2021 15:19:01 -0400 Message-Id: <20210326191906.43567-4-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210326191906.43567-1-jim2101024@gmail.com> References: <20210326191906.43567-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org If any downstream device may wake up during S2/S3 suspend, we do not want to turn off its power when suspending. Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 58 +++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index b76ec7d9af32..89745bb6ada6 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -193,6 +193,7 @@ static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val); static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val); static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val); +static bool brcm_pcie_link_up(struct brcm_pcie *pcie); enum { RGR1_SW_INIT_1, @@ -299,22 +300,65 @@ struct brcm_pcie { void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); struct regulator_bulk_data supplies[PCIE_BRCM_MAX_EP_REGULATORS]; unsigned int num_supplies; + bool ep_wakeup_capable; }; -static int brcm_set_regulators(struct brcm_pcie *pcie, bool on) +static int pci_dev_may_wakeup(struct pci_dev *dev, void *data) { + bool *ret = data; + + if (device_may_wakeup(&dev->dev)) { + *ret = true; + dev_dbg(&dev->dev, "disable cancelled for wake-up device\n"); + } + return (int) *ret; +} + +enum { + TURN_OFF, /* Turn egulators off, unless an EP is wakeup-capable */ + TURN_OFF_ALWAYS, /* Turn Regulators off, no exceptions */ + TURN_ON, /* Turn regulators on, unless pcie->ep_wakeup_capable */ +}; + +static int brcm_set_regulators(struct brcm_pcie *pcie, int how) +{ + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); struct device *dev = pcie->dev; int ret; if (!pcie->num_supplies) return 0; - if (on) + if (how == TURN_ON) { + if (pcie->ep_wakeup_capable) { + /* + * We are resuming from a suspend. In the + * previous suspend we did not disable the power + * supplies, so there is no need to enable them + * (and falsely increase their usage count). + */ + pcie->ep_wakeup_capable = false; + return 0; + } + } else if (how == TURN_OFF) { + /* + * If at least one device on this bus is enabled as a + * wake-up source, do not turn off regulators. + */ + pcie->ep_wakeup_capable = false; + if (bridge->bus && brcm_pcie_link_up(pcie)) { + pci_walk_bus(bridge->bus, pci_dev_may_wakeup, &pcie->ep_wakeup_capable); + if (pcie->ep_wakeup_capable) + return 0; + } + } + + if (how == TURN_ON) ret = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); else ret = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); if (ret) dev_err(dev, "failed to %s EP regulators\n", - on ? "enable" : "disable"); + how == TURN_ON ? "enable" : "disable"); return ret; } @@ -1218,7 +1262,7 @@ static int brcm_pcie_suspend(struct device *dev) brcm_phy_stop(pcie); clk_disable_unprepare(pcie->clk); - return brcm_set_regulators(pcie, false); + return brcm_set_regulators(pcie, TURN_OFF); } static int brcm_pcie_resume(struct device *dev) @@ -1231,7 +1275,7 @@ static int brcm_pcie_resume(struct device *dev) base = pcie->base; clk_prepare_enable(pcie->clk); - ret = brcm_set_regulators(pcie, true); + ret = brcm_set_regulators(pcie, TURN_ON); if (ret) return ret; @@ -1271,7 +1315,7 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie) brcm_phy_stop(pcie); reset_control_assert(pcie->rescal); clk_disable_unprepare(pcie->clk); - brcm_set_regulators(pcie, false); + brcm_set_regulators(pcie, TURN_OFF_ALWAYS); regulator_bulk_free(pcie->num_supplies, pcie->supplies); } @@ -1369,7 +1413,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) goto fail; } - ret = brcm_set_regulators(pcie, true); + ret = brcm_set_regulators(pcie, TURN_ON); if (ret) goto fail; From patchwork Fri Mar 26 19:19:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 12167371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39BDFC433E0 for ; Fri, 26 Mar 2021 19:20:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1FA4C61A13 for ; Fri, 26 Mar 2021 19:20:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230026AbhCZTTx (ORCPT ); Fri, 26 Mar 2021 15:19:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230230AbhCZTTX (ORCPT ); Fri, 26 Mar 2021 15:19:23 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6F4EC0613AA; Fri, 26 Mar 2021 12:19:22 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id bf3so7524732edb.6; Fri, 26 Mar 2021 12:19:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ml2lWLGpOaR2MEq6nedJpA3igERFdLP4LEElGLKkZws=; b=cK8RSpvdKDjYYJfpCu2ltYA9ueBdewUw857Bv0ho2ruAvtG17DBnqm4SdJYlCHuCqS pkRvF2F1vJQ7F0/d6AimMoKDaJaRT5gBe8xNWjh6iLHOA/pnfenJd0EPm4yovbCm8W5s wWMUIG9GBhD+fUB5Xi4ZiMPoZs/4PrriOTHmkMhhGx+IqpnWgvpIFQZnvCKaS1zogxP8 H8XLh27ZWl+LWdNxIwffLSYc1guHW7McbVlaE53rIvGJSnUTdRy+fkZSo5gzWx0PsKzE fscT6tG8dJ5N2Eh+moldHJapqj4aNrFsyDltJEy8TsfY5KfB2WdYiETICqEuAYy2ML6d zu5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ml2lWLGpOaR2MEq6nedJpA3igERFdLP4LEElGLKkZws=; b=LambhKsnV1InDIt7uRtvGpDRgWvfPaCqTrqUHcp3YwhC7nOLM63bzlEiJ5a8zOG1X1 Jep9w0hEVI+bbkjbGvbpyxyn6rWPrGTh6TB9RvHnRCTL+nIQnZvxZXRKATh2Z8htO2+W 7dBB3NXCTg/8WXFlH1YwAFhD0OB4Hegg1DyaqlqY/MziUTh40PLJmlX2Cv32MSouWL7g mHASx97ehPekJ2zEjEF+MDml/fWdycsMvEUaFdHjc+LjKvNkXWb/VC/nWWhvHGOZZZEc Q94iOGsUNIZuHBTq+71OSD0ptDemOVpuwNlsYJJNd/MBQutGL3hkRP8fOiFB2WChB2pE nEWg== X-Gm-Message-State: AOAM533Qryc2N3GKyAG5YdXp7iPCnvj/U/Cg89o7HGFcNTwILgVpWmoW 0YCnSeDY8HHpWS+8+baqBCn724WzuXg= X-Google-Smtp-Source: ABdhPJwzVR1KR1vKMODpCAinj0MQcXxrRz7RUrG5Wj0zhIHZbOzKFSTuIKUO2BCFD8yUJ2HdtOqo2A== X-Received: by 2002:a05:6402:1613:: with SMTP id f19mr17182438edv.222.1616786361397; Fri, 26 Mar 2021 12:19:21 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id c19sm4739373edu.20.2021.03.26.12.19.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 12:19:20 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 4/6] PCI: brcmstb: Give 7216 SOCs their own config type Date: Fri, 26 Mar 2021 15:19:02 -0400 Message-Id: <20210326191906.43567-5-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210326191906.43567-1-jim2101024@gmail.com> References: <20210326191906.43567-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This distinction is required for an imminent commit. Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 89745bb6ada6..9c8b922a9c19 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -260,6 +260,13 @@ static const struct pcie_cfg_data bcm2711_cfg = { .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic, }; +static const struct pcie_cfg_data bcm7216_cfg = { + .offsets = pcie_offset_bcm7278, + .type = BCM7278, + .perst_set = brcm_pcie_perst_set_7278, + .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, +}; + struct brcm_msi { struct device *dev; void __iomem *base; @@ -1336,7 +1343,7 @@ static const struct of_device_id brcm_pcie_match[] = { { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg }, { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg }, { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg }, - { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg }, + { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg }, { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg }, {}, }; From patchwork Fri Mar 26 19:19:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 12167375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB4AEC433E1 for ; Fri, 26 Mar 2021 19:20:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8AAED61A28 for ; Fri, 26 Mar 2021 19:20:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230253AbhCZTTy (ORCPT ); Fri, 26 Mar 2021 15:19:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230233AbhCZTT0 (ORCPT ); Fri, 26 Mar 2021 15:19:26 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A33BAC0613AA; Fri, 26 Mar 2021 12:19:25 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id ce10so10026719ejb.6; Fri, 26 Mar 2021 12:19:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CbOru8HTziHXx1MOScCCzN/4ropTyOGA7gdkEVgE5CE=; b=BgT/cgeQZtEA/L1Vl5Tk7R2gJflM0DZ1BuziI0EsBWvMLrznNaNS9IMeAMbyUVPmUT a+9QDxdt9M3lxNg44aUhh2NM/UricSVPLpsKUZo2PsrEEHtO5vneBVL7Fj0FeQfunMXX Dy5j+tffa9SVVGlvTQ9z0df6Rv9QWFTfyFKd9ctKfehj2yNBAHFNStor/E/3IdVbIP40 VZ0JzOVRpx9ZIjYK9i4qavdOvQd0vC3IGuMkM0m94KI0UU/yUa2TFA7ggqqWIjuwweaH RSCb4AMceMO6PUaA7EOOe9LacjjBMUFO4p4fN5E58pVFqifKNkN9weAKbaGTwrvk+Hof nxeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CbOru8HTziHXx1MOScCCzN/4ropTyOGA7gdkEVgE5CE=; b=FF18gGPbYRbq95xHqRnhNi7yxNUkHp0edJcgRxqjY8rwLbJiDGF3fsmu5t9fH66Psv Uf9dEOrNOhltEI+grKrd1xzbzrLaSd/aHLNwLCkuP7WnsS/XkQfS7diNAZbAlroT4eR/ e+Dz4XLH8RlWTDoeYytbHBeMgfZyu4+TJOuuwyEX9y6EYXBsafgyZ/Jr4gMeUVdhdNN+ HXIaHXWYxytqUEJa1A/5CeMtCheeVf/WSJ5ONPJBMwnbHL236W3SrTYZLcGzMP2h5I2U +CJX8yU63IDPa0REK+eQExf6BYCubpFLiicFKr+8l25FUm3gEAsjYgHMOkMIy9mLgb0p 2GgQ== X-Gm-Message-State: AOAM533RJY7uV3PNM4coioH8kwNyKZrIvDW/+KdZIdw+JaHTsygoRntz hrbDSeX1uzjMjzwc3qn1kdFK2Kq3nU4= X-Google-Smtp-Source: ABdhPJylcnOdwMTEDieBQCrlVk1jxkYpeaxbCkr9A0j8aCEsFFD66b2Jn6eFCbcmX0m4HopdUBdGkg== X-Received: by 2002:a17:906:7c44:: with SMTP id g4mr16897137ejp.269.1616786363981; Fri, 26 Mar 2021 12:19:23 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id c19sm4739373edu.20.2021.03.26.12.19.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 12:19:23 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 5/6] PCI: brcmstb: Add panic/die handler to RC driver Date: Fri, 26 Mar 2021 15:19:03 -0400 Message-Id: <20210326191906.43567-6-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210326191906.43567-1-jim2101024@gmail.com> References: <20210326191906.43567-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Whereas most PCIe HW returns 0xffffffff on illegal accesses and the like, by default Broadcom's STB PCIe controller effects an abort. This simple handler determines if the PCIe controller was the cause of the abort and if so, prints out diagnostic info. Example output: brcm-pcie 8b20000.pcie: Error: Mem Acc: 32bit, Read, @0x38000000 brcm-pcie 8b20000.pcie: Type: TO=0 Abt=0 UnspReq=1 AccDsble=0 BadAddr=0 Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 122 ++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 9c8b922a9c19..2d9288399014 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -12,11 +12,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -186,6 +188,39 @@ #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0 +/* Error report regiseters */ +#define PCIE_OUTB_ERR_TREAT 0x6000 +#define PCIE_OUTB_ERR_TREAT_CONFIG_MASK 0x1 +#define PCIE_OUTB_ERR_TREAT_MEM_MASK 0x2 +#define PCIE_OUTB_ERR_VALID 0x6004 +#define PCIE_OUTB_ERR_CLEAR 0x6008 +#define PCIE_OUTB_ERR_ACC_INFO 0x600c +#define PCIE_OUTB_ERR_ACC_INFO_CFG_ERR_MASK 0x01 +#define PCIE_OUTB_ERR_ACC_INFO_MEM_ERR_MASK 0x02 +#define PCIE_OUTB_ERR_ACC_INFO_TYPE_64_MASK 0x04 +#define PCIE_OUTB_ERR_ACC_INFO_DIR_WRITE_MASK 0x10 +#define PCIE_OUTB_ERR_ACC_INFO_BYTE_LANES_MASK 0xff00 +#define PCIE_OUTB_ERR_ACC_ADDR 0x6010 +#define PCIE_OUTB_ERR_ACC_ADDR_BUS_MASK 0xff00000 +#define PCIE_OUTB_ERR_ACC_ADDR_DEV_MASK 0xf8000 +#define PCIE_OUTB_ERR_ACC_ADDR_FUNC_MASK 0x7000 +#define PCIE_OUTB_ERR_ACC_ADDR_REG_MASK 0xfff +#define PCIE_OUTB_ERR_CFG_CAUSE 0x6014 +#define PCIE_OUTB_ERR_CFG_CAUSE_TIMEOUT_MASK 0x40 +#define PCIE_OUTB_ERR_CFG_CAUSE_ABORT_MASK 0x20 +#define PCIE_OUTB_ERR_CFG_CAUSE_UNSUPP_REQ_MASK 0x10 +#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_TIMEOUT_MASK 0x4 +#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_DISABLED_MASK 0x2 +#define PCIE_OUTB_ERR_CFG_CAUSE_ACC_64BIT__MASK 0x1 +#define PCIE_OUTB_ERR_MEM_ADDR_LO 0x6018 +#define PCIE_OUTB_ERR_MEM_ADDR_HI 0x601c +#define PCIE_OUTB_ERR_MEM_CAUSE 0x6020 +#define PCIE_OUTB_ERR_MEM_CAUSE_TIMEOUT_MASK 0x40 +#define PCIE_OUTB_ERR_MEM_CAUSE_ABORT_MASK 0x20 +#define PCIE_OUTB_ERR_MEM_CAUSE_UNSUPP_REQ_MASK 0x10 +#define PCIE_OUTB_ERR_MEM_CAUSE_ACC_DISABLED_MASK 0x2 +#define PCIE_OUTB_ERR_MEM_CAUSE_BAD_ADDR_MASK 0x1 + /* Forward declarations */ struct brcm_pcie; static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val); @@ -218,6 +253,7 @@ struct pcie_cfg_data { const enum pcie_type type; void (*perst_set)(struct brcm_pcie *pcie, u32 val); void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val); + const bool has_err_report; }; static const int pcie_offsets[] = { @@ -265,6 +301,7 @@ static const struct pcie_cfg_data bcm7216_cfg = { .type = BCM7278, .perst_set = brcm_pcie_perst_set_7278, .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278, + .has_err_report = true, }; struct brcm_msi { @@ -308,8 +345,87 @@ struct brcm_pcie { struct regulator_bulk_data supplies[PCIE_BRCM_MAX_EP_REGULATORS]; unsigned int num_supplies; bool ep_wakeup_capable; + bool has_err_report; + struct notifier_block die_notifier; }; +/* Dump out PCIe errors on die or panic */ +static int dump_pcie_error(struct notifier_block *self, unsigned long v, void *p) +{ + const struct brcm_pcie *pcie = container_of(self, struct brcm_pcie, die_notifier); + void __iomem *base = pcie->base; + int i, is_cfg_err, is_mem_err, lanes; + char *width_str, *direction_str, lanes_str[9]; + u32 info; + + if (readl(base + PCIE_OUTB_ERR_VALID) == 0) + return NOTIFY_DONE; + info = readl(base + PCIE_OUTB_ERR_ACC_INFO); + + + is_cfg_err = !!(info & PCIE_OUTB_ERR_ACC_INFO_CFG_ERR_MASK); + is_mem_err = !!(info & PCIE_OUTB_ERR_ACC_INFO_MEM_ERR_MASK); + width_str = (info & PCIE_OUTB_ERR_ACC_INFO_TYPE_64_MASK) ? "64bit" : "32bit"; + direction_str = (info & PCIE_OUTB_ERR_ACC_INFO_DIR_WRITE_MASK) ? "Write" : "Read"; + lanes = FIELD_GET(PCIE_OUTB_ERR_ACC_INFO_BYTE_LANES_MASK, info); + for (i = 0, lanes_str[8] = 0; i < 8; i++) + lanes_str[i] = (lanes & (1 << i)) ? '1' : '0'; + + if (is_cfg_err) { + u32 cfg_addr = readl(base + PCIE_OUTB_ERR_ACC_ADDR); + u32 cause = readl(base + PCIE_OUTB_ERR_CFG_CAUSE); + int bus = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_BUS_MASK, cfg_addr); + int dev = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_DEV_MASK, cfg_addr); + int func = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_FUNC_MASK, cfg_addr); + int reg = FIELD_GET(PCIE_OUTB_ERR_ACC_ADDR_REG_MASK, cfg_addr); + + dev_err(pcie->dev, "Error: CFG Acc, %s, %s, Bus=%d, Dev=%d, Fun=%d, Reg=0x%x, lanes=%s\n", + width_str, direction_str, bus, dev, func, reg, lanes_str); + dev_err(pcie->dev, " Type: TO=%d Abt=%d UnsupReq=%d AccTO=%d AccDsbld=%d Acc64bit=%d\n", + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_TIMEOUT_MASK), + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_ABORT_MASK), + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_UNSUPP_REQ_MASK), + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_TIMEOUT_MASK), + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_DISABLED_MASK), + !!(cause & PCIE_OUTB_ERR_CFG_CAUSE_ACC_64BIT__MASK)); + } + + if (is_mem_err) { + u32 cause = readl(base + PCIE_OUTB_ERR_MEM_CAUSE); + u32 lo = readl(base + PCIE_OUTB_ERR_MEM_ADDR_LO); + u32 hi = readl(base + PCIE_OUTB_ERR_MEM_ADDR_HI); + u64 addr = ((u64)hi << 32) | (u64)lo; + + dev_err(pcie->dev, "Error: Mem Acc, %s, %s, @0x%llx, lanes=%s\n", + width_str, direction_str, addr, lanes_str); + dev_err(pcie->dev, " Type: TO=%d Abt=%d UnsupReq=%d AccDsble=%d BadAddr=%d\n", + !!(cause & PCIE_OUTB_ERR_MEM_CAUSE_TIMEOUT_MASK), + !!(cause & PCIE_OUTB_ERR_MEM_CAUSE_ABORT_MASK), + !!(cause & PCIE_OUTB_ERR_MEM_CAUSE_UNSUPP_REQ_MASK), + !!(cause & PCIE_OUTB_ERR_MEM_CAUSE_ACC_DISABLED_MASK), + !!(cause & PCIE_OUTB_ERR_MEM_CAUSE_BAD_ADDR_MASK)); + } + + /* Clear the error */ + writel(1, base + PCIE_OUTB_ERR_CLEAR); + + return NOTIFY_DONE; +} + +static void brcm_register_die_notifiers(struct brcm_pcie *pcie) +{ + pcie->die_notifier.notifier_call = dump_pcie_error; + register_die_notifier(&pcie->die_notifier); + atomic_notifier_chain_register(&panic_notifier_list, &pcie->die_notifier); +} + +static void brcm_unregister_die_notifiers(struct brcm_pcie *pcie) +{ + unregister_die_notifier(&pcie->die_notifier); + atomic_notifier_chain_unregister(&panic_notifier_list, &pcie->die_notifier); + pcie->die_notifier.notifier_call = NULL; +} + static int pci_dev_may_wakeup(struct pci_dev *dev, void *data) { bool *ret = data; @@ -1332,6 +1448,8 @@ static int brcm_pcie_remove(struct platform_device *pdev) struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); pci_stop_root_bus(bridge->bus); + if (pcie->has_err_report) + brcm_unregister_die_notifiers(pcie); pci_remove_root_bus(bridge->bus); __brcm_pcie_remove(pcie); @@ -1371,6 +1489,7 @@ static int brcm_pcie_probe(struct platform_device *pdev) pcie->np = np; pcie->reg_offsets = data->offsets; pcie->type = data->type; + pcie->has_err_report = data->has_err_report; pcie->perst_set = data->perst_set; pcie->bridge_sw_init_set = data->bridge_sw_init_set; @@ -1448,6 +1567,9 @@ static int brcm_pcie_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + if (pcie->has_err_report) + brcm_register_die_notifiers(pcie); + return pci_host_probe(bridge); fail: __brcm_pcie_remove(pcie); From patchwork Fri Mar 26 19:19:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 12167373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 691CEC433C1 for ; Fri, 26 Mar 2021 19:20:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A1CC61A21 for ; Fri, 26 Mar 2021 19:20:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230261AbhCZTTy (ORCPT ); Fri, 26 Mar 2021 15:19:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230236AbhCZTT2 (ORCPT ); Fri, 26 Mar 2021 15:19:28 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F7A4C0613AA; Fri, 26 Mar 2021 12:19:28 -0700 (PDT) Received: by mail-ed1-x531.google.com with SMTP id dm8so7553466edb.2; Fri, 26 Mar 2021 12:19:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=M/9AAleVmFAMrayfO8gflHwlnHawghg4IbNPiAHidSA=; b=BwBmdNMkYjWREZoEW6Qw+pyNmX+4hg+o4WGSPNdGSW0EzAqFPTHSTsEsjj+uuTuzoZ 5GWuW3AMy3aGoyG+U1a+mB0O1ZSyw7GI3HDnng82EBqU73XwuYOqadvIiPZBKwkbjoaA 7BLqBrRFOGP4VxorPBbLEy3xdhHIM8wNz+BX8oEumvLEYmgK1MlzLAuwHSGi7wbIlG2i 2Od8/TXTQKRJ1Naazh+NjXkNBzog88Y7LyYyBif3ZOfFidCd0YfdSow5cxYaxcfLTkhF Q3K/KarVpbSVzhqtC9aZd/28a/xGLfBjgGvjfLGl768qDvf6gB2/p4oL6VQlvuEdpcKd xfjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=M/9AAleVmFAMrayfO8gflHwlnHawghg4IbNPiAHidSA=; b=Ll3TIIyb3+cTyav5N+duey019cLReQSZgDRfCrRUCxlnXbiWgSstwEvZbC5MqyD+z8 tsjNeQ40N5RiIjeU6m1Wvs38hTiHgW7lYS1j7gfSgXzka4otkWe23j5tq3p9ycq8VO+/ VE19FqtSUM9LN2m4yHvUYniJLNnkFHN5n/e5ch68VygZNbFtP1N8x6Kq65uzK0wZiiv4 2JHmY2D41nscMhBDjMp9vIyOhum8jCmWuMl3ua48BUJ5ZxTBpRPF10PCgm/OzU5qkJ+g Y0duvPmPY2zI0z+qisBzXjguS8iL2WaJJlDpuAHlDnleH2eQDUkU59LgVOnu/N8TaKwb F5jg== X-Gm-Message-State: AOAM532GdcVjVFbNmJeYUvpdXKrNwHJ/xJbkjgkj56QjJ+MWB4d0lCC8 04KtsG67ghUOutl6hvpT8Q7lWWaxYYk= X-Google-Smtp-Source: ABdhPJy4mPNuOgXTUv0iVfS8Og7f8FyOegkBueCSwmhMt50Ur/q5IXlXsgTOR5ipG8s3Cw+/IbYTWg== X-Received: by 2002:aa7:da04:: with SMTP id r4mr16990098eds.343.1616786366594; Fri, 26 Mar 2021 12:19:26 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id c19sm4739373edu.20.2021.03.26.12.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 12:19:26 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Rob Herring , Mark Brown , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Lorenzo Pieralisi , Bjorn Helgaas , Florian Fainelli , Jim Quinlan , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 6/6] PCI: brcmstb: Check return value of clk_prepare_enable() Date: Fri, 26 Mar 2021 15:19:04 -0400 Message-Id: <20210326191906.43567-7-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210326191906.43567-1-jim2101024@gmail.com> References: <20210326191906.43567-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The check was missing on PCIe resume. Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli Fixes: 8195b7417018 ("PCI: brcmstb: Add suspend and resume pm_ops") --- drivers/pci/controller/pcie-brcmstb.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 2d9288399014..f6d9d785b301 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1396,7 +1396,9 @@ static int brcm_pcie_resume(struct device *dev) int ret; base = pcie->base; - clk_prepare_enable(pcie->clk); + ret = clk_prepare_enable(pcie->clk); + if (ret) + return ret; ret = brcm_set_regulators(pcie, TURN_ON); if (ret) @@ -1535,7 +1537,9 @@ static int brcm_pcie_probe(struct platform_device *pdev) ret = brcm_pcie_get_regulators(pcie); if (ret) { - dev_err(pcie->dev, "failed to get regulators (err=%d)\n", ret); + pcie->num_supplies = 0; + if (ret != -EPROBE_DEFER) + dev_err(pcie->dev, "failed to get regulators (err=%d)\n", ret); goto fail; }