From patchwork Thu Apr 1 06:00:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 12177225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65E72C433B4 for ; Thu, 1 Apr 2021 06:01:23 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 13B5861029 for ; Thu, 1 Apr 2021 06:01:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 13B5861029 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=gdnyVNQbkPMdRH6s/FIr6eWvfC9lMy0J/QBUZWF5ogA=; b=jhl6UMoBUR6f9dPUA5OxlqCab qcV5098jkztuKauS1OxMgNW4wfY0D9jjWTgCdm3MCGxBL2fDv/5hn24j/ydWhLVasDs4G/uPB4e74 737bXmkX+dPVu+6AN/J284UZ5tMPJUlMB/6PBSgyw21612nHbxPH5p/6oertZw96oiOIGIpzHyFph Ea8T53FsFZOSfcRmp43a1H8BF/fPutbT12RKD4JUgczJvJhPZdKCjdGLfNUfUQsFa9fIQh8UOkPYK K6nAQFQWsXePHFVb3yv8RMVt4z1xQHDO3PPhWAFo9A+gWrYrXilrnUk2+Mm4IR86Pns3g45Um50xs SLhF2j0hw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOF-008dME-AI; Thu, 01 Apr 2021 06:01:11 +0000 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOA-008dLE-KW for linux-riscv@lists.infradead.org; Thu, 01 Apr 2021 06:01:08 +0000 Received: by mail-pj1-x1036.google.com with SMTP id kk2-20020a17090b4a02b02900c777aa746fso430110pjb.3 for ; Wed, 31 Mar 2021 23:01:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GpnIpJRKR8YVkqmVpaGdSvOnyOEqskwKr4L6q3eaylA=; b=jT6Haqa51bUP9dayQuFMVbVDUzAPBplG+LPKKoKA1yURkZAENCVcZbmZMN2sAhlXgB W+YuNnelqR0IsbmSvAJ9oWldln5Nhhyp9gk2HhtAfnhHE9NWBmcizewfH8MiBjT6nmAS /+oU0EUGf82+J6oXj9/F3YdqKX2mPtbJL5ZTHoga4Q877X+xCO9jMUgFQvffEOKH2tD2 mjjJUzfubd1MYikRsehmvbH5tK6ks2KNAHZs4BjMMqPprESrT19OjzQyqjHTBg5iLRJ0 CZiwc76gZIVYk+6Apmk4DPunfsMBOPU3Efxp3JmtF+qVVgmV8DZxKHv27s8XjlgcuRba hWfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GpnIpJRKR8YVkqmVpaGdSvOnyOEqskwKr4L6q3eaylA=; b=uGX0dKu3aocfZE7WK7JJEHavkYtuTI54CTRDPb5fvOR4Rt4Wr3Fh4/sfjNX25l0HT+ BSUyGaquoFUCw7uJIW7vSJZKEcSKzEdrDUjhmUbc5p7lBAxAF1PS55oYJLxLMhGiopmw gDWOxAbgLx7D6V0+9lAALpgkl8cUaRqtib/KwHQUsF/U/CSDLYxgfYNR7b3Z94ezQpSP mK3lG4TyzDvAftBOkCvZ0GxW2z3HbX656x95e3b42b8ArUh+v4fZY6cyX2oUYn3tCLXB XMpLHxrtffapcldWeb8b2L56JNydASFreHBqzosC7qA5+TEJyCjHmb5rEQ93WgkZEvJA YL4w== X-Gm-Message-State: AOAM531mOoxzYQOgXR6W4dbynoHGOd/7qGSx050HWqpsSUns+KsyxPs9 rqVqL7tIi5b0L2m4NhHHsB51+g== X-Google-Smtp-Source: ABdhPJxLBCPD2YoxELe9+amN+WWZUmBn7iOBnXCAQm9LogvFqg9wzrf6lwA8mFXR2oIA8hJgdo+IEg== X-Received: by 2002:a17:902:9a06:b029:e6:9241:2779 with SMTP id v6-20020a1709029a06b02900e692412779mr6391875plp.24.1617256865185; Wed, 31 Mar 2021 23:01:05 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id a6sm4037328pfc.61.2021.03.31.23.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 23:01:04 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, paul.walmsley@sifive.com, hes@sifive.com, erik.danie@sifive.com, zong.li@sifive.com, bhelgaas@google.com, robh+dt@kernel.org, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.pieralisi@arm.com, p.zabel@pengutronix.de, alex.dewar90@gmail.com, khilman@baylibre.com, hayashi.kunihiko@socionext.com, vidyas@nvidia.com, jh80.chung@samsung.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, helgaas@kernel.org Subject: [PATCH v4 1/6] clk: sifive: Add pcie_aux clock in prci driver for PCIe driver Date: Thu, 1 Apr 2021 14:00:49 +0800 Message-Id: <20210401060054.40788-2-greentime.hu@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210401060054.40788-1-greentime.hu@sifive.com> References: <20210401060054.40788-1-greentime.hu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210401_070106_827263_F512BC41 X-CRM114-Status: GOOD ( 16.83 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We add pcie_aux clock in this patch so that pcie driver can use clk_prepare_enable() and clk_disable_unprepare() to enable and disable pcie_aux clock. Signed-off-by: Greentime Hu Acked-by: Stephen Boyd --- drivers/clk/sifive/fu740-prci.c | 11 +++++ drivers/clk/sifive/fu740-prci.h | 2 +- drivers/clk/sifive/sifive-prci.c | 41 +++++++++++++++++++ drivers/clk/sifive/sifive-prci.h | 9 ++++ include/dt-bindings/clock/sifive-fu740-prci.h | 1 + 5 files changed, 63 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 764d1097aa51..53f6e00a03b9 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -72,6 +72,12 @@ static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, }; +static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { + .enable = sifive_prci_pcie_aux_clock_enable, + .disable = sifive_prci_pcie_aux_clock_disable, + .is_enabled = sifive_prci_pcie_aux_clock_is_enabled, +}; + /* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu740[] = { [PRCI_CLK_COREPLL] = { @@ -120,4 +126,9 @@ struct __prci_clock __prci_init_clocks_fu740[] = { .parent_name = "hfpclkpll", .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, }, + [PRCI_CLK_PCIE_AUX] = { + .name = "pcie_aux", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_pcie_aux_clk_ops, + }, }; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h index 13ef971f7764..511a0bf7ba2b 100644 --- a/drivers/clk/sifive/fu740-prci.h +++ b/drivers/clk/sifive/fu740-prci.h @@ -9,7 +9,7 @@ #include "sifive-prci.h" -#define NUM_CLOCK_FU740 8 +#define NUM_CLOCK_FU740 9 extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index c78b042750e2..8fdba5da2902 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -448,6 +448,47 @@ void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd) r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ } +/* PCIE AUX clock APIs for enable, disable. */ +int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw) +{ + struct __prci_clock *pc = clk_hw_to_prci_clock(hw); + struct __prci_data *pd = pc->pd; + u32 r; + + r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); + + if (r & PRCI_PCIE_AUX_EN_MASK) + return 1; + else + return 0; +} + +int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw) +{ + struct __prci_clock *pc = clk_hw_to_prci_clock(hw); + struct __prci_data *pd = pc->pd; + u32 r __maybe_unused; + + if (sifive_prci_pcie_aux_clock_is_enabled(hw)) + return 0; + + __prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd); + r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */ + + return 0; +} + +void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw) +{ + struct __prci_clock *pc = clk_hw_to_prci_clock(hw); + struct __prci_data *pd = pc->pd; + u32 r __maybe_unused; + + __prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd); + r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */ + +} + /** * __prci_register_clocks() - register clock controls in the PRCI * @dev: Linux struct device diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index dbdbd1722688..022c67cf053c 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -67,6 +67,11 @@ #define PRCI_DDRPLLCFG1_CKE_SHIFT 31 #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) +/* PCIEAUX */ +#define PRCI_PCIE_AUX_OFFSET 0x14 +#define PRCI_PCIE_AUX_EN_SHIFT 0 +#define PRCI_PCIE_AUX_EN_MASK (0x1 << PRCI_PCIE_AUX_EN_SHIFT) + /* GEMGXLPLLCFG0 */ #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 @@ -296,4 +301,8 @@ unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw, unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate); +int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw); +int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw); +void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw); + #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h index cd7706ea5677..7899b7fee7db 100644 --- a/include/dt-bindings/clock/sifive-fu740-prci.h +++ b/include/dt-bindings/clock/sifive-fu740-prci.h @@ -19,5 +19,6 @@ #define PRCI_CLK_CLTXPLL 5 #define PRCI_CLK_TLCLK 6 #define PRCI_CLK_PCLK 7 +#define PRCI_CLK_PCIE_AUX 8 #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ From patchwork Thu Apr 1 06:00:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 12177229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08D61C433B4 for ; Thu, 1 Apr 2021 06:01:28 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2A4061001 for ; Thu, 1 Apr 2021 06:01:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A2A4061001 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=P192ppIXF/qA09gHcCFl2NwcNbS+LBDQehKJLO5dYx8=; b=Q+vKgmdfv2Ug7Q6ijpRTj5bfz b6yKt6rHYFBg2/xINeEGZsyj5eIqxA55Csw5gOgWuFSSspn/tUsWY+N/PjXOr+WvvBHhtmp7usWSu tUXX4vUuCZX+UbsfGe0VGDXUW9pl+Bz/KNfGIJMiMVeFgWw21wi5Ww160DqMZRMudYeYsRsqoKfuB kD+og9G1Z+XY/Net+elz2UoTMV60DJryHMYGniCJulU2+O/VNRQ4gEEn19JCunXpTE7RBQ79H9i7I oTIboGia1DHifGCKjf2XkXTn2BjUEewf3kbItZzCvj5dejvDIDGJ0r6Z9r7G2oV+T2Lv/zOd1ecQ5 8Gy7abaAA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOK-008dN0-06; Thu, 01 Apr 2021 06:01:16 +0000 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOE-008dLz-FL for linux-riscv@lists.infradead.org; Thu, 01 Apr 2021 06:01:12 +0000 Received: by mail-pl1-x634.google.com with SMTP id l1so458362plg.12 for ; Wed, 31 Mar 2021 23:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=N3Ofv7Rek7cgGq9uaGjBnpEgWWaqpn6QcKrofIPEUwg=; b=khgPA2tQj0XBl2pjmoT1nQKH2acgI+DuwZDuMbLf2uyMrCQKpwXFRC2bkp5RSvE4bR dpj/jj1FSTaErZYHck9AuCc7U9cjMBG0NCw4eJrFCQGkDoIx6ApYpcsY8wG6iuq5KKF4 arNMGBm/Kc412mQ8pwCeZ3dJ6uJO0a7FiVG7ZLKpEsubvuwA560wW6Vsl6LbV/3nav0k /37SBRMn8mdwx7h46HewEDJOdO0Wx5ENT1UW2PI2VMihHUpecdzQvMU4MF2h4F6T00vR V5DRlHfr2hcROXKGeVqExb6aASusihjhKxlKnJNTycdj6UO2FzMt28303zUN4d+A84vf HNZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N3Ofv7Rek7cgGq9uaGjBnpEgWWaqpn6QcKrofIPEUwg=; b=MKpc8nuWgrVHwaDyQL9F+fnnYPTD45Z7sR9tMWhIBqa0SOMiVoUWZj7jvoo/Jr5xvL 7njucPTDzWGyvC5N3Sus78oKld07o7NnwT4O8RA8TlQU7h3fAjRAkToLFMeMRWpppA36 r9ZTMKMXZUbRKRqS0DTLW1PZyFiggp0pXAoRDi/fjQuY90sVdXfJgZFAb1egSVarNqyU KuF9evw7JKXGCiCtIJupvRN6zoy9geQU4Gne0P2RVvFq6xw7RuUUf8BmMmZEzKjcR/n4 D2IFVjS40SQePunXLEJs9vDP05XcHFncpJFHxMwokn0fHsJntHlqkoVrfomupNqiPFus ovow== X-Gm-Message-State: AOAM532pcN4bdk43xvI1EPlt0CzIwUQzS9gtV8y/Mbnrmi9I8dqtogXc 35ux+3P1FPMA6ndl9371M14ByQ== X-Google-Smtp-Source: ABdhPJwHZ+BcpY81xjQ/CI0AKookTPicx5Fd19k1RijF0z5miZkInR3ttYqjRggO0gvUVrY6JGCAWA== X-Received: by 2002:a17:90a:2e0d:: with SMTP id q13mr7467523pjd.225.1617256869026; Wed, 31 Mar 2021 23:01:09 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id a6sm4037328pfc.61.2021.03.31.23.01.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 23:01:08 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, paul.walmsley@sifive.com, hes@sifive.com, erik.danie@sifive.com, zong.li@sifive.com, bhelgaas@google.com, robh+dt@kernel.org, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.pieralisi@arm.com, p.zabel@pengutronix.de, alex.dewar90@gmail.com, khilman@baylibre.com, hayashi.kunihiko@socionext.com, vidyas@nvidia.com, jh80.chung@samsung.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, helgaas@kernel.org Subject: [PATCH v4 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver Date: Thu, 1 Apr 2021 14:00:50 +0800 Message-Id: <20210401060054.40788-3-greentime.hu@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210401060054.40788-1-greentime.hu@sifive.com> References: <20210401060054.40788-1-greentime.hu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210401_070111_061770_D9840B99 X-CRM114-Status: GOOD ( 13.53 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Signed-off-by: Greentime Hu Reviewed-by: Philipp Zabel Acked-by: Stephen Boyd --- drivers/clk/sifive/Kconfig | 2 ++ drivers/clk/sifive/sifive-prci.c | 13 +++++++++++++ drivers/clk/sifive/sifive-prci.h | 4 ++++ drivers/reset/Kconfig | 1 + 4 files changed, 20 insertions(+) diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 1c14eb20c066..9132c3c4aa86 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -10,6 +10,8 @@ if CLK_SIFIVE config CLK_SIFIVE_PRCI bool "PRCI driver for SiFive SoCs" + select RESET_CONTROLLER + select RESET_SIMPLE select CLK_ANALOGBITS_WRPLL_CLN28HPC help Supports the Power Reset Clock interface (PRCI) IP block found in diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 8fdba5da2902..0704fddba6b9 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -583,6 +583,19 @@ static int sifive_prci_probe(struct platform_device *pdev) if (IS_ERR(pd->va)) return PTR_ERR(pd->va); + pd->reset.rcdev.owner = THIS_MODULE; + pd->reset.rcdev.nr_resets = PRCI_RST_NR; + pd->reset.rcdev.ops = &reset_simple_ops; + pd->reset.rcdev.of_node = pdev->dev.of_node; + pd->reset.active_low = true; + pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET; + spin_lock_init(&pd->reset.lock); + + r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev); + if (r) { + dev_err(dev, "could not register reset controller: %d\n", r); + return r; + } r = __prci_register_clocks(dev, pd, desc); if (r) { dev_err(dev, "could not register clocks: %d\n", r); diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 022c67cf053c..91658a88af4e 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -11,6 +11,7 @@ #include #include +#include #include /* @@ -121,6 +122,8 @@ #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) +#define PRCI_RST_NR 7 + /* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 @@ -221,6 +224,7 @@ */ struct __prci_data { void __iomem *va; + struct reset_simple_data reset; struct clk_hw_onecell_data hw_clks; }; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 71ab75a46491..d0f5d0afc240 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -187,6 +187,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - SiFive FU740 SoCs config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST From patchwork Thu Apr 1 06:00:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 12177231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED94AC433ED for ; Thu, 1 Apr 2021 06:01:30 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9949061029 for ; Thu, 1 Apr 2021 06:01:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9949061029 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2xZCF3JYSCq6fgpTW5R5587DzkBB2b5+rShtykeH1SM=; b=DnKZbr3uiZ5sHOVw0jS96ewNM EmB3xKY4ZSvT1E+bWzQWOx+2ekXpWPndpbPpbvRkCl7RDQlVZc55yFnQSEy7QNbyfK6nfjo/DCo/T aWP/hBJ8ZCzCGwXZIMuiGN+LYp0jk2lOJjTKQvl6yJoflvD7FSFmbB5xGIxqh9ejBKaueoxUi/VJn GmFs1p/8eiqdvVwTX//G+T3t9LDcANnGb06tLnwzduU1usw+kbJeVAqbWFvyHyjh8fT+qyemNjL6o AueOgCaDx0zvtahYsLfQ7PXViExhxldn8oEQwjABlqu7xkFee9Z2CtOZs/oH4ptbhyugzAO335nDR U3ycuiK3A==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOM-008dNZ-Nu; Thu, 01 Apr 2021 06:01:18 +0000 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOI-008dMg-Dg for linux-riscv@lists.infradead.org; Thu, 01 Apr 2021 06:01:16 +0000 Received: by mail-pl1-x630.google.com with SMTP id v8so461619plz.10 for ; Wed, 31 Mar 2021 23:01:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QOCh/TS5wxbMixJ7U1RoahsowYw6MPj7syv0qXToETI=; b=iPjWyKtkwhzUHTxPcjnT4icYgXJ7zeDUmfzg9v5YkSf5p3CwKPx6bI7A7SoN6Syojb +X/YcY+mMV2reL7FiisXXKwUCnCFbegv+dR+mgozFG9QthGF/cvRGbx4ItscX/pzmjSr YdbNQIUOdkiZRfFVSyX/4vhaHdDRmeClwLKm5jF38Bg9Qh6oQWsn3wuwt2HjMpzI2teg XligTyJSVmA/gqRO4F3zNX/TjnOr+h7Iqv5vJaQSsxNnWsyDRJqxd9sd+35b2VkgwnDC 1ox57sHJ1mYlfIf7EduwYwidHRP+6Rw4en/UcSGLsJ1HHBChwm1dc2jcws0hzVnRp1PB sKQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QOCh/TS5wxbMixJ7U1RoahsowYw6MPj7syv0qXToETI=; b=IzR+mgPxVeygu1w6k5gfPoRv8XTQ9qPJrFY153QJQQaqUvzT+2if/dLEDBWhtd/BvA joLSsSCpsQUm86p0Iae6BUeWJsVGHV7Iat7HE2NWb7r2XjuR9bbtrl+kJo5m0yfGnecZ 4+RUHNgZY5VtaXF1VKryzbK5NZqMIlumVLyEs/iyDeKggcd7DbFtiqPf0es/eYgbrb89 WHXH6TfipNnyaFNHb5jN8uXi7InzU8xGytUtUl2qfSiKR+0kcW+9xZQKXsMis3m33HA1 0slJj6R6rm3aB1iWCbZwGkRFFFFa6dupLoOWEyfrgFXGSBeXF/cn6sAQ/G9knqqqUZTA oxCw== X-Gm-Message-State: AOAM5307y0I3RD6FS1r6+YPhLrrEa5E8NTyB26uC8LdHUwEfNi2oq5o+ WZKkRigx146YguETSFEx4bRbHw== X-Google-Smtp-Source: ABdhPJy4PCdLb+qz9XgaXNOzMe05wTqJNbB/uYxc86af5nogDmNs+NbnIcxuL9wZclBB8UWU1DpfJQ== X-Received: by 2002:a17:90b:3551:: with SMTP id lt17mr7247531pjb.1.1617256872902; Wed, 31 Mar 2021 23:01:12 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id a6sm4037328pfc.61.2021.03.31.23.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 23:01:12 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, paul.walmsley@sifive.com, hes@sifive.com, erik.danie@sifive.com, zong.li@sifive.com, bhelgaas@google.com, robh+dt@kernel.org, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.pieralisi@arm.com, p.zabel@pengutronix.de, alex.dewar90@gmail.com, khilman@baylibre.com, hayashi.kunihiko@socionext.com, vidyas@nvidia.com, jh80.chung@samsung.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, helgaas@kernel.org Subject: [PATCH v4 3/6] MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver Date: Thu, 1 Apr 2021 14:00:51 +0800 Message-Id: <20210401060054.40788-4-greentime.hu@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210401060054.40788-1-greentime.hu@sifive.com> References: <20210401060054.40788-1-greentime.hu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210401_070114_522966_4177B817 X-CRM114-Status: UNSURE ( 7.55 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Here add maintainer information for SiFive FU740 PCIe driver. Signed-off-by: Greentime Hu --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bfc1b86e3e73..4da888be6e80 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13592,6 +13592,14 @@ S: Maintained F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt F: drivers/pci/controller/dwc/*imx6* +PCI DRIVER FOR FU740 +M: Paul Walmsley +M: Greentime Hu +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml +F: drivers/pci/controller/dwc/pcie-fu740.c + PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD) M: Jonathan Derrick L: linux-pci@vger.kernel.org From patchwork Thu Apr 1 06:00:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 12177233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6293CC433B4 for ; Thu, 1 Apr 2021 06:01:36 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0855B61001 for ; Thu, 1 Apr 2021 06:01:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0855B61001 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ctFB1afYFcd5pfxmJSyJTL7qqd0QDSjcMkO0bMR56Yc=; b=GRJ2GAIKaPNf0kdp8UQ3IsRH8 sJVooDIa9J+w0mt5m9mhPRVN85xZ1cXluULRNvbOii1yE4xM4D0n/0RuIEpk+7yL5xby65mk3rnLZ 0m5AAiyENbL2M+vDsh6+CR/S/THer4NGlMsZd/SZsDAEr8zxHM0HkbQrTK9qSLfsFCrLW0+E4vBFi wc0vhuT3owjCGI1JsDAilraDhGXrvcL0rmgZUvVeCq1aXjQeW08nx0EgY+sR6z6jaoKjMhdEh56Vz JAdN7zL1M2maUBpfoDJAADRoINuBCI5hN6IuT6gjDCqUEJM/IVoOO3bOovTB0nKEWtWp9t7Qm6bz4 69JXXOfaA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOR-008dP8-9Z; Thu, 01 Apr 2021 06:01:23 +0000 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOM-008dNS-8N for linux-riscv@lists.infradead.org; Thu, 01 Apr 2021 06:01:20 +0000 Received: by mail-pj1-x102e.google.com with SMTP id q6-20020a17090a4306b02900c42a012202so422844pjg.5 for ; Wed, 31 Mar 2021 23:01:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dzHWDiN1Wjk8roHrncU6culKFNwJPo7qFVNBejhbdf4=; b=k8eR6VtkN8wT1BSouzItYIwAJdSwTRr7it0UlwPvelXLQvFcYC54FHPNplZN0dDFOG 0qLm8kfXUFYgf4dXNG6SW+ER4jWu3KcBNOX5Z5rVHepsqGfcOyWAYGwoW/1scNNWMmCX rJjthb05E5cEzrU7/e2F4UHqgjiPs0OSjZ/dIE2Gxs+56kbznt45dpOYE4W3K2g2ftnK rhmOQs8++mURWC0q9gJkgVtHazLQRJjOMRhJsXk76QMeWHbH1TV0qhpyNi+mHKQYow0s AlSrSto1iQK9Och9PepOI3B/xUWkDbPge6A+xg2jwrbXLNerdTrY0gqXIKesLwLjPCgD m5/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dzHWDiN1Wjk8roHrncU6culKFNwJPo7qFVNBejhbdf4=; b=TE+chhMOyxSn8moXYLG/OkNzFemzRkyWhbW8dUF444v6SYjmg0pfJbW46mAHcfQmAv RvgU3nwrkFGij29LWsFlOwOeBpSBMSRqr7i5WKAs507fv7wOYfXE9ZusdcSeBv71qANE gCEK+BpVCUyxvjEGmqf6OPMXsh8Nbple9V/+z1MXcc4H3G3rPJHHttTy88oRWFMuCP0U klyJeg/ZLjp5V0che7ePZfQc45JRBoUHarYpKg7BB7hXR0Jl0agERCNjE70ZhOh8S26j CMd57/I94aJ7oMxPn+E5UdhoZ3GTTp2PGUUll1DyHhCAFYwhG/Lzc8G8Xf1rwoUIUaI5 2xBw== X-Gm-Message-State: AOAM531lbwtlKStkzYjUmMLR3AV5mKbr5ThV5Q5oS0E+LEUji2fTaT7L 0VWrT+QadSpd/LBDJzky/wBqTQ== X-Google-Smtp-Source: ABdhPJwYiv6IgPM0+CkEXm5L8017kKc4FDmNfsfG7B94lYbTSJr4sXxzel32KW9uR7kI3Wh+OC61tQ== X-Received: by 2002:a17:90a:8c08:: with SMTP id a8mr7312649pjo.136.1617256876819; Wed, 31 Mar 2021 23:01:16 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id a6sm4037328pfc.61.2021.03.31.23.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 23:01:16 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, paul.walmsley@sifive.com, hes@sifive.com, erik.danie@sifive.com, zong.li@sifive.com, bhelgaas@google.com, robh+dt@kernel.org, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.pieralisi@arm.com, p.zabel@pengutronix.de, alex.dewar90@gmail.com, khilman@baylibre.com, hayashi.kunihiko@socionext.com, vidyas@nvidia.com, jh80.chung@samsung.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, helgaas@kernel.org Subject: [PATCH v4 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller Date: Thu, 1 Apr 2021 14:00:52 +0800 Message-Id: <20210401060054.40788-5-greentime.hu@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210401060054.40788-1-greentime.hu@sifive.com> References: <20210401060054.40788-1-greentime.hu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210401_070118_688450_8C58B59D X-CRM114-Status: GOOD ( 10.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add PCIe host controller DT bindings of SiFive FU740. Signed-off-by: Greentime Hu --- .../bindings/pci/sifive,fu740-pcie.yaml | 109 ++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml new file mode 100644 index 000000000000..ccb58e5f06d4 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive FU740 PCIe host controller + +description: |+ + SiFive FU740 PCIe host controller is based on the Synopsys DesignWare + PCI core. It shares common features with the PCIe DesignWare core and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.txt. + +maintainers: + - Paul Walmsley + - Greentime Hu + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: sifive,fu740-pcie + + reg: + maxItems: 3 + + reg-names: + items: + - const: dbi + - const: config + - const: mgmt + + num-lanes: + const: 8 + + msi-parent: true + + interrupt-names: + items: + - const: msi + - const: inta + - const: intb + - const: intc + - const: intd + + resets: + description: A phandle to the PCIe power up reset line. + + pwren-gpios: + description: Should specify the GPIO for controlling the PCI bus device power on. + maxItems: 1 + +required: + - dma-coherent + - num-lanes + - interrupts + - interrupt-names + - interrupt-parent + - interrupt-map-mask + - interrupt-map + - clock-names + - clocks + - resets + - pwren-gpios + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + #include + + pcie@e00000000 { + compatible = "sifive,fu740-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + reg = <0xe 0x00000000 0x0 0x80000000>, + <0xd 0xf0000000 0x0 0x10000000>, + <0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */ + <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */ + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */ + <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ + num-lanes = <0x8>; + interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>, + <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci PRCI_CLK_PCIE_AUX>; + resets = <&prci 4>; + pwren-gpios = <&gpio 5 0>; + reset-gpios = <&gpio 8 0>; + }; + }; From patchwork Thu Apr 1 06:00:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 12177235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F4A2C433B4 for ; Thu, 1 Apr 2021 06:01:41 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A52F61029 for ; Thu, 1 Apr 2021 06:01:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0A52F61029 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6UCDSwqdZN+ycPjO8zrXShqamiDXk2b1bBCaQAFy8E0=; b=WtiDhaS7fOKZQcicdWe92N5Td bso4Ef8lYoqrjeF6cLpI5BC/cIAEheh34wPXjOw+Bwbpmyf9al5JUZv7ON8CUCjiIKFSXQ2vovz51 IWLASfS9b5arO5y7e4NU8lU0J0nL/9BrWhI5PU6Vn3O6L1/TF379nB4A8AXPDoIb+7xOiI45T3bLs JW8CHT8syxPSytLCIOxn9wGZYvrYaCKhTISS58UzCfLVSf1Ym5ss8baBiwcd9+F9Qu8IahKOYjhbi TrY5wEbJohvn6KHrysLJOHXSGnM3xgoScbRWcxF+em96H5gi/vFebz29Bo666m3JNVM6CBfkgptaX bbghTiB8g==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOU-008dQ0-PE; Thu, 01 Apr 2021 06:01:26 +0000 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOP-008dOH-Vx for linux-riscv@lists.infradead.org; Thu, 01 Apr 2021 06:01:24 +0000 Received: by mail-pl1-x634.google.com with SMTP id w11so472025ply.6 for ; Wed, 31 Mar 2021 23:01:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mfhDzx20AsGw7xB1elLqDgyXq/O2lE+xOqpu/FQh9ps=; b=JEO8o499A8x7LiAfUs8bi/XTYPTZerMJFxKkx1lmjDDW9XldTBqYGqwz2boJkxZYwv lDvlxIe8M0q61OmkNInX24/eQHeNkxdoa2CVeucL0CvZXLtNLcc/pZpWdqGJ+MpIljxF /6HKp/gK59bC95XTwc00EM5yBcyypAjh1qbU1BtgNT17ccMpAufqBaFSdgyjBDGrElVc BQhpFlyelXd/yf/bRXdKScZzOnJG33hnpAKZMT8ppu+jbW7CO2A51I+tz+nfOYO1PJv9 zOYmEMeM5jE8qAYB/ynUrIKfGk+ILkxovOdHDYmze7fe7kHsw63Q10gyXVb9htvYB5QT N56w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mfhDzx20AsGw7xB1elLqDgyXq/O2lE+xOqpu/FQh9ps=; b=roa6pR4hBTqXUW7ubtDefhCyRHnau2d+E1luya5Z9IC6MtEYg5GaATD6CNGweFUOO7 mBv+tRlfnpY7QtjtW0qwDVdV8uJXt6d9vPqvUA+erHwxYuzijSkOXV9FWTJ9yh4eXMxd 0eHwYyFbVsIAbKOVc7iL1GeY+15xAQhmiVsp+12NMJ2+d/ffcBV+e3v21ZfTRUrcQ87X RrOdZWL4dxcySkHfIV9Kl4pbhEtdQS6hiRz0Ov71IhKXVpRLco/pAa0aLcjfILGiyo90 apvfINXOm5XEynx9776ECckHyQukEB6XsHwEXQ7FND95kg92cLKITLXVnCq99w+CCtsb gPOw== X-Gm-Message-State: AOAM5333Oud8ySJd2U7Ga5i1rIjFo+LBYRP1bXs1n3JEMd0bOJqrZDGI py1uSXfecRNQy3824DDoB4zQSQ== X-Google-Smtp-Source: ABdhPJwd1QPlk77uDYZg5uGmksD6SLy38xOqqQfvBpuje83in9GjNEj7/XKVDitYcvW7bQjjGkcY6w== X-Received: by 2002:a17:90a:e646:: with SMTP id ep6mr7395443pjb.101.1617256880746; Wed, 31 Mar 2021 23:01:20 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id a6sm4037328pfc.61.2021.03.31.23.01.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 23:01:20 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, paul.walmsley@sifive.com, hes@sifive.com, erik.danie@sifive.com, zong.li@sifive.com, bhelgaas@google.com, robh+dt@kernel.org, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.pieralisi@arm.com, p.zabel@pengutronix.de, alex.dewar90@gmail.com, khilman@baylibre.com, hayashi.kunihiko@socionext.com, vidyas@nvidia.com, jh80.chung@samsung.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, helgaas@kernel.org Subject: [PATCH v4 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver Date: Thu, 1 Apr 2021 14:00:53 +0800 Message-Id: <20210401060054.40788-6-greentime.hu@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210401060054.40788-1-greentime.hu@sifive.com> References: <20210401060054.40788-1-greentime.hu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210401_070122_211901_9784BA89 X-CRM114-Status: GOOD ( 23.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Paul Walmsley Add driver for the SiFive FU740 PCIe host controller. This controller is based on the DesignWare PCIe core. Signed-off-by: Paul Walmsley Co-developed-by: Henry Styles Signed-off-by: Henry Styles Co-developed-by: Erik Danie Signed-off-by: Erik Danie Co-developed-by: Greentime Hu Signed-off-by: Greentime Hu --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-fu740.c | 324 ++++++++++++++++++++++++ 3 files changed, 334 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-fu740.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 22c5529e9a65..0a37d21ed64e 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -318,4 +318,13 @@ config PCIE_AL required only for DT-based platforms. ACPI platforms with the Annapurna Labs PCIe controller don't need to enable this. +config PCIE_FU740 + bool "SiFive FU740 PCIe host controller" + depends on PCI_MSI_IRQ_DOMAIN + depends on SOC_SIFIVE || COMPILE_TEST + select PCIE_DW_HOST + help + Say Y here if you want PCIe controller support for the SiFive + FU740. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index a751553fa0db..625f6aaeb5b8 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o +obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controller/dwc/pcie-fu740.c new file mode 100644 index 000000000000..ebbcbda97490 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-fu740.c @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * FU740 DesignWare PCIe Controller integration + * Copyright (C) 2019-2021 SiFive, Inc. + * Paul Walmsley + * Greentime Hu + * + * Based in part on the i.MX6 PCIe host controller shim which is: + * + * Copyright (C) 2013 Kosagi + * https://www.kosagi.com + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_fu740_pcie(x) dev_get_drvdata((x)->dev) + +struct fu740_pcie { + struct dw_pcie pci; + void __iomem *mgmt_base; + struct gpio_desc *reset; + struct gpio_desc *pwren; + struct clk *pcie_aux; + struct reset_control *rst; +}; + +#define SIFIVE_DEVICESRESETREG 0x28 + +#define PCIEX8MGMT_PERST_N 0x0 +#define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10 +#define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18 +#define PCIEX8MGMT_DEVICE_TYPE 0x708 +#define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860 +#define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870 +#define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878 +#define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880 +#define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888 +#define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890 +#define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898 +#define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0 +#define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0 +#define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8 +#define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0 +#define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8 +#define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0 +#define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8 + +#define PCIEX8MGMT_PHY_CDR_TRACK_EN BIT(0) +#define PCIEX8MGMT_PHY_LOS_THRSHLD BIT(5) +#define PCIEX8MGMT_PHY_TERM_EN BIT(9) +#define PCIEX8MGMT_PHY_TERM_ACDC BIT(10) +#define PCIEX8MGMT_PHY_EN BIT(11) +#define PCIEX8MGMT_PHY_INIT_VAL (PCIEX8MGMT_PHY_CDR_TRACK_EN|\ + PCIEX8MGMT_PHY_LOS_THRSHLD|\ + PCIEX8MGMT_PHY_TERM_EN|\ + PCIEX8MGMT_PHY_TERM_ACDC|\ + PCIEX8MGMT_PHY_EN) + +#define PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 0x1008 +#define PCIEX8MGMT_PHY_LANE_OFF 0x100 +#define PCIEX8MGMT_PHY_LANE0_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 0) +#define PCIEX8MGMT_PHY_LANE1_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 1) +#define PCIEX8MGMT_PHY_LANE2_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 2) +#define PCIEX8MGMT_PHY_LANE3_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 3) + +static void fu740_pcie_assert_reset(struct fu740_pcie *afp) +{ + /* Assert PERST_N GPIO */ + gpiod_set_value_cansleep(afp->reset, 0); + /* Assert controller PERST_N */ + writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N); +} + +static void fu740_pcie_deassert_reset(struct fu740_pcie *afp) +{ + /* Deassert controller PERST_N */ + writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N); + /* Deassert PERST_N GPIO */ + gpiod_set_value_cansleep(afp->reset, 1); +} + +static void fu740_pcie_power_on(struct fu740_pcie *afp) +{ + gpiod_set_value_cansleep(afp->pwren, 1); + /* + * Ensure that PERST has been asserted for at least 100 ms. + * Section 2.2 of PCI Express Card Electromechanical Specification + * Revision 3.0 + */ + msleep(100); +} + +static void fu740_pcie_drive_reset(struct fu740_pcie *afp) +{ + fu740_pcie_assert_reset(afp); + fu740_pcie_power_on(afp); + fu740_pcie_deassert_reset(afp); +} + +static void fu740_phyregwrite(const uint8_t phy, const uint16_t addr, + const uint16_t wrdata, struct fu740_pcie *afp) +{ + struct device *dev = afp->pci.dev; + void __iomem *phy_cr_para_addr; + void __iomem *phy_cr_para_wr_data; + void __iomem *phy_cr_para_wr_en; + void __iomem *phy_cr_para_ack; + int ret, val; + + /* Setup */ + if (phy) { + phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ADDR; + phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_DATA; + phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_EN; + phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ACK; + } else { + phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ADDR; + phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_DATA; + phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_EN; + phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ACK; + } + + writel_relaxed(addr, phy_cr_para_addr); + writel_relaxed(wrdata, phy_cr_para_wr_data); + writel_relaxed(1, phy_cr_para_wr_en); + + /* Wait for wait_idle */ + ret = readl_poll_timeout(phy_cr_para_ack, val, val, 10, 5000); + if (ret) + dev_err(dev, "Wait for wait_ilde state failed!\n"); + + /* Clear */ + writel_relaxed(0, phy_cr_para_wr_en); + + /* Wait for ~wait_idle */ + ret = readl_poll_timeout(phy_cr_para_ack, val, !val, 10, 5000); + if (ret) + dev_err(dev, "Wait for !wait_ilde state failed!\n"); +} + +static void fu740_pcie_init_phy(struct fu740_pcie *afp) +{ + /* Enable phy cr_para_sel interfaces */ + writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL); + writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL); + + /* + * Wait 10 cr_para cycles to guarantee that the registers are ready + * to be edited. + */ + ndelay(10); + + /* Set PHY AC termination mode */ + fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); + fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); + fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); + fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); + fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); + fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); + fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); + fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); +} + +static void fu740_pcie_ltssm_enable(struct device *dev) +{ + struct fu740_pcie *afp = dev_get_drvdata(dev); + + /* Enable LTSSM */ + writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE); +} + +static int fu740_pcie_start_link(struct dw_pcie *pci) +{ + struct device *dev = pci->dev; + + /* Start LTSSM. */ + fu740_pcie_ltssm_enable(dev); + return 0; +} + +static int fu740_pcie_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct fu740_pcie *afp = to_fu740_pcie(pci); + struct device *dev = pci->dev; + int ret; + + /* Power on reset */ + fu740_pcie_drive_reset(afp); + + /* Enable pcieauxclk */ + ret = clk_prepare_enable(afp->pcie_aux); + if (ret) + dev_err(dev, "unable to enable pcie_aux clock\n"); + + /* + * Assert hold_phy_rst (hold the controller LTSSM in reset after + * power_up_rst_n for register programming with cr_para) + */ + writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST); + + /* Deassert power_up_rst_n */ + ret = reset_control_deassert(afp->rst); + if (ret) + dev_err(dev, "unable to deassert pcie_power_up_rst_n\n"); + + fu740_pcie_init_phy(afp); + + /* Disable pcieauxclk */ + clk_disable_unprepare(afp->pcie_aux); + /* Clear hold_phy_rst */ + writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST); + /* Enable pcieauxclk */ + ret = clk_prepare_enable(afp->pcie_aux); + /* Set RC mode */ + writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE); + + return 0; +} + +static const struct dw_pcie_host_ops fu740_pcie_host_ops = { + .host_init = fu740_pcie_host_init, +}; + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = fu740_pcie_start_link, +}; + +static int fu740_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dw_pcie *pci; + struct fu740_pcie *afp; + int ret; + + afp = devm_kzalloc(dev, sizeof(*afp), GFP_KERNEL); + if (!afp) + return -ENOMEM; + pci = &afp->pci; + pci->dev = dev; + pci->ops = &dw_pcie_ops; + pci->pp.ops = &fu740_pcie_host_ops; + + /* SiFive specific region: mgmt */ + afp->mgmt_base = devm_platform_ioremap_resource_byname(pdev, "mgmt"); + if (IS_ERR(afp->mgmt_base)) + return PTR_ERR(afp->mgmt_base); + + /* Fetch GPIOs */ + afp->reset = devm_gpiod_get_optional(dev, "reset-gpios", GPIOD_OUT_LOW); + if (IS_ERR(afp->reset)) { + dev_err(dev, "unable to get reset-gpios\n"); + return ret; + } + afp->pwren = devm_gpiod_get_optional(dev, "pwren-gpios", GPIOD_OUT_LOW); + if (IS_ERR(afp->pwren)) { + dev_err(dev, "unable to get pwren-gpios\n"); + return ret; + } + + /* Fetch clocks */ + afp->pcie_aux = devm_clk_get(dev, "pcie_aux"); + if (IS_ERR(afp->pcie_aux)) + return dev_err_probe(dev, PTR_ERR(afp->pcie_aux), + "pcie_aux clock source missing or invalid\n"); + + /* Fetch reset */ + afp->rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(afp->rst)) + return dev_err_probe(dev, PTR_ERR(afp->rst), "unable to get reset\n"); + + platform_set_drvdata(pdev, afp); + + ret = dw_pcie_host_init(&pci->pp); + if (ret < 0) + return ret; + + return 0; +} + +static void fu740_pcie_shutdown(struct platform_device *pdev) +{ + struct fu740_pcie *afp = platform_get_drvdata(pdev); + + /* Bring down link, so bootloader gets clean state in case of reboot */ + fu740_pcie_assert_reset(afp); +} + +static const struct of_device_id fu740_pcie_of_match[] = { + { .compatible = "sifive,fu740-pcie", }, + {}, +}; + +static struct platform_driver fu740_pcie_driver = { + .driver = { + .name = "fu740-pcie", + .of_match_table = fu740_pcie_of_match, + .suppress_bind_attrs = true, + }, + .probe = fu740_pcie_probe, + .shutdown = fu740_pcie_shutdown, +}; + +builtin_platform_driver(fu740_pcie_driver); From patchwork Thu Apr 1 06:00:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 12177237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28A49C43603 for ; Thu, 1 Apr 2021 06:01:44 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D4DDA6105A for ; Thu, 1 Apr 2021 06:01:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D4DDA6105A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=e38bc+dZ53pyHUpolad+fZ7YUBCZdXJBsHAxQOIuAOc=; b=IBM5ZekKoJd8WVeDG+vm+whbg CorbIr5Je9QBAWoNFIOCM8qqRrhM+MGY9FCAZpw4Pvn005kBOKHAI9y4/UIpGifsN6lT9s8aUrfTk QGgBBsxezhsKmkPClMj/znIWx7m/sANL54RneQx85CTBHDTT/2BUhiOUoRHF1l5ufvWcFkHhLXJzz s4A7+vsjmEdw2YUbATYQXte3qeX0TgceRScZp3paHImrQmhag0CPbahivdaGMDknSD0l39VOfrFYe d9Q4ow0cX79A8v7632x/8wDLZnfnKabAXF9ifw0/GKHjAMBv6Ic7HtQXMjtYjnZk+gD+IXUC8ZkQU FA+mhsTqg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOX-008dRe-Ob; Thu, 01 Apr 2021 06:01:29 +0000 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRqOU-008dPi-5h for linux-riscv@lists.infradead.org; Thu, 01 Apr 2021 06:01:28 +0000 Received: by mail-pf1-x431.google.com with SMTP id c17so655422pfn.6 for ; Wed, 31 Mar 2021 23:01:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bJDxiGn0zb+AtBhh3GrH3c02J/dSNj0T0Os6e9JU2HI=; b=fADFrw70kQ6R9GVUIqdKks1e5hHtR47gSn2Ei7hYKbBt0gKF8Uk2eLlfFRlEMYW3Rg NS2s5c+CnMsJcIUytKnOsifC4Ycy3o1qIPAaSN9vuopXuPr7jhL8WzWNTYX4PTYjLdz9 8Lm9b++bZYs77iQ1TZO0C/QeTxhUuwZCJe42bOZbYTb2yTyw3jw+F1gvCTwnJbpr2Tq+ MLsDvkEvqFI1nJlOyuZS0DhDo6t8BLOGwHcMluY47uYrfvKkvVBkXC/qNiA7vD7tLgZY UpwNq8Nez8+FbI9uXByFHPPZmdPzq8+YpX7d+0jNS49ok9S63UtuLTuB/7pll8cSY/PH jEqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bJDxiGn0zb+AtBhh3GrH3c02J/dSNj0T0Os6e9JU2HI=; b=NPyiQvjQPelpj/HtBF44wQp1WEyQNPhbBqNBtLCHDO1ytKIIHeFj3sEtnED640VdlJ KzycO7QLukM4BFuYNCEYe/Bid4bumjh30y1PSjTFTLDUGG01gesJxvHaxKEorRYB7GHF d2xt+zgvS9H5LStv0CSPhYklTlt0K9cCw5DaDJIZV7lyTY9ATCCF6N7ZiYbfO8Q/C1fi 5V8nNrtW9VfyByo1Yy3euvHxVOfyXBnuBxkR9Pp80xokJxsqCyua33Gcl+cciIAEcr4W gR6krpz+C+ys4hgedaWK6DoLjNjpm3X+XhYymzGmvCzV77JQfrL97ns9gJHUsYAkGFO4 gdYQ== X-Gm-Message-State: AOAM530FVU6RHoaSwP30mjKbOnXF4J3D7jEi64TscbxoCsamP4SZLiTT Qb/mZQyPvpNcVWrW62bYsWgLMA== X-Google-Smtp-Source: ABdhPJyQi+hmIS6NcVuS5ZNb8DrPEY3M/Gs8RhNMfXIYA91WfDdO0PRAMZBlYQ8QD6rU6+FOVZG/Ug== X-Received: by 2002:a62:4e57:0:b029:203:93bc:3cb with SMTP id c84-20020a624e570000b029020393bc03cbmr6022563pfb.56.1617256884685; Wed, 31 Mar 2021 23:01:24 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id a6sm4037328pfc.61.2021.03.31.23.01.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 23:01:24 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, paul.walmsley@sifive.com, hes@sifive.com, erik.danie@sifive.com, zong.li@sifive.com, bhelgaas@google.com, robh+dt@kernel.org, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.pieralisi@arm.com, p.zabel@pengutronix.de, alex.dewar90@gmail.com, khilman@baylibre.com, hayashi.kunihiko@socionext.com, vidyas@nvidia.com, jh80.chung@samsung.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, helgaas@kernel.org Cc: Palmer Dabbelt Subject: [PATCH v4 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC Date: Thu, 1 Apr 2021 14:00:54 +0800 Message-Id: <20210401060054.40788-7-greentime.hu@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210401060054.40788-1-greentime.hu@sifive.com> References: <20210401060054.40788-1-greentime.hu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210401_070126_610644_09DE8912 X-CRM114-Status: UNSURE ( 8.01 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Signed-off-by: Greentime Hu Acked-by: Palmer Dabbelt --- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index d1bb22b11920..b2317c8e3a80 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -158,6 +158,7 @@ prci: clock-controller@10000000 { reg = <0x0 0x10000000 0x0 0x1000>; clocks = <&hfclk>, <&rtcclk>; #clock-cells = <1>; + #reset-cells = <1>; }; uart0: serial@10010000 { compatible = "sifive,fu740-c000-uart", "sifive,uart0"; @@ -288,5 +289,37 @@ gpio: gpio@10060000 { clocks = <&prci PRCI_CLK_PCLK>; status = "disabled"; }; + pcie@e00000000 { + compatible = "sifive,fu740-pcie"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + reg = <0xe 0x00000000 0x0 0x80000000>, + <0xd 0xf0000000 0x0 0x10000000>, + <0x0 0x100d0000 0x0 0x1000>; + reg-names = "dbi", "config", "mgmt"; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */ + <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */ + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */ + <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ + num-lanes = <0x8>; + interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, + <0x0 0x0 0x0 0x2 &plic0 58>, + <0x0 0x0 0x0 0x3 &plic0 59>, + <0x0 0x0 0x0 0x4 &plic0 60>; + clock-names = "pcie_aux"; + clocks = <&prci PRCI_CLK_PCIE_AUX>; + pwren-gpios = <&gpio 5 0>; + reset-gpios = <&gpio 8 0>; + resets = <&prci 4>; + status = "okay"; + }; }; };