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Fri, 2 Apr 2021 02:28:48 -0700 Envelope-to: git@xilinx.com, mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Received: from [10.140.6.60] (port=58326 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lSG6g-0005gX-VA; Fri, 02 Apr 2021 02:28:47 -0700 From: Nava kishore Manne To: , , , , , , , , , Subject: [PATCH 1/3] dt-bindings: zynqmp: Add new PD_PL macro Date: Fri, 2 Apr 2021 14:50:47 +0530 Message-ID: <20210402092049.479-2-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210402092049.479-1-nava.manne@xilinx.com> References: <20210402092049.479-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cc6b5ac7-2bf4-4572-504f-08d8f5b9bb55 X-MS-TrafficTypeDiagnostic: BL0PR02MB5635: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1079; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2021 09:28:53.2800 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc6b5ac7-2bf4-4572-504f-08d8f5b9bb55 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT006.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB5635 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Add new power domain for PL region. Signed-off-by: Nava kishore Manne Acked-by: Rob Herring --- include/dt-bindings/power/xlnx-zynqmp-power.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h index 0d9a412fd5e0..5f718759c38f 100644 --- a/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -35,5 +35,6 @@ #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 +#define PD_PL 69 #endif From patchwork Fri Apr 2 09:20:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12180565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78D8FC433ED for ; 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Fri, 02 Apr 2021 02:28:50 -0700 From: Nava kishore Manne To: , , , , , , , , , Subject: [PATCH 2/3] fpga: region: Add fpga-region property 'power-domains' Date: Fri, 2 Apr 2021 14:50:48 +0530 Message-ID: <20210402092049.479-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210402092049.479-1-nava.manne@xilinx.com> References: <20210402092049.479-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f78da796-3174-4eec-e3ac-08d8f5b9bd8d X-MS-TrafficTypeDiagnostic: SN6PR02MB5341: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HylBxwrF8ACviXGWrhO5qVo6Rvuzmb465frPYKaCHgimaztuEWniPZKpoq+3JXSJwdgGvShf2ieVQ4ArrkYGr1CH4jFEhQCkcwDunkRyZwHDobhNExYqpHpRO0RQ2MR5oExAlOiMHIHkVZqn6UvU8yeyDDHrmBpSdPQxA9zxJjOpB7XN2TUZLlniu+TxAlCJez7BnWTSS2us9MZAx31j3HFgnhpeo4N4GY+cYii92DqrlSLN3PL15Vx5ZKbMx5sYu56filxc5y7lT0bNeva6AhfT/QyBHu+CiO1hnQXf0KkJh5PLKjrpKBAoNa3QnZOKMVMe15OUiXOFTQnSD3HZOxKQt9n8HbCouqkSZMy6DBUSWs7Bj1lR+DFJ2Q+8d2qwYKKu+O9+gOaYU+GS6EjJDkgtk6xXUW7AeB1DOxvd+Y9PGqOt3XJyPQ8ffru/Qv/hvw+QCg67JQWkdbWxWaNqomKV+yH8S2WxJGL4VYlD/7idt2mX2AHwlIXuzS+NMMykA5ljnTl3LP8OGuQ/S6OIwMzGOg6eC0950TFUzV1FgOPKzQ/NScjx8BaoddpyLUj/YQjVl0MBr74RDKGyrYBj5qoT5g5XuPLkz6WFRTjGu5DVhtUFHnK2vVqP46fjeTRqZQU2vYBnvwDDgkowMYyYKUZEANArTp1I5E6YbLBzTOXd4lCeaqcHWEvLATEVpZdkT6tBJLncserRWkS544v738JHcVFeOCvk+MMIoI2U8zie+OptLG0m4V715uzQyaI1 X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(376002)(136003)(346002)(39860400002)(396003)(46966006)(36840700001)(7696005)(47076005)(7636003)(356005)(8676002)(5660300002)(110136005)(426003)(8936002)(921005)(1076003)(186003)(9786002)(36860700001)(82740400003)(26005)(36756003)(478600001)(82310400003)(2616005)(70206006)(6636002)(316002)(2906002)(336012)(36906005)(70586007)(102446001)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2021 09:28:57.0063 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f78da796-3174-4eec-e3ac-08d8f5b9bd8d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT006.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5341 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Add fpga-region property 'power-domains' to allow to handle the FPGA/PL power domins. dt-bindings: fpga: Enable PM generic domain support Signed-off-by: Nava kishore Manne Acked-by: Rob Herring --- .../devicetree/bindings/fpga/fpga-region.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index e811cf825019..969ca53bb65e 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -196,6 +196,20 @@ Optional properties: - config-complete-timeout-us : The maximum time in microseconds time for the FPGA to go to operating mode after the region has been programmed. - child nodes : devices in the FPGA after programming. +- power-domains : A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. +Example: + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&zynqmp_pcap>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&zynqmp_firmware PL_PD>; + }; + + The PL_PD power domain will be turned on before loading the bitstream +and turned off while removing/unloading the bitstream using overlays. In the example below, when an overlay is applied targeting fpga-region0, fpga_mgr is used to program the FPGA. Two bridges are controlled during From patchwork Fri Apr 2 09:20:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12180567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72F4EC43461 for ; Fri, 2 Apr 2021 09:29:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3770661103 for ; Fri, 2 Apr 2021 09:29:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234914AbhDBJ3D (ORCPT ); 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Fri, 2 Apr 2021 02:28:54 -0700 Envelope-to: git@xilinx.com, mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Received: from [10.140.6.60] (port=58326 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lSG6m-0005gX-ST; Fri, 02 Apr 2021 02:28:53 -0700 From: Nava kishore Manne To: , , , , , , , , , Subject: [PATCH 3/3] fpga: region: Adds runtime PM support Date: Fri, 2 Apr 2021 14:50:49 +0530 Message-ID: <20210402092049.479-4-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210402092049.479-1-nava.manne@xilinx.com> References: <20210402092049.479-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1c3bd0c6-dff7-4fc8-d98d-08d8f5b9be0d X-MS-TrafficTypeDiagnostic: BL0PR02MB5697: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3044; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2021 09:28:57.8449 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c3bd0c6-dff7-4fc8-d98d-08d8f5b9be0d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT006.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB5697 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Adds support to handle FPGA/PL power domain. With this patch, the PL power domain will be turned on before loading the bitstream and turned off while removing/unloading the bitstream using overlays. This can be achieved by adding the runtime PM support. Signed-off-by: Nava kishore Manne --- drivers/fpga/of-fpga-region.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c index e405309baadc..35fc2f3d4bd8 100644 --- a/drivers/fpga/of-fpga-region.c +++ b/drivers/fpga/of-fpga-region.c @@ -15,6 +15,7 @@ #include #include #include +#include static const struct of_device_id fpga_region_of_match[] = { { .compatible = "fpga-region", }, @@ -302,6 +303,7 @@ static int of_fpga_region_notify_pre_apply(struct fpga_region *region, } region->info = info; + pm_runtime_get_sync(dev->parent); ret = fpga_region_program_fpga(region); if (ret) { /* error; reject overlay */ @@ -324,10 +326,13 @@ static int of_fpga_region_notify_pre_apply(struct fpga_region *region, static void of_fpga_region_notify_post_remove(struct fpga_region *region, struct of_overlay_notify_data *nd) { + struct device *dev = ®ion->dev; + fpga_bridges_disable(®ion->bridge_list); fpga_bridges_put(®ion->bridge_list); fpga_image_info_free(region->info); region->info = NULL; + pm_runtime_put(dev->parent); } /** @@ -411,9 +416,16 @@ static int of_fpga_region_probe(struct platform_device *pdev) goto eprobe_mgr_put; } + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_get_sync(&pdev->dev); + if (ret < 0) + goto err_pm; + + pm_runtime_put(&pdev->dev); + ret = fpga_region_register(region); if (ret) - goto eprobe_mgr_put; + goto err_pm; of_platform_populate(np, fpga_region_of_match, NULL, ®ion->dev); platform_set_drvdata(pdev, region); @@ -422,6 +434,9 @@ static int of_fpga_region_probe(struct platform_device *pdev) return 0; +err_pm: + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); eprobe_mgr_put: fpga_mgr_put(mgr); return ret; @@ -434,6 +449,7 @@ static int of_fpga_region_remove(struct platform_device *pdev) fpga_region_unregister(region); fpga_mgr_put(mgr); + pm_runtime_disable(region->dev.parent); return 0; }