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Tue, 06 Apr 2021 04:36:32 -0700 (PDT) From: Fabien Parent To: Rob Herring , Matthias Brugger Cc: mkorpershoek@baylibre.com, Fabien Parent , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] arm64: dts: mediatek: mt8167: add larb nodes Date: Tue, 6 Apr 2021 13:36:28 +0200 Message-Id: <20210406113631.2675029-1-fparent@baylibre.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210406_123634_898336_BF7D3D7A X-CRM114-Status: GOOD ( 11.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add larb nodes for MT8167: * larb0 is used for display (dsi and hdmi) * larb1 is used for camera (csi) * larb2 is used for the video hardware decoder Signed-off-by: Fabien Parent --- Note: This series is based on https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.12-next/dts64-2 V3: * Removed unicode character in commit summary V2: * Removed unneeded mediatek,larb-id property arch/arm64/boot/dts/mediatek/mt8167.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 4b951f81db9e..bbddd4b22d3e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -140,5 +140,35 @@ smi_common: smi@14017000 { clock-names = "apb", "smi"; power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; + + larb0: larb@14016000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x14016000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + + larb1: larb@15001000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB1_SMI>, + <&imgsys CLK_IMG_LARB1_SMI>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; + }; + + larb2: larb@16010000 { + compatible = "mediatek,mt8167-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB1_CKEN>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; + }; }; }; From patchwork Tue Apr 6 11:36:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 12185001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-21.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99FADC433ED for ; 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Tue, 06 Apr 2021 04:36:34 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id k3sm11880735wrc.67.2021.04.06.04.36.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 04:36:34 -0700 (PDT) From: Fabien Parent To: Rob Herring , Matthias Brugger Cc: mkorpershoek@baylibre.com, Fabien Parent , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] arm64: dts: mediatek: mt8167: add iommu node Date: Tue, 6 Apr 2021 13:36:29 +0200 Message-Id: <20210406113631.2675029-2-fparent@baylibre.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210406113631.2675029-1-fparent@baylibre.com> References: <20210406113631.2675029-1-fparent@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210406_123636_233309_311F8E0E X-CRM114-Status: GOOD ( 11.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add node for the MT8167's IOMMU. Signed-off-by: Fabien Parent --- Note: This series is based on https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.12-next/dts64-2 V3: * Removed unicode character in commit summary V2: * Remove unneeded cell-index property arch/arm64/boot/dts/mediatek/mt8167.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index bbddd4b22d3e..9029051624a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -170,5 +170,13 @@ larb2: larb@16010000 { clock-names = "apb", "smi"; power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; }; + + iommu: m4u@10203000 { + compatible = "mediatek,mt8167-m4u"; + reg = <0 0x10203000 0 0x1000>; + mediatek,larbs = <&larb0 &larb1 &larb2>; + interrupts = ; + #iommu-cells = <1>; + }; }; }; From patchwork Tue Apr 6 11:36:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Parent X-Patchwork-Id: 12185009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-21.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E99CCC433ED for ; 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Tue, 06 Apr 2021 04:36:36 -0700 (PDT) Received: from localhost.localdomain ([88.160.162.107]) by smtp.gmail.com with ESMTPSA id k3sm11880735wrc.67.2021.04.06.04.36.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 04:36:35 -0700 (PDT) From: Fabien Parent To: Rob Herring , Matthias Brugger Cc: mkorpershoek@baylibre.com, Fabien Parent , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] arm64: dts: mediatek: mt8167: add some DRM nodes Date: Tue, 6 Apr 2021 13:36:30 +0200 Message-Id: <20210406113631.2675029-3-fparent@baylibre.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210406113631.2675029-1-fparent@baylibre.com> References: <20210406113631.2675029-1-fparent@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210406_123637_573896_DFBA9599 X-CRM114-Status: GOOD ( 12.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add all the DRM nodes required to get DSI to work on MT8167 SoC. Signed-off-by: Fabien Parent --- Note: This series is based on https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.12-next/dts64-2 V3: * Removed unicode character in commit summary V2: * No changes arch/arm64/boot/dts/mediatek/mt8167.dtsi | 149 +++++++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 9029051624a6..17942095944e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -16,6 +16,19 @@ / { compatible = "mediatek,mt8167"; + aliases { + aal0 = &aal; + ccorr0 = &ccorr; + color0 = &color; + dither0 = &dither; + dsi0 = &dsi; + ovl0 = &ovl0; + pwm0 = &disp_pwm; + rdma0 = &rdma0; + rdma1 = &rdma1; + wdma0 = &wdma; + }; + soc { topckgen: topckgen@10000000 { compatible = "mediatek,mt8167-topckgen", "syscon"; @@ -114,6 +127,13 @@ vdecsys: syscon@16000000 { #clock-cells = <1>; }; + mutex: mutex@14015000 { + compatible = "mediatek,mt8167-disp-mutex"; + reg = <0 0x14015000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + pio: pinctrl@1000b000 { compatible = "mediatek,mt8167-pinctrl"; reg = <0 0x1000b000 0 0x1000>; @@ -126,6 +146,135 @@ pio: pinctrl@1000b000 { interrupts = ; }; + rdma1: rdma1@1400a000 { + compatible = "mediatek,mt8167-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + }; + + disp_pwm: disp_pwm@1100f000 { + compatible = "mediatek,mt8167-disp-pwm", + "mediatek,mt8173-disp-pwn"; + reg = <0 0x1100f000 0 0x1000>; + #pwm-cells = <2>; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&topckgen CLK_TOP_PWM_MM>, + <&mmsys CLK_MM_DISP_PWM_26M>, + <&mmsys CLK_MM_DISP_PWM_MM>; + clock-names = "pwm_sel", + "pwm_mm", + "main", + "mm"; + status = "disabled"; + }; + + dsi: dsi@14012000 { + compatible = "mediatek,mt8167-dsi", + "mediatek,mt2701-dsi"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, + <&mmsys CLK_MM_DSI_DIGITAL>, + <&mipi_tx>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx>; + phy-names = "dphy"; + status = "disabled"; + }; + + mipi_tx: mipi_dphy@14018000 { + compatible = "mediatek,mt8167-mipi-tx", + "mediatek,mt2701-mipi-tx"; + reg = <0 0x14018000 0 0x90>; + clocks = <&topckgen CLK_TOP_MIPI_26M_DBG>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + ovl0: ovl0@14007000 { + compatible = "mediatek,mt8167-disp-ovl", + "mediatek,mt8173-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + mediatek,larb = <&larb0>; + }; + + rdma0: rdma0@14009000 { + compatible = "mediatek,mt8167-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,larb = <&larb0>; + }; + + color: color@1400c000 { + compatible = "mediatek,mt8167-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + ccorr: ccorr@1400d000 { + compatible = "mediatek,mt8167-disp-ccorr", + "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400d000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_CCORR>; + }; + + aal: aal@1400e000 { + compatible = "mediatek,mt8167-disp-aal"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_AAL>; + }; + + gamma: gamma@1400f000 { + compatible = "mediatek,mt8167-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_GAMMA>; + }; + + dither: dither@14010000 { + compatible = "mediatek,mt8167-disp-dither"; + reg = <0 0x14010000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_DITHER>; + }; + + wdma: wdma0@1400b000 { + compatible = "mediatek,mt8167-disp-wdma"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu M4U_PORT_DISP_WDMA0>; + mediatek,larb = <&larb0>; + }; + mmsys: mmsys@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>;