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Tue, 6 Apr 2021 15:32:59 +0000 From: quanyang.wang@windriver.com To: Michael Turquette , Stephen Boyd , Laurent Pinchart , Michal Simek Cc: Rajan Vaja , Jolly Shah , Greg Kroah-Hartman , Quanyang Wang , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [V3][PATCH] clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable Date: Tue, 6 Apr 2021 23:31:31 +0800 Message-Id: <20210406153131.601701-1-quanyang.wang@windriver.com> X-Mailer: git-send-email 2.25.1 X-Originating-IP: [60.247.85.82] X-ClientProxiedBy: BYAPR08CA0002.namprd08.prod.outlook.com (2603:10b6:a03:100::15) To CY4PR11MB0071.namprd11.prod.outlook.com (2603:10b6:910:7a::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from pek-qwang2-d1.wrs.com (60.247.85.82) by BYAPR08CA0002.namprd08.prod.outlook.com (2603:10b6:a03:100::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4020.16 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: ImVd6MQfgTAnZMUZoxIFf/kbRMB9DSh2VEnSxrRc+eFygqz+siEw2T8uaB6UZZLCIWExIQ5ZYEWTZqOS9iy3ilj+FS+TSmNvX4Ni+/lXpD1sxs6KuPcVsnfeSkGwM1q1pWAydwZG2pkSupPoXT1NnHJbY9LddLYX2x6ENM/tMTZAlP4F1o7qPrJovaiuRsD+fskJU40N83oa1s/VgvMky2/YUOzsujdkNB4R1p3DkxRHfqB7SVfzIqmvdWtB08L366nbYDXOm84N9t/BwlV7CQqa0YHtCHmi5Q3m9WPrTTpZErmWfn7aSQkkLHhItUOhiXdbXp6dIuOFI+3avYb/ZDozxkT57ATsYsF/Cr//+c7XiNNhTKuid9UwzuchOwW3FWEwL/juva6AWzv3y3LC5fMat+qAPDjqFcgarvHIDwLU068OgHQ1SXtUCFLpvhquLZq9Itci+hGSClUwdGqcT2b1epSuLTa5ZlbhKPIHFhNBJcDsoe+S4+npTp1/S3alVdbyxnuBQdj0Lh2Snu6/CWRvLgLeHpoV4Lt4nj8eF+IdmODQHPRYLQOuGN38L2TBTvcEbuaXzad4poFEfdcQxLotKaSdroHfeJYfkCzustlWilu6Px7vNhEiIDrgM4gA7ErpC3LCpI/bGRuTA2H8VBtElmbcvXgq74iI7OM4rUCqdF/zg8CxKepjZfdRWU8x+Gpe+SUSrEcXNuak9wTBn6k0JH5mM/VSuf8EH5/EEuRkhJR7ovv7QwUYXARbOSZVNnI/qr6SiDNtUjyvQnlw5BEDnXLAPm/G6VdVCdoWpdqsZRyKAzrnPCGn0OWUQV7fWU02lLILZZUwKFxLPGiZiFqDaq2GwHFLqeS4Fm8dIFrrso2XQmiuaxv1UnWvF/JSqD1kizxYf7HrJDR7SF26fyfDMzSG+yb+uIbio3xg8QBtiwSIC2MRYZGt5yOgnVdLVT5Gzifo1UDgdQsMQZdcth6v4bY01W/xAEch0ZclBqrGsOmfU8zeCyR5nU1R8h+tHGywf4CzXSvqZ7V8awcCl39PKmyv9fC4kk5EQlNKwfZBBiZ1jp6qHXrI61J76jf9zJSMcu67E5LNc+4aUWiRYeBJruMqXGEOw0nbw2aioLp1ckNICMXOEP9FmduYUoIqqrXHRR4u7ap259FVpm93/NQlVJPPvnpsXlzEConI4ZZ1r+zkweR1Mh5JdO6PBZH00CLQhWozOTgj081eUxvPnM7khx4jWS74uA287Sy0I3KCfUFjPwPjw5y39fy5O17iTyPiRxS9thn4OgYGs21U/pyGzAHB5HkuD71sLfPYQgJiO38ExjWZKSnBYLXltf+y X-OriginatorOrg: windriver.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5b5b441b-fb2a-460e-377f-08d8f91141c5 X-MS-Exchange-CrossTenant-AuthSource: CY4PR11MB0071.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2021 15:32:59.0786 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 8ddb2873-a1ad-4a18-ae4e-4644631433be X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Je0qS4ahOw/RQRvPAb8EoY9F0Ej0uNoTB72WTQT3SOgS37F/4BHGe5xS6W4sEaUtPqu8yg6skx5/RPbBrZGKf5sDZpBPnMKZV/Yaa0ZIznQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR11MB2008 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Quanyang Wang If there is a IOCTL_SET_PLL_FRAC_MODE request sent to ATF ever, we shouldn't skip invoking PM_CLOCK_ENABLE fn even though this pll has been enabled. In ATF implementation, it will only assign the mode to the variable (struct pm_pll *)pll->mode when handling IOCTL_SET_PLL_FRAC_MODE call. Invoking PM_CLOCK_ENABLE can force ATF send request to PWU to set the pll mode to PLL's register. There is a scenario that happens in enabling VPLL_INT(clk_id:96): 1) VPLL_INT has been enabled during booting. 2) A driver calls clk_set_rate and according to the rate, the VPLL_INT should be set to FRAC mode. Then zynqmp_pll_set_mode is called to pass IOCTL_SET_PLL_FRAC_MODE to ATF. Note that at this point ATF just stores the mode to a variable. 3) This driver calls clk_prepare_enable and zynqmp_pll_enable is called to try to enable VPLL_INT pll. Because of 1), the function zynqmp_pll_enable just returns without doing anything after checking that this pll has been enabled. In the scenario above, the pll mode of VPLL_INT will never be set successfully. So adding set_pll_mode to check condition to fix it. Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Quanyang Wang Tested-by: Laurent Pinchart --- V3: - add Fixes tag. V2: - add Tested-by tag, thanks Laurent. - fix typos in commit message and multiline code comments. --- drivers/clk/zynqmp/pll.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index 92f449ed38e5..0d64268a4a84 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -14,10 +14,12 @@ * struct zynqmp_pll - PLL clock * @hw: Handle between common and hardware-specific interfaces * @clk_id: PLL clock ID + * @set_pll_mode: Whether an IOCTL_SET_PLL_FRAC_MODE request be sent to ATF */ struct zynqmp_pll { struct clk_hw hw; u32 clk_id; + bool set_pll_mode; }; #define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw) @@ -81,6 +83,8 @@ static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on) if (ret) pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n", __func__, clk_name, ret); + else + clk->set_pll_mode = true; } /** @@ -240,9 +244,15 @@ static int zynqmp_pll_enable(struct clk_hw *hw) u32 clk_id = clk->clk_id; int ret; - if (zynqmp_pll_is_enabled(hw)) + /* + * Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request + * that has been sent to ATF. + */ + if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode)) return 0; + clk->set_pll_mode = false; + ret = zynqmp_pm_clock_enable(clk_id); if (ret) pr_warn_once("%s() clock enable failed for %s, ret = %d\n",