From patchwork Thu Apr 8 18:57:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12192315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18138C433ED for ; Thu, 8 Apr 2021 18:57:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E982861055 for ; Thu, 8 Apr 2021 18:57:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232919AbhDHS56 (ORCPT ); Thu, 8 Apr 2021 14:57:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231676AbhDHS55 (ORCPT ); Thu, 8 Apr 2021 14:57:57 -0400 Received: from mail-out.m-online.net (mail-out.m-online.net [IPv6:2001:a60:0:28:0:1:25:1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22322C061761 for ; Thu, 8 Apr 2021 11:57:46 -0700 (PDT) Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FGVrS6c6Jz1s0tT; Thu, 8 Apr 2021 20:57:44 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FGVrS6B6zz1sP6L; Thu, 8 Apr 2021 20:57:44 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id tXPFZTZEgpD8; Thu, 8 Apr 2021 20:57:42 +0200 (CEST) X-Auth-Info: p5cMduAmyOqEn8MAeK5uyJwgZkRL6v4PETODEROFxhg= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 8 Apr 2021 20:57:42 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 1/7] clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clock Date: Thu, 8 Apr 2021 20:57:25 +0200 Message-Id: <20210408185731.135511-2-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408185731.135511-1-marex@denx.de> References: <20210408185731.135511-1-marex@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The ETHCK_K are modeled as composite clock of MUX and GATE, however per STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet, ETHPTPDIV divider is attached past the ETHCK_K mux, and ETH_CLK/eth_clk_fb clock are output past ETHCKEN gate. Therefore, in case ETH_CLK/eth_clk_fb are not in use AND PTP clock are in use, ETHCKEN gate can be turned off. Current driver does not permit that, fix it. This patch converts ETHCK_K from composite clock into a ETHCKEN gate, ETHPTP_K from composite clock into ETHPTPDIV divider, and adds another NO_ID clock "ck_ker_eth" which models the ETHSRC mux and is parent clock to both ETHCK_K and ETHPTP_K. Therefore, all references to ETHCK_K and ETHPTP_K remain functional as before. [1] STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet https://www.st.com/resource/en/reference_manual/dm00327659-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- drivers/clk/clk-stm32mp1.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index a875649df8b8..a7c7f544ee5d 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -1949,7 +1949,6 @@ static const struct clock_config stm32mp1_clock_cfg[] = { KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI), KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1), KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO), - KCLK(ETHCK_K, "ethck_k", eth_src, 0, G_ETHCK, M_ETHCK), /* Particulary Kernel Clocks (no mux or no gate) */ MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM), @@ -1958,11 +1957,16 @@ static const struct clock_config stm32mp1_clock_cfg[] = { MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU), MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12), - COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE | + COMPOSITE(NO_ID, "ck_ker_eth", eth_src, CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT, _NO_GATE, _MMUX(M_ETHCK), - _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)), + _NO_DIV), + + MGATE_MP1(ETHCK_K, "ethck_k", "ck_ker_eth", 0, G_ETHCK), + + DIV(ETHPTP_K, "ethptp_k", "ck_ker_eth", CLK_OPS_PARENT_ENABLE | + CLK_SET_RATE_NO_REPARENT, RCC_ETHCKSELR, 4, 4, 0), /* RTC clock */ DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0), From patchwork Thu Apr 8 18:57:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12192317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F8DBC433B4 for ; Thu, 8 Apr 2021 18:57:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6281461041 for ; Thu, 8 Apr 2021 18:57:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232941AbhDHS6A (ORCPT ); Thu, 8 Apr 2021 14:58:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231676AbhDHS6A (ORCPT ); Thu, 8 Apr 2021 14:58:00 -0400 Received: from mail-out.m-online.net (mail-out.m-online.net [IPv6:2001:a60:0:28:0:1:25:1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A3E4C061760 for ; Thu, 8 Apr 2021 11:57:48 -0700 (PDT) Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FGVrV6BKcz1s1JW; Thu, 8 Apr 2021 20:57:46 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FGVrV55gFz1sP6L; Thu, 8 Apr 2021 20:57:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id LiaVNAZLBKFU; Thu, 8 Apr 2021 20:57:45 +0200 (CEST) X-Auth-Info: mKSswWMJwBizmZOvUfcTfxruhPUJhso+JrJkQB+c8pk= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 8 Apr 2021 20:57:44 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/7] clk: stm32mp1: The dev is always NULL, replace it with np Date: Thu, 8 Apr 2021 20:57:26 +0200 Message-Id: <20210408185731.135511-3-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408185731.135511-1-marex@denx.de> References: <20210408185731.135511-1-marex@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Instead of passing around $dev to all the registration functions, which is always NULL, pass around struct device_node pointer $np. This way it is possible to use of_clk_hw_register*() functions and/or register clock with associated $np pointer. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- drivers/clk/clk-stm32mp1.c | 56 +++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index a7c7f544ee5d..cf5a1d055c5a 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -317,7 +317,7 @@ struct clock_config { int num_parents; unsigned long flags; void *cfg; - struct clk_hw * (*func)(struct device *dev, + struct clk_hw * (*func)(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg); @@ -377,14 +377,14 @@ struct stm32_composite_cfg { }; static struct clk_hw * -_clk_hw_register_gate(struct device *dev, +_clk_hw_register_gate(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct gate_cfg *gate_cfg = cfg->cfg; - return clk_hw_register_gate(dev, + return clk_hw_register_gate(NULL, cfg->name, cfg->parent_name, cfg->flags, @@ -395,27 +395,27 @@ _clk_hw_register_gate(struct device *dev, } static struct clk_hw * -_clk_hw_register_fixed_factor(struct device *dev, +_clk_hw_register_fixed_factor(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct fixed_factor_cfg *ff_cfg = cfg->cfg; - return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name, + return clk_hw_register_fixed_factor(NULL, cfg->name, cfg->parent_name, cfg->flags, ff_cfg->mult, ff_cfg->div); } static struct clk_hw * -_clk_hw_register_divider_table(struct device *dev, +_clk_hw_register_divider_table(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct div_cfg *div_cfg = cfg->cfg; - return clk_hw_register_divider_table(dev, + return clk_hw_register_divider_table(NULL, cfg->name, cfg->parent_name, cfg->flags, @@ -428,14 +428,14 @@ _clk_hw_register_divider_table(struct device *dev, } static struct clk_hw * -_clk_hw_register_mux(struct device *dev, +_clk_hw_register_mux(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct mux_cfg *mux_cfg = cfg->cfg; - return clk_hw_register_mux(dev, cfg->name, cfg->parent_names, + return clk_hw_register_mux(NULL, cfg->name, cfg->parent_names, cfg->num_parents, cfg->flags, mux_cfg->reg_off + base, mux_cfg->shift, mux_cfg->width, mux_cfg->mux_flags, lock); @@ -570,7 +570,7 @@ _get_stm32_gate(void __iomem *base, } static struct clk_hw * -clk_stm32_register_gate_ops(struct device *dev, +clk_stm32_register_gate_ops(struct device_node *np, const char *name, const char *parent_name, unsigned long flags, @@ -598,7 +598,7 @@ clk_stm32_register_gate_ops(struct device *dev, hw->init = &init; - ret = clk_hw_register(dev, hw); + ret = clk_hw_register(NULL, hw); if (ret) hw = ERR_PTR(ret); @@ -606,7 +606,7 @@ clk_stm32_register_gate_ops(struct device *dev, } static struct clk_hw * -clk_stm32_register_composite(struct device *dev, +clk_stm32_register_composite(struct device_node *np, const char *name, const char * const *parent_names, int num_parents, void __iomem *base, const struct stm32_composite_cfg *cfg, @@ -655,7 +655,7 @@ clk_stm32_register_composite(struct device *dev, } } - return clk_hw_register_composite(dev, name, parent_names, num_parents, + return clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, mux_ops, div_hw, div_ops, gate_hw, gate_ops, flags); } @@ -863,7 +863,7 @@ static const struct clk_ops pll_ops = { .is_enabled = pll_is_enabled, }; -static struct clk_hw *clk_register_pll(struct device *dev, const char *name, +static struct clk_hw *clk_register_pll(struct device_node *np, const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, @@ -889,7 +889,7 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name, element->lock = lock; hw = &element->hw; - err = clk_hw_register(dev, hw); + err = clk_hw_register(NULL, hw); if (err) { kfree(element); @@ -993,7 +993,7 @@ static const struct clk_ops timer_ker_ops = { }; -static struct clk_hw *clk_register_cktim(struct device *dev, const char *name, +static struct clk_hw *clk_register_cktim(struct device_node *np, const char *name, const char *parent_name, unsigned long flags, void __iomem *apbdiv, @@ -1021,7 +1021,7 @@ static struct clk_hw *clk_register_cktim(struct device *dev, const char *name, tim_ker->timpre = timpre; hw = &tim_ker->hw; - err = clk_hw_register(dev, hw); + err = clk_hw_register(NULL, hw); if (err) { kfree(tim_ker); @@ -1035,14 +1035,14 @@ struct stm32_pll_cfg { u32 offset; }; -static struct clk_hw *_clk_register_pll(struct device *dev, +static struct clk_hw *_clk_register_pll(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg; - return clk_register_pll(dev, cfg->name, cfg->parent_name, + return clk_register_pll(np, cfg->name, cfg->parent_name, base + stm_pll_cfg->offset, cfg->flags, lock); } @@ -1051,25 +1051,25 @@ struct stm32_cktim_cfg { u32 offset_timpre; }; -static struct clk_hw *_clk_register_cktim(struct device *dev, +static struct clk_hw *_clk_register_cktim(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct stm32_cktim_cfg *cktim_cfg = cfg->cfg; - return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags, + return clk_register_cktim(np, cfg->name, cfg->parent_name, cfg->flags, cktim_cfg->offset_apbdiv + base, cktim_cfg->offset_timpre + base, lock); } static struct clk_hw * -_clk_stm32_register_gate(struct device *dev, +_clk_stm32_register_gate(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { - return clk_stm32_register_gate_ops(dev, + return clk_stm32_register_gate_ops(np, cfg->name, cfg->parent_name, cfg->flags, @@ -1079,12 +1079,12 @@ _clk_stm32_register_gate(struct device *dev, } static struct clk_hw * -_clk_stm32_register_composite(struct device *dev, +_clk_stm32_register_composite(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { - return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names, + return clk_stm32_register_composite(np, cfg->name, cfg->parent_names, cfg->num_parents, base, cfg->cfg, cfg->flags, lock); } @@ -2020,7 +2020,7 @@ static const struct of_device_id stm32mp1_match_data[] = { { } }; -static int stm32_register_hw_clk(struct device *dev, +static int stm32_register_hw_clk(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) @@ -2031,7 +2031,7 @@ static int stm32_register_hw_clk(struct device *dev, hws = clk_data->hws; if (cfg->func) - hw = (*cfg->func)(dev, clk_data, base, lock, cfg); + hw = (*cfg->func)(np, clk_data, base, lock, cfg); if (IS_ERR(hw)) { pr_err("Unable to register %s\n", cfg->name); @@ -2077,7 +2077,7 @@ static int stm32_rcc_init(struct device_node *np, hws[n] = ERR_PTR(-ENOENT); for (n = 0; n < data->num; n++) { - err = stm32_register_hw_clk(NULL, clk_data, base, &rlock, + err = stm32_register_hw_clk(np, clk_data, base, &rlock, &data->cfg[n]); if (err) { pr_err("%s: can't register %s\n", __func__, From patchwork Thu Apr 8 18:57:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12192319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A399C433ED for ; Thu, 8 Apr 2021 18:57:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 271D161041 for ; Thu, 8 Apr 2021 18:57:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232942AbhDHS6C (ORCPT ); Thu, 8 Apr 2021 14:58:02 -0400 Received: from mail-out.m-online.net ([212.18.0.9]:33355 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231676AbhDHS6B (ORCPT ); Thu, 8 Apr 2021 14:58:01 -0400 Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FGVrX3fPHz1qs3X; Thu, 8 Apr 2021 20:57:48 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FGVrX3FwZz1sP6L; Thu, 8 Apr 2021 20:57:48 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id yKdnRZjQGlhH; Thu, 8 Apr 2021 20:57:46 +0200 (CEST) X-Auth-Info: cl6Qrnir4ogKBLWSnkIvFaukjculI3dZHSOpLRTSF1A= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 8 Apr 2021 20:57:46 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 3/7] clk: stm32mp1: Register clock with device_node pointer Date: Thu, 8 Apr 2021 20:57:27 +0200 Message-Id: <20210408185731.135511-4-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408185731.135511-1-marex@denx.de> References: <20210408185731.135511-1-marex@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Use of_clk_hw_register() where applicable to associate device_node with the newly registered clock, elsewhere use functions which permit passing the device node to newly registered clock. There are two exceptions, _clk_hw_register_fixed_factor() does not pass the device_node pointer to new fixed factor clock and neither does clk_stm32_register_composite(), because there is so far no way to do that. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- NOTE: But if this patch is acceptable, the _clk_hw_register_fixed_factor() and clk_stm32_register_composite() can be easily fixed up too. --- drivers/clk/clk-stm32mp1.c | 44 ++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index cf5a1d055c5a..85bba1ee5fbd 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -384,14 +384,11 @@ _clk_hw_register_gate(struct device_node *np, { struct gate_cfg *gate_cfg = cfg->cfg; - return clk_hw_register_gate(NULL, - cfg->name, - cfg->parent_name, - cfg->flags, - gate_cfg->reg_off + base, - gate_cfg->bit_idx, - gate_cfg->gate_flags, - lock); + return __clk_hw_register_gate(NULL, np, cfg->name, cfg->parent_name, + NULL, NULL, cfg->flags, + gate_cfg->reg_off + base, + gate_cfg->bit_idx, + gate_cfg->gate_flags, lock); } static struct clk_hw * @@ -415,16 +412,12 @@ _clk_hw_register_divider_table(struct device_node *np, { struct div_cfg *div_cfg = cfg->cfg; - return clk_hw_register_divider_table(NULL, - cfg->name, - cfg->parent_name, - cfg->flags, - div_cfg->reg_off + base, - div_cfg->shift, - div_cfg->width, - div_cfg->div_flags, - div_cfg->table, - lock); + return __clk_hw_register_divider(NULL, np, cfg->name, cfg->parent_name, + NULL, NULL, cfg->flags, + div_cfg->reg_off + base, + div_cfg->shift, div_cfg->width, + div_cfg->div_flags, div_cfg->table, + lock); } static struct clk_hw * @@ -435,10 +428,11 @@ _clk_hw_register_mux(struct device_node *np, { struct mux_cfg *mux_cfg = cfg->cfg; - return clk_hw_register_mux(NULL, cfg->name, cfg->parent_names, - cfg->num_parents, cfg->flags, - mux_cfg->reg_off + base, mux_cfg->shift, - mux_cfg->width, mux_cfg->mux_flags, lock); + return __clk_hw_register_mux(NULL, np, cfg->name, cfg->num_parents, + cfg->parent_names, NULL, NULL, cfg->flags, + mux_cfg->reg_off + base, mux_cfg->shift, + BIT(mux_cfg->width) - 1, + mux_cfg->mux_flags, NULL, lock); } /* MP1 Gate clock with set & clear registers */ @@ -598,7 +592,7 @@ clk_stm32_register_gate_ops(struct device_node *np, hw->init = &init; - ret = clk_hw_register(NULL, hw); + ret = of_clk_hw_register(np, hw); if (ret) hw = ERR_PTR(ret); @@ -889,7 +883,7 @@ static struct clk_hw *clk_register_pll(struct device_node *np, const char *name, element->lock = lock; hw = &element->hw; - err = clk_hw_register(NULL, hw); + err = of_clk_hw_register(np, hw); if (err) { kfree(element); @@ -1021,7 +1015,7 @@ static struct clk_hw *clk_register_cktim(struct device_node *np, const char *nam tim_ker->timpre = timpre; hw = &tim_ker->hw; - err = clk_hw_register(NULL, hw); + err = of_clk_hw_register(np, hw); if (err) { kfree(tim_ker); From patchwork Thu Apr 8 18:57:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12192321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A0D4C43461 for ; Thu, 8 Apr 2021 18:57:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5035961041 for ; Thu, 8 Apr 2021 18:57:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232874AbhDHS6D (ORCPT ); Thu, 8 Apr 2021 14:58:03 -0400 Received: from mail-out.m-online.net ([212.18.0.9]:46310 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231676AbhDHS6D (ORCPT ); Thu, 8 Apr 2021 14:58:03 -0400 Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FGVrZ3slWz1qs3n; Thu, 8 Apr 2021 20:57:50 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FGVrZ3MQgz1sP6L; Thu, 8 Apr 2021 20:57:50 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id 38IfaBtYSKAk; Thu, 8 Apr 2021 20:57:48 +0200 (CEST) X-Auth-Info: J63wzc2qCa/aVLORef+YkWrrwZm7Uz9ZiA18D/Aqg/4= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 8 Apr 2021 20:57:48 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 4/7] clk: stm32mp1: Add parent_data to ETHRX clock Date: Thu, 8 Apr 2021 20:57:28 +0200 Message-Id: <20210408185731.135511-5-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408185731.135511-1-marex@denx.de> References: <20210408185731.135511-1-marex@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Pass parent_data to ETHRX clock with new fw_name = "ETH_RX_CLK/ETH_REF_CLK". By default, this change has no impact on the operation of the clock driver. However, due to the fw_name, it permits DT to override ETHRX clock parent, which might be needed in case the ETHRX clock are supplied by external clock source. Example of MCO2 supplying clock to ETH_RX_CLK via external pad-to-pad wire: &rcc { clocks = <&rcc CK_MCO2>; clock-names = "ETH_RX_CLK/ETH_REF_CLK"; }; Note that while this patch permits to implement this rare usecase, the issue with ethernet RX and TX input clock modeling on MP1 is far more complex and requires more core plumbing. [1] STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet https://www.st.com/resource/en/reference_manual/dm00327659-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- drivers/clk/clk-stm32mp1.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 85bba1ee5fbd..f9a9960945c6 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -152,6 +152,10 @@ static const char * const eth_src[] = { "pll4_p", "pll3_q" }; +const struct clk_parent_data ethrx_src[] = { + { .name = "ethck_k", .fw_name = "ETH_RX_CLK/ETH_REF_CLK" }, +}; + static const char * const rng_src[] = { "ck_csi", "pll4_r", "ck_lse", "ck_lsi" }; @@ -314,6 +318,7 @@ struct clock_config { const char *name; const char *parent_name; const char * const *parent_names; + const struct clk_parent_data *parent_data; int num_parents; unsigned long flags; void *cfg; @@ -567,6 +572,7 @@ static struct clk_hw * clk_stm32_register_gate_ops(struct device_node *np, const char *name, const char *parent_name, + const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *base, const struct stm32_gate_cfg *cfg, @@ -577,7 +583,10 @@ clk_stm32_register_gate_ops(struct device_node *np, int ret; init.name = name; - init.parent_names = &parent_name; + if (parent_name) + init.parent_names = &parent_name; + if (parent_data) + init.parent_data = parent_data; init.num_parents = 1; init.flags = flags; @@ -602,6 +611,7 @@ clk_stm32_register_gate_ops(struct device_node *np, static struct clk_hw * clk_stm32_register_composite(struct device_node *np, const char *name, const char * const *parent_names, + const struct clk_parent_data *parent_data, int num_parents, void __iomem *base, const struct stm32_composite_cfg *cfg, unsigned long flags, spinlock_t *lock) @@ -1066,6 +1076,7 @@ _clk_stm32_register_gate(struct device_node *np, return clk_stm32_register_gate_ops(np, cfg->name, cfg->parent_name, + cfg->parent_data, cfg->flags, base, cfg->cfg, @@ -1079,8 +1090,8 @@ _clk_stm32_register_composite(struct device_node *np, const struct clock_config *cfg) { return clk_stm32_register_composite(np, cfg->name, cfg->parent_names, - cfg->num_parents, base, cfg->cfg, - cfg->flags, lock); + cfg->parent_data, cfg->num_parents, + base, cfg->cfg, cfg->flags, lock); } #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ @@ -1187,6 +1198,16 @@ _clk_stm32_register_composite(struct device_node *np, .func = _clk_stm32_register_gate,\ } +#define STM32_GATE_PDATA(_id, _name, _parent, _flags, _gate)\ +{\ + .id = _id,\ + .name = _name,\ + .parent_data = _parent,\ + .flags = _flags,\ + .cfg = (struct stm32_gate_cfg *) {_gate},\ + .func = _clk_stm32_register_gate,\ +} + #define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\ (&(struct stm32_gate_cfg) {\ &(struct gate_cfg) {\ @@ -1220,6 +1241,10 @@ _clk_stm32_register_composite(struct device_node *np, STM32_GATE(_id, _name, _parent, _flags,\ _STM32_MGATE(_mgate)) +#define MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate)\ + STM32_GATE_PDATA(_id, _name, _parent, _flags,\ + _STM32_MGATE(_mgate)) + #define _STM32_DIV(_div_offset, _div_shift, _div_width,\ _div_flags, _div_table, _ops)\ .div = &(struct stm32_div_cfg) {\ @@ -1279,6 +1304,9 @@ _clk_stm32_register_composite(struct device_node *np, #define PCLK(_id, _name, _parent, _flags, _mgate)\ MGATE_MP1(_id, _name, _parent, _flags, _mgate) +#define PCLK_PDATA(_id, _name, _parent, _flags, _mgate)\ + MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate) + #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\ COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\ CLK_SET_RATE_NO_REPARENT | _flags,\ @@ -1886,7 +1914,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = { PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA), PCLK(GPU, "gpu", "ck_axi", 0, G_GPU), PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX), - PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX), + PCLK_PDATA(ETHRX, "ethrx", ethrx_src, 0, G_ETHRX), PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC), PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC), PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI), From patchwork Thu Apr 8 18:57:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12192323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07D35C433ED for ; Thu, 8 Apr 2021 18:57:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D310E61041 for ; Thu, 8 Apr 2021 18:57:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232951AbhDHS6E (ORCPT ); Thu, 8 Apr 2021 14:58:04 -0400 Received: from mail-out.m-online.net ([212.18.0.10]:58863 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231676AbhDHS6E (ORCPT ); Thu, 8 Apr 2021 14:58:04 -0400 Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FGVrc1MZrz1s0tQ; Thu, 8 Apr 2021 20:57:52 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FGVrc09JHz1sP6L; Thu, 8 Apr 2021 20:57:52 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id Z338hh1SwnAR; Thu, 8 Apr 2021 20:57:50 +0200 (CEST) X-Auth-Info: fLof6CmnyBaU687AIPkgOjxz+lIqhaGYviSmucAScZM= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 8 Apr 2021 20:57:50 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 5/7] ARM: dts: stm32: Add alternate pinmux for ethernet0 pins Date: Thu, 8 Apr 2021 20:57:29 +0200 Message-Id: <20210408185731.135511-6-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408185731.135511-1-marex@denx.de> References: <20210408185731.135511-1-marex@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add another mux option for ethernet0 pins, this is used on DHCOM when the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin and then fed back via PA1 pin. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 060baa8b7e9d..08ab62c9f254 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -305,6 +305,40 @@ pins1 { }; }; + ethernet0_rmii_pins_b: rmii-1 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ From patchwork Thu Apr 8 18:57:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12192325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A686C43470 for ; Thu, 8 Apr 2021 18:57:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6518561055 for ; Thu, 8 Apr 2021 18:57:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232959AbhDHS6G (ORCPT ); Thu, 8 Apr 2021 14:58:06 -0400 Received: from mail-out.m-online.net ([212.18.0.9]:47758 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231676AbhDHS6F (ORCPT ); Thu, 8 Apr 2021 14:58:05 -0400 Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FGVrd3hW4z1qs3X; Thu, 8 Apr 2021 20:57:53 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FGVrd3GQcz1sP6L; Thu, 8 Apr 2021 20:57:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id kKX1SwTWq4T4; Thu, 8 Apr 2021 20:57:52 +0200 (CEST) X-Auth-Info: PYUlD6ZuzpNhXpVYetA+iDOJFP1Yq4gYoeueKikx10o= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 8 Apr 2021 20:57:52 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 6/7] ARM: dts: stm32: Add alternate pinmux for mco2 pins Date: Thu, 8 Apr 2021 20:57:30 +0200 Message-Id: <20210408185731.135511-7-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408185731.135511-1-marex@denx.de> References: <20210408185731.135511-1-marex@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add pinmux option for MCO2 pin. This is used on DHCOM when the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 08ab62c9f254..f003c05c24c3 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -849,6 +849,21 @@ pins { }; }; + mco2_pins_a: mco2-0 { + pins { + pinmux = ; /* MCO2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + mco2_sleep_pins_a: mco2-sleep-0 { + pins { + pinmux = ; /* MCO2 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ From patchwork Thu Apr 8 18:57:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 12192327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1618BC433B4 for ; Thu, 8 Apr 2021 18:57:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CCCCB6100B for ; Thu, 8 Apr 2021 18:57:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232969AbhDHS6I (ORCPT ); Thu, 8 Apr 2021 14:58:08 -0400 Received: from mail-out.m-online.net ([212.18.0.10]:55324 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232950AbhDHS6H (ORCPT ); Thu, 8 Apr 2021 14:58:07 -0400 Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FGVrg0wR0z1s0tQ; Thu, 8 Apr 2021 20:57:55 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FGVrg0QdYz1sP6L; Thu, 8 Apr 2021 20:57:55 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id 3IhKjxWABGys; Thu, 8 Apr 2021 20:57:53 +0200 (CEST) X-Auth-Info: Y+oWh5Z/E83ZtGFhjgYSHn1lsHThtGGRawrfe9BsR4U= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 8 Apr 2021 20:57:53 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 7/7] ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM Date: Thu, 8 Apr 2021 20:57:31 +0200 Message-Id: <20210408185731.135511-8-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408185731.135511-1-marex@denx.de> References: <20210408185731.135511-1-marex@denx.de> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK pad for the PHY and the same 50 MHz clock are fed back to ETHRX via internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad using external pad-to-pad connection. Option (1) has two downsides. ETHCK_K is supplied directly from either PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and since the same PLL output is also used to supply SDMMC blocks, the performance of SD and eMMC access is affected. The second downside is that using this option, the EMI of the SoM is higher. Option (2) solves both of those problems, so implement it here. In this case, the PLL4_P is no longer limited and can be operated faster, at 100 MHz, which improves SDMMC performance (read performance is improved from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M count=1). The EMI interference also decreases. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 272a1a67a9ad..4c7c06a7aea0 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -114,15 +114,29 @@ &dts { status = "okay"; }; +&rcc { + /* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */ + clocks = <&rcc CK_MCO2>; + clock-names = "ETH_RX_CLK/ETH_REF_CLK"; + + /* + * Set PLL4P output to 100 MHz to supply SDMMC with faster clock, + * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2, + * so that MCO2 behaves as a divider for the ETHRX clock here. + */ + assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <50000000>, <100000000>; +}; + ðernet0 { status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-0 = <ðernet0_rmii_pins_b &mco2_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_b &mco2_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rmii"; max-speed = <100>; phy-handle = <&phy0>; - st,eth-ref-clk-sel; phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; mdio0 {