From patchwork Fri Apr 9 16:22:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 12194471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 013D8C433ED for ; Fri, 9 Apr 2021 16:32:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C3B186108B for ; Fri, 9 Apr 2021 16:32:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233957AbhDIQcx (ORCPT ); Fri, 9 Apr 2021 12:32:53 -0400 Received: from mx.socionext.com ([202.248.49.38]:3686 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233713AbhDIQcw (ORCPT ); Fri, 9 Apr 2021 12:32:52 -0400 Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 10 Apr 2021 01:22:28 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id 0BC432059027; Sat, 10 Apr 2021 01:22:29 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Sat, 10 Apr 2021 01:22:29 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan2.css.socionext.com (Postfix) with ESMTP id 63620B1D40; Sat, 10 Apr 2021 01:22:28 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Marc Zyngier Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jassi Brar , Masami Hiramatsu , Kunihiko Hayashi Subject: [PATCH v10 1/3] PCI: portdrv: Add pcie_port_service_get_irq() function Date: Sat, 10 Apr 2021 01:22:16 +0900 Message-Id: <1617985338-19648-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617985338-19648-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1617985338-19648-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add pcie_port_service_get_irq() that returns the virtual IRQ number for specified portdrv service. Cc: Lorenzo Pieralisi Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring Acked-by: Bjorn Helgaas --- drivers/pci/pcie/portdrv.h | 1 + drivers/pci/pcie/portdrv_core.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) 2.7.4 diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 2ff5724..628a3de 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -144,4 +144,5 @@ static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {} #endif /* !CONFIG_PCIE_PME */ struct device *pcie_port_find_device(struct pci_dev *dev, u32 service); +int pcie_port_service_get_irq(struct pci_dev *dev, u32 service); #endif /* _PORTDRV_H_ */ diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index e1fed664..b60f0f3 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -477,7 +477,22 @@ struct device *pcie_port_find_device(struct pci_dev *dev, } EXPORT_SYMBOL_GPL(pcie_port_find_device); +/* + * pcie_port_service_get_irq - get irq of the service + * @dev: PCI Express port the service is associated with + * @service: For the service to find + * + * Get IRQ number associated with given service on a pci_dev. + */ +int pcie_port_service_get_irq(struct pci_dev *dev, u32 service) +{ + struct pcie_device *pciedev; + + pciedev = to_pcie_device(pcie_port_find_device(dev, service)); + + return pciedev->irq; +} + /** * pcie_port_device_remove - unregister PCI Express port service devices * @dev: PCI Express port the service devices to unregister are associated with -- From patchwork Fri Apr 9 16:22:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 12194475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 257CAC433B4 for ; Fri, 9 Apr 2021 16:32:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D5FC2600EF for ; Fri, 9 Apr 2021 16:32:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233713AbhDIQdA (ORCPT ); Fri, 9 Apr 2021 12:33:00 -0400 Received: from mx.socionext.com ([202.248.49.38]:3688 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233978AbhDIQdA (ORCPT ); Fri, 9 Apr 2021 12:33:00 -0400 Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 10 Apr 2021 01:22:29 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id 8972C2059027; Sat, 10 Apr 2021 01:22:29 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Sat, 10 Apr 2021 01:22:29 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan2.css.socionext.com (Postfix) with ESMTP id 30F7BB1D40; Sat, 10 Apr 2021 01:22:29 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Marc Zyngier Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jassi Brar , Masami Hiramatsu , Kunihiko Hayashi Subject: [PATCH v10 2/3] PCI: dwc: Add msi_host_isr() callback Date: Sat, 10 Apr 2021 01:22:17 +0900 Message-Id: <1617985338-19648-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617985338-19648-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1617985338-19648-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This adds msi_host_isr() callback function support to describe SoC-dependent service triggered by MSI. For example, when AER interrupt is triggered by MSI, the callback function reads SoC-dependent registers and detects that the interrupt is from AER, and invoke AER interrupts related to MSI. Cc: Marc Zyngier Cc: Jingoo Han Cc: Gustavo Pimentel Signed-off-by: Kunihiko Hayashi Acked-by: Gustavo Pimentel Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 7e55b2b..3cc6311 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -61,6 +61,9 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) irqreturn_t ret = IRQ_NONE; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + if (pp->ops->msi_host_isr) + pp->ops->msi_host_isr(pp); + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; for (i = 0; i < num_ctrls; i++) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 7247c8b..3c15909 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -175,6 +175,7 @@ enum dw_pcie_device_mode { struct dw_pcie_host_ops { int (*host_init)(struct pcie_port *pp); int (*msi_host_init)(struct pcie_port *pp); + void (*msi_host_isr)(struct pcie_port *pp); }; struct pcie_port { From patchwork Fri Apr 9 16:22:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 12194469 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F070CC433B4 for ; Fri, 9 Apr 2021 16:32:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B583C600EF for ; Fri, 9 Apr 2021 16:32:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232642AbhDIQcu (ORCPT ); Fri, 9 Apr 2021 12:32:50 -0400 Received: from mx.socionext.com ([202.248.49.38]:3685 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229665AbhDIQct (ORCPT ); Fri, 9 Apr 2021 12:32:49 -0400 X-Greylist: delayed 605 seconds by postgrey-1.27 at vger.kernel.org; Fri, 09 Apr 2021 12:32:49 EDT Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 10 Apr 2021 01:22:30 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id 455292059027; Sat, 10 Apr 2021 01:22:30 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Sat, 10 Apr 2021 01:22:30 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan2.css.socionext.com (Postfix) with ESMTP id EFEC1B1D40; Sat, 10 Apr 2021 01:22:29 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Marc Zyngier Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jassi Brar , Masami Hiramatsu , Kunihiko Hayashi Subject: [PATCH v10 3/3] PCI: uniphier: Add misc interrupt handler to invoke PME and AER Date: Sat, 10 Apr 2021 01:22:18 +0900 Message-Id: <1617985338-19648-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617985338-19648-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1617985338-19648-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch adds misc interrupt handler to detect and invoke PME/AER event. In UniPhier PCIe controller, PME/AER signals are assigned to the same signal as MSI by the internal logic. These signals should be detected by the internal register, however, DWC MSI handler can't handle these signals. DWC MSI handler calls .msi_host_isr() callback function, that detects PME/AER signals using the internal register and invokes the interrupt with PME/AER vIRQ numbers. These vIRQ numbers is obtained by uniphier_pcie_port_get_irq() function, that finds the device that matches PME/AER from the devices associated with Root Port, and returns its vIRQ number. Cc: Marc Zyngier Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-uniphier.c | 101 +++++++++++++++++++++++++---- 1 file changed, 89 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 7e8bad3..bc4db6f 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -21,6 +21,7 @@ #include #include "pcie-designware.h" +#include "../../pcie/portdrv.h" #define PCL_PINCTRL0 0x002c #define PCL_PERST_PLDN_REGEN BIT(12) @@ -44,7 +45,9 @@ #define PCL_SYS_AUX_PWR_DET BIT(8) #define PCL_RCV_INT 0x8108 +#define PCL_RCV_INT_ALL_INT_MASK GENMASK(28, 25) #define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17) +#define PCL_RCV_INT_ALL_MSI_MASK GENMASK(12, 9) #define PCL_CFG_BW_MGT_STATUS BIT(4) #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3) #define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2) @@ -68,6 +71,8 @@ struct uniphier_pcie_priv { struct reset_control *rst; struct phy *phy; struct irq_domain *legacy_irq_domain; + int aer_irq; + int pme_irq; }; #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev) @@ -164,7 +169,15 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci) static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv) { - writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT); + u32 val; + + val = PCL_RCV_INT_ALL_ENABLE; + if (pci_msi_enabled()) + val |= PCL_RCV_INT_ALL_INT_MASK; + else + val |= PCL_RCV_INT_ALL_MSI_MASK; + + writel(val, priv->base + PCL_RCV_INT); writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX); } @@ -228,28 +241,51 @@ static const struct irq_domain_ops uniphier_intx_domain_ops = { .map = uniphier_pcie_intx_map, }; -static void uniphier_pcie_irq_handler(struct irq_desc *desc) +static void uniphier_pcie_misc_isr(struct pcie_port *pp, bool is_msi) { - struct pcie_port *pp = irq_desc_get_handler_data(desc); struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); - struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned long reg; - u32 val, bit, virq; + u32 val; - /* INT for debug */ val = readl(priv->base + PCL_RCV_INT); if (val & PCL_CFG_BW_MGT_STATUS) dev_dbg(pci->dev, "Link Bandwidth Management Event\n"); if (val & PCL_CFG_LINK_AUTO_BW_STATUS) dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n"); - if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) - dev_dbg(pci->dev, "Root Error\n"); - if (val & PCL_CFG_PME_MSI_STATUS) - dev_dbg(pci->dev, "PME Interrupt\n"); + + if (is_msi) { + if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) { + dev_dbg(pci->dev, "Root Error Status\n"); + if (priv->aer_irq) + generic_handle_irq(priv->aer_irq); + } + + if (val & PCL_CFG_PME_MSI_STATUS) { + dev_dbg(pci->dev, "PME Interrupt\n"); + if (priv->pme_irq) + generic_handle_irq(priv->pme_irq); + } + } writel(val, priv->base + PCL_RCV_INT); +} + +static void uniphier_pcie_msi_host_isr(struct pcie_port *pp) +{ + uniphier_pcie_misc_isr(pp, true); +} + +static void uniphier_pcie_irq_handler(struct irq_desc *desc) +{ + struct pcie_port *pp = irq_desc_get_handler_data(desc); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long reg; + u32 val, bit, virq; + + uniphier_pcie_misc_isr(pp, false); /* INTx */ chained_irq_enter(chip, desc); @@ -317,8 +353,45 @@ static int uniphier_pcie_host_init(struct pcie_port *pp) return 0; } +static int uniphier_pcie_port_get_irq(struct pcie_port *pp, u32 service) +{ + struct pci_dev *pcidev; + int irq = 0; + + if (!IS_ENABLED(CONFIG_PCIEAER) && !IS_ENABLED(CONFIG_PCIE_PME)) + return 0; + + /* + * Finds the device that matches 'service' from the devices + * associated with Root Port, and returns its vIRQ number. + */ + list_for_each_entry(pcidev, &pp->bridge->bus->devices, bus_list) { + irq = pcie_port_service_get_irq(pcidev, service); + if (irq) + break; + } + + return irq; +} + +static int uniphier_pcie_host_init_complete(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); + + if (IS_ENABLED(CONFIG_PCIE_PME)) + priv->pme_irq = + uniphier_pcie_port_get_irq(pp, PCIE_PORT_SERVICE_PME); + if (IS_ENABLED(CONFIG_PCIEAER)) + priv->aer_irq = + uniphier_pcie_port_get_irq(pp, PCIE_PORT_SERVICE_AER); + + return 0; +} + static const struct dw_pcie_host_ops uniphier_pcie_host_ops = { .host_init = uniphier_pcie_host_init, + .msi_host_isr = uniphier_pcie_msi_host_isr, }; static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv) @@ -398,7 +471,11 @@ static int uniphier_pcie_probe(struct platform_device *pdev) priv->pci.pp.ops = &uniphier_pcie_host_ops; - return dw_pcie_host_init(&priv->pci.pp); + ret = dw_pcie_host_init(&priv->pci.pp); + if (ret) + return ret; + + return uniphier_pcie_host_init_complete(&priv->pci.pp); } static const struct of_device_id uniphier_pcie_match[] = {