From patchwork Thu Nov 22 18:39:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10694699 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 35FEC1926 for ; Thu, 22 Nov 2018 18:39:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 31D522CED5 for ; Thu, 22 Nov 2018 18:39:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 250692CEDB; Thu, 22 Nov 2018 18:39:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B22362CEF9 for ; Thu, 22 Nov 2018 18:39:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729400AbeKWFUW (ORCPT ); Fri, 23 Nov 2018 00:20:22 -0500 Received: from mail-lf1-f66.google.com ([209.85.167.66]:38567 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729652AbeKWFUW (ORCPT ); Fri, 23 Nov 2018 00:20:22 -0500 Received: by mail-lf1-f66.google.com with SMTP id p86so7150164lfg.5 for ; Thu, 22 Nov 2018 10:39:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=subject:from:to:references:organization:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=KG0pP74NvsqMG6H+tGCfruA/yxmbUS9d4iBkyYnv338=; b=aPijYIih+hHyuRLbkc7/bT+XR5Z/15Vj8e1UEbLdweNQAi8Sn4THiHZsYKcqoZvPK7 tZfpNqcWHntx5wiyQ41hOzLPYISPKa270G9ui14lwFN52n+BbzL/HAJHBSVhUQxWiZcR XKyhcSh8AOPNBm5aXdOXjEDToNRY7eHE6newTFOIvDMhXiyHVSImWuc3B1A3SRxDexNm 2Z+8D2hFtWDxWYk2eiv1VfMqL9DEL5R72xDgloqAMhV5d2aXt1QtpWbuwib4Qx7/138L dmHhJwYrl5HbX/7sm3mBMJvQAKUPlIbdkI009kkjCyBnj0znvTiqqpECYwkALYFHDer/ QBOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:from:to:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=KG0pP74NvsqMG6H+tGCfruA/yxmbUS9d4iBkyYnv338=; b=IJdGPsqvySs0AHWizoCcKeFfq0c+vy0tzrBWnHh/e4uQaUYbdC/qfdRLY/i9Aih33E JCv/X29kOxZ2dXL4o0R4HJFJJ+fun3JfiB7Uin3hMxsXyV+OAEsyTCQFidAMYvXhDEN6 +LEEQFiAZMaLFqFf0jsSNN4xe3xRre+xIlr3yu2lUFhLrlHcG5fOyQ8XkuETpCO9KOJc NHSvZjJiNjO/dx4jxhTxAFZggVJPbDrb4HinttwgFvZN+xYyEE+P0UX3hPfyrEUkCs/1 yUax8QNMG08DZ7Iiu1fbdaCApYeTB6QwafT7OxL1G5LsNdb2C0/VP/q+LuxEl+5ZzIFm n9nQ== X-Gm-Message-State: AGRZ1gLioparUoj0YITMWgZAYs7uS+UjbAfTYt+77FwcFGfDR6/78YAr RVwk8+hnhrFN9D9BB/YmnLGbxbakaAw= X-Google-Smtp-Source: AJdET5eu5S9qsDaJcyttRilaA1aU9IhBMcXIC6coh9AKU21kJzkiGDzBrn5O6nXAkJwoOpSE+l7e1w== X-Received: by 2002:a19:9904:: with SMTP id b4mr6917604lfe.95.1542911984418; Thu, 22 Nov 2018 10:39:44 -0800 (PST) Received: from wasted.cogentembedded.com ([31.173.85.10]) by smtp.gmail.com with ESMTPSA id f20-v6sm4294792ljk.33.2018.11.22.10.39.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Nov 2018 10:39:43 -0800 (PST) Subject: [PATCH 1/4] clk: renesas: rcar-gen3-cpg: factor out cpg_reg_modify() From: Sergei Shtylyov To: linux-renesas-soc@vger.kernel.org, Michael Turquette , Stephen Boyd , Geert Uytterhoeven , linux-clk@vger.kernel.org References: Organization: Cogent Embedded Message-ID: <8cca22f7-dbd7-2da0-2f58-e490982d2f6c@cogentembedded.com> Date: Thu, 22 Nov 2018 21:39:42 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-MW Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There's quite often repeated sequence of a CPG register read-modify-write, so it seems worth factoring it out into a function -- this saves 68 bytes of the object code already (AArch64 gcc 4.8.5) and will save more with the next patches... Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- drivers/clk/renesas/rcar-gen3-cpg.c | 37 ++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c @@ -30,6 +30,15 @@ #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ +static void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set) +{ + u32 val = readl(reg); + + val &= ~clear; + val |= set; + writel(val, reg); +}; + struct cpg_simple_notifier { struct notifier_block nb; void __iomem *reg; @@ -118,7 +127,6 @@ static int cpg_z_clk_set_rate(struct clk struct cpg_z_clk *zclk = to_z_clk(hw); unsigned int mult; unsigned int i; - u32 val, kick; /* Factor of 2 is for fixed divider */ mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); @@ -127,17 +135,14 @@ static int cpg_z_clk_set_rate(struct clk if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) return -EBUSY; - val = readl(zclk->reg) & ~zclk->mask; - val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask; - writel(val, zclk->reg); + cpg_reg_modify(zclk->reg, zclk->mask, + ((32 - mult) << __ffs(zclk->mask)) & zclk->mask); /* * Set KICK bit in FRQCRB to update hardware setting and wait for * clock change completion. */ - kick = readl(zclk->kick_reg); - kick |= CPG_FRQCRB_KICK; - writel(kick, zclk->kick_reg); + cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); /* * Note: There is no HW information about the worst case latency. @@ -262,12 +267,10 @@ static const struct sd_div_table cpg_sd_ static int cpg_sd_clock_enable(struct clk_hw *hw) { struct sd_clock *clock = to_sd_clock(hw); - u32 val = readl(clock->csn.reg); - - val &= ~(CPG_SD_STP_MASK); - val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK; - writel(val, clock->csn.reg); + cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK, + clock->div_table[clock->cur_div_idx].val & + CPG_SD_STP_MASK); return 0; } @@ -276,7 +279,7 @@ static void cpg_sd_clock_disable(struct { struct sd_clock *clock = to_sd_clock(hw); - writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg); + cpg_reg_modify(clock->csn.reg, 0, CPG_SD_STP_MASK); } static int cpg_sd_clock_is_enabled(struct clk_hw *hw) @@ -323,7 +326,6 @@ static int cpg_sd_clock_set_rate(struct { struct sd_clock *clock = to_sd_clock(hw); unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); - u32 val; unsigned int i; for (i = 0; i < clock->div_num; i++) @@ -335,10 +337,9 @@ static int cpg_sd_clock_set_rate(struct clock->cur_div_idx = i; - val = readl(clock->csn.reg); - val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK); - val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK); - writel(val, clock->csn.reg); + cpg_reg_modify(clock->csn.reg, CPG_SD_STP_MASK | CPG_SD_FC_MASK, + clock->div_table[i].val & + (CPG_SD_STP_MASK | CPG_SD_FC_MASK)); return 0; } From patchwork Thu Nov 22 18:41:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10694703 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EED0114DE for ; Thu, 22 Nov 2018 18:41:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E739E2CEF9 for ; Thu, 22 Nov 2018 18:41:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D09992CEFE; Thu, 22 Nov 2018 18:41:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5DD822CEFE for ; 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Thu, 22 Nov 2018 10:41:55 -0800 (PST) Subject: [PATCH 2/4] clk: renesas: rcar-gen3-cpg: add RPC clock From: Sergei Shtylyov To: linux-renesas-soc@vger.kernel.org, Michael Turquette , Stephen Boyd , Geert Uytterhoeven , linux-clk@vger.kernel.org References: Organization: Cogent Embedded Message-ID: <5aa01cae-28ff-efb5-bf4d-1994760ecb79@cogentembedded.com> Date: Thu, 22 Nov 2018 21:41:54 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-MW Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the RPC clock for the R-Car gen3 SoCs -- this clock is controlled by the RPCCKCR register on all the R-Car gen3 SoCs except V3M (R8A77970). Signed-off-by: Sergei Shtylyov --- drivers/clk/renesas/rcar-gen3-cpg.c | 118 ++++++++++++++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 2 2 files changed, 120 insertions(+) Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c @@ -409,6 +409,121 @@ free_clock: return clk; } +#define CPG_RPC_CKSTP2 BIT(9) +#define CPG_RPC_CKSTP BIT(8) +#define CPG_RPC_DIV_4_3_MASK GENMASK(4, 3) +#define CPG_RPC_DIV_2_0_MASK GENMASK(2, 0) + +struct rpc_clock { + struct clk_hw hw; + void __iomem *reg; +}; + +#define to_rpc_clock(_hw) container_of(_hw, struct rpc_clock, hw) + +static int cpg_rpc_clock_enable(struct clk_hw *hw) +{ + struct rpc_clock *clock = to_rpc_clock(hw); + + cpg_reg_modify(clock->reg, CPG_RPC_CKSTP, 0); + + return 0; +} + +static void cpg_rpc_clock_disable(struct clk_hw *hw) +{ + struct rpc_clock *clock = to_rpc_clock(hw); + + cpg_reg_modify(clock->reg, 0, CPG_RPC_CKSTP); +} + +static int cpg_rpc_clock_is_enabled(struct clk_hw *hw) +{ + struct rpc_clock *clock = to_rpc_clock(hw); + + return !(readl(clock->reg) & CPG_RPC_CKSTP); +} + +static unsigned long cpg_rpc_clock_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rpc_clock *clock = to_rpc_clock(hw); + u32 div = (readl(clock->reg) & CPG_RPC_DIV_2_0_MASK) + 1; + + return DIV_ROUND_CLOSEST(parent_rate, div); +} + +static unsigned int cpg_rpc_clock_calc_div(struct rpc_clock *clock, + unsigned long rate, + unsigned long parent_rate) +{ + unsigned int div; + + if (!rate) + rate = 1; + + div = ALIGN(DIV_ROUND_CLOSEST(parent_rate, rate), 2); + + return clamp_t(unsigned int, div, 2, 8); +} + +static long cpg_rpc_clock_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct rpc_clock *clock = to_rpc_clock(hw); + unsigned int div = cpg_rpc_clock_calc_div(clock, rate, *parent_rate); + + return DIV_ROUND_CLOSEST(*parent_rate, div); +} + +static int cpg_rpc_clock_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct rpc_clock *clock = to_rpc_clock(hw); + unsigned int div = cpg_rpc_clock_calc_div(clock, rate, parent_rate); + + cpg_reg_modify(clock->reg, CPG_RPC_DIV_2_0_MASK, div - 1); + + return 0; +} + +static const struct clk_ops cpg_rpc_clock_ops = { + .enable = cpg_rpc_clock_enable, + .disable = cpg_rpc_clock_disable, + .is_enabled = cpg_rpc_clock_is_enabled, + .recalc_rate = cpg_rpc_clock_recalc_rate, + .round_rate = cpg_rpc_clock_round_rate, + .set_rate = cpg_rpc_clock_set_rate, +}; + +static struct clk * __init cpg_rpc_clk_register(const struct cpg_core_clk *core, + void __iomem *base, + const char *parent_name) +{ + struct clk_init_data init; + struct rpc_clock *clock; + struct clk *clk; + + clock = kzalloc(sizeof(*clock), GFP_KERNEL); + if (!clock) + return ERR_PTR(-ENOMEM); + + init.name = core->name; + init.ops = &cpg_rpc_clock_ops; + init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; + init.parent_names = &parent_name; + init.num_parents = 1; + + clock->reg = base + CPG_RPCCKCR; + clock->hw.init = &init; + + clk = clk_register(NULL, &clock->hw); + if (IS_ERR(clk)) + kfree(clock); + + return clk; +} + static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; @@ -583,6 +698,9 @@ struct clk * __init rcar_gen3_cpg_clk_re } break; + case CLK_TYPE_GEN3_RPC: + return cpg_rpc_clk_register(core, base, __clk_get_name(parent)); + default: return ERR_PTR(-EINVAL); } Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.h +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h @@ -23,6 +23,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_Z2, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ + CLK_TYPE_GEN3_RPC, /* SoC specific definitions start here */ CLK_TYPE_GEN3_SOC_BASE, @@ -57,6 +58,7 @@ struct rcar_gen3_cpg_pll_config { u8 osc_prediv; }; +#define CPG_RPCCKCR 0x238 #define CPG_RCKCR 0x240 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, From patchwork Thu Nov 22 18:43:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10694707 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 848BA17FE for ; Thu, 22 Nov 2018 18:43:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7EBC32CEED for ; Thu, 22 Nov 2018 18:43:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7027A2CEFB; Thu, 22 Nov 2018 18:43:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0C3A62CEED for ; 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Thu, 22 Nov 2018 10:43:20 -0800 (PST) Subject: [PATCH 3/4] clk: renesas: rcar-gen3-cpg: add RPCD2 clock From: Sergei Shtylyov To: linux-renesas-soc@vger.kernel.org, Michael Turquette , Stephen Boyd , Geert Uytterhoeven , linux-clk@vger.kernel.org References: Organization: Cogent Embedded Message-ID: <71808cdc-c95b-8ba2-10aa-01f6a6af7cf1@cogentembedded.com> Date: Thu, 22 Nov 2018 21:43:19 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-MW Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the RPCD2 clock for the R-Car gen3 SoCs -- this clock is en/disabled via the RPCCKCR register on all the R-Car gen3 SoCs except V3M (R8A77970) and has a fixed divisor of 2 (applied to the RPC clock). Signed-off-by: Sergei Shtylyov --- drivers/clk/renesas/rcar-gen3-cpg.c | 87 ++++++++++++++++++++++++++++++++++++ drivers/clk/renesas/rcar-gen3-cpg.h | 1 2 files changed, 88 insertions(+) Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.c +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.c @@ -524,6 +524,89 @@ static struct clk * __init cpg_rpc_clk_r return clk; } +static int cpg_rpcd2_clock_enable(struct clk_hw *hw) +{ + struct rpc_clock *clock = to_rpc_clock(hw); + + cpg_reg_modify(clock->reg, CPG_RPC_CKSTP2, 0); + + return 0; +} + +static void cpg_rpcd2_clock_disable(struct clk_hw *hw) +{ + struct rpc_clock *clock = to_rpc_clock(hw); + + cpg_reg_modify(clock->reg, 0, CPG_RPC_CKSTP2); +} + +static int cpg_rpcd2_clock_is_enabled(struct clk_hw *hw) +{ + struct rpc_clock *clock = to_rpc_clock(hw); + + return !(readl(clock->reg) & CPG_RPC_CKSTP2); +} + +static unsigned long cpg_rpcd2_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate / 2; +} + +static long cpg_rpcd2_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return *parent_rate / 2; +} + +static int cpg_rpcd2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + /* + * We must report success but we can do so unconditionally because + * the round_rate() method returns values that ensure this call is + * a nop. + */ + return 0; +} + +static const struct clk_ops cpg_rpcd2_clock_ops = { + .enable = cpg_rpcd2_clock_enable, + .disable = cpg_rpcd2_clock_disable, + .is_enabled = cpg_rpcd2_clock_is_enabled, + .recalc_rate = cpg_rpcd2_recalc_rate, + .round_rate = cpg_rpcd2_round_rate, + .set_rate = cpg_rpcd2_set_rate, +}; + +static struct clk * __init cpg_rpcd2_clk_register(const struct cpg_core_clk *core, + void __iomem *base, + const char *parent_name) +{ + struct clk_init_data init; + struct rpc_clock *clock; + struct clk *clk; + + clock = kzalloc(sizeof(*clock), GFP_KERNEL); + if (!clock) + return ERR_PTR(-ENOMEM); + + init.name = core->name; + init.ops = &cpg_rpcd2_clock_ops; + init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; + init.parent_names = &parent_name; + init.num_parents = 1; + + clock->reg = base + CPG_RPCCKCR; + clock->hw.init = &init; + + clk = clk_register(NULL, &clock->hw); + if (IS_ERR(clk)) + kfree(clock); + + return clk; +} + static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; static unsigned int cpg_clk_extalr __initdata; @@ -701,6 +784,10 @@ struct clk * __init rcar_gen3_cpg_clk_re case CLK_TYPE_GEN3_RPC: return cpg_rpc_clk_register(core, base, __clk_get_name(parent)); + case CLK_TYPE_GEN3_RPCD2: + return cpg_rpcd2_clk_register(core, base, + __clk_get_name(parent)); + default: return ERR_PTR(-EINVAL); } Index: renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/rcar-gen3-cpg.h +++ renesas-drivers/drivers/clk/renesas/rcar-gen3-cpg.h @@ -24,6 +24,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ CLK_TYPE_GEN3_RPC, + CLK_TYPE_GEN3_RPCD2, /* SoC specific definitions start here */ CLK_TYPE_GEN3_SOC_BASE, From patchwork Thu Nov 22 18:45:14 2018 Content-Type: text/plain; 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Thu, 22 Nov 2018 10:45:15 -0800 (PST) Subject: [PATCH 4/4] clk: renesas: r8a77980-cpg-mssr: add RPC clocks From: Sergei Shtylyov To: linux-renesas-soc@vger.kernel.org, Michael Turquette , Stephen Boyd , Geert Uytterhoeven , linux-clk@vger.kernel.org References: Organization: Cogent Embedded Message-ID: <0e51165d-65cb-1522-3174-b63818180070@cogentembedded.com> Date: Thu, 22 Nov 2018 21:45:14 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-MW Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the RPCSRC internal clock on R-Car V3H (R8A77980) -- it's controlled by the RPCCKCR.DIV[4:3] on all the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field is different between SoCs. Add the RPC[D2] clocks (derived from this internal clock) and the RPC-IF module clock as well... Signed-off-by: Sergei Shtylyov --- drivers/clk/renesas/r8a77980-cpg-mssr.c | 40 +++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) Index: renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c =================================================================== --- renesas-drivers.orig/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -10,6 +10,7 @@ * Copyright (C) 2015 Glider bvba */ +#include #include #include #include @@ -21,6 +22,10 @@ #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" +enum r8a77980_clk_types { + CLK_TYPE_R8A77980_RPCSRC = CLK_TYPE_GEN3_SOC_BASE, +}; + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A77980_CLK_OSC, @@ -41,12 +46,17 @@ enum clk_ids { CLK_S2, CLK_S3, CLK_SDSRC, + CLK_RPCSRC, CLK_OCO, /* Module Clocks */ MOD_CLK_BASE }; +static const struct clk_div_table cpg_rpcsrc_div_table[] = { + { 2, 5 }, { 3, 6 }, { 0, 0 }, +}; + static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -65,8 +75,14 @@ static const struct cpg_core_clk r8a7798 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_R8A77980_RPCSRC, CLK_PLL1), DEF_RATE(".oco", CLK_OCO, 32768), + DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, + CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, + R8A77980_CLK_RPC), + /* Core Clock Outputs */ DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), @@ -164,6 +180,7 @@ static const struct mssr_mod_clk r8a7798 DEF_MOD("gpio1", 911, R8A77980_CLK_CP), DEF_MOD("gpio0", 912, R8A77980_CLK_CP), DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2), + DEF_MOD("rpc-if", 917, R8A77980_CLK_RPC), DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6), DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6), DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2), @@ -215,6 +232,27 @@ static int __init r8a77980_cpg_mssr_init return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); } +static struct clk * __init r8a77980_cpg_clk_register(struct device *dev, + const struct cpg_core_clk *core, const struct cpg_mssr_info *info, + struct clk **clks, void __iomem *base, + struct raw_notifier_head *notifiers) +{ + if (core->type == CLK_TYPE_R8A77980_RPCSRC) { + const struct clk *parent = clks[core->parent]; + + if (IS_ERR(parent)) + return ERR_CAST(parent); + + return clk_register_divider_table(NULL, core->name, + __clk_get_name(parent), 0, + base + CPG_RPCCKCR, 3, 2, 0, + cpg_rpcsrc_div_table, NULL); + } else { + return rcar_gen3_cpg_clk_register(dev, core, info, clks, base, + notifiers); + } +} + const struct cpg_mssr_info r8a77980_cpg_mssr_info __initconst = { /* Core Clocks */ .core_clks = r8a77980_core_clks, @@ -233,5 +271,5 @@ const struct cpg_mssr_info r8a77980_cpg_ /* Callbacks */ .init = r8a77980_cpg_mssr_init, - .cpg_clk_register = rcar_gen3_cpg_clk_register, + .cpg_clk_register = r8a77980_cpg_clk_register, };